projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* gencode.c (write_header): Add "insn" and "extension" arguments
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 enum op_types {
17 OP_UNKNOWN,
18 };
19
20 #ifdef DEBUG
21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
22 static void trace_output PARAMS ((enum op_types result));
23 static int init_text_p = 0;
24 static asection *text;
25 static bfd_vma text_start;
26 static bfd_vma text_end;
27 extern bfd *exec_bfd;
28
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
31 #endif
32
33 #ifndef SIZE_OPERANDS
34 #define SIZE_OPERANDS 16
35 #endif
36
37 #ifndef SIZE_VALUES
38 #define SIZE_VALUES 11
39 #endif
40
41 #ifndef SIZE_LOCATION
42 #define SIZE_LOCATION 40
43 #endif
44
45 static void
46 trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50 {
51 }
52
53 static void
54 trace_output (result)
55 enum op_types result;
56 {
57 }
58
59 #else
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
62 #endif
63
64 \f
65 /* mov imm8, dn */
66 void OP_8000 (insn, extension)
67 unsigned long insn, extension;
68 {
69 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
70 }
71
72 /* mov dm, dn */
73 void OP_80 (insn, extension)
74 unsigned long insn, extension;
75 {
76 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
77 }
78
79 /* mov dm, an */
80 void OP_F1E0 (insn, extension)
81 unsigned long insn, extension;
82 {
83 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
84 }
85
86 /* mov am, dn */
87 void OP_F1D0 (insn, extension)
88 unsigned long insn, extension;
89 {
90 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
91 }
92
93 /* mov imm8, an */
94 void OP_9000 (insn, extension)
95 unsigned long insn, extension;
96 {
97 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
98 }
99
100 /* mov am, an */
101 void OP_90 (insn, extension)
102 unsigned long insn, extension;
103 {
104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
105 }
106
107 /* mov sp, an */
108 void OP_3C (insn, extension)
109 unsigned long insn, extension;
110 {
111 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
112 }
113
114 /* mov am, sp */
115 void OP_F2F0 (insn, extension)
116 unsigned long insn, extension;
117 {
118 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
119 }
120
121 /* mov psw, dn */
122 void OP_F2E4 (insn, extension)
123 unsigned long insn, extension;
124 {
125 State.regs[REG_D0 + (insn & 0x3)] = PSW;
126 }
127
128 /* mov dm, psw */
129 void OP_F2F3 (insn, extension)
130 unsigned long insn, extension;
131 {
132 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
133 }
134
135 /* mov mdr, dn */
136 void OP_F2E0 (insn, extension)
137 unsigned long insn, extension;
138 {
139 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
140 }
141
142 /* mov dm, mdr */
143 void OP_F2F2 (insn, extension)
144 unsigned long insn, extension;
145 {
146 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
147 }
148
149 /* mov (am), dn */
150 void OP_70 (insn, extension)
151 unsigned long insn, extension;
152 {
153 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
154 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
155 }
156
157 /* mov (d8,am), dn */
158 void OP_F80000 (insn, extension)
159 unsigned long insn, extension;
160 {
161 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
162 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
163 + SEXT8 (insn & 0xff)), 4);
164 }
165
166 /* mov (d16,am), dn */
167 void OP_FA000000 (insn, extension)
168 unsigned long insn, extension;
169 {
170 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
171 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
172 + SEXT16 (insn & 0xffff)), 4);
173 }
174
175 /* mov (d32,am), dn */
176 void OP_FC000000 (insn, extension)
177 unsigned long insn, extension;
178 {
179 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
180 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
181 + ((insn & 0xffff) << 16) | extension), 4);
182 }
183
184 /* mov (d8,sp), dn */
185 void OP_5800 (insn, extension)
186 unsigned long insn, extension;
187 {
188 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
189 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
190 }
191
192 /* mov (d16,sp), dn */
193 void OP_FAB40000 (insn, extension)
194 unsigned long insn, extension;
195 {
196 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
197 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
198 }
199
200 /* mov (d32,sp), dn */
201 void OP_FCB40000 (insn, extension)
202 unsigned long insn, extension;
203 {
204 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
205 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
206 }
207
208 /* mov (di,am), dn */
209 void OP_F300 (insn, extension)
210 unsigned long insn, extension;
211 {
212 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
213 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
214 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
215 }
216
217 /* mov (abs16), dn */
218 void OP_300000 (insn, extension)
219 unsigned long insn, extension;
220 {
221 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
222 }
223
224 /* mov (abs32), dn */
225 void OP_FCA40000 (insn, extension)
226 unsigned long insn, extension;
227 {
228 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
229 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
230 }
231
232 /* mov (am), an */
233 void OP_F000 (insn, extension)
234 unsigned long insn, extension;
235 {
236 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
237 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
238 }
239
240 /* mov (d8,am), an */
241 void OP_F82000 (insn, extension)
242 unsigned long insn, extension;
243 {
244 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
245 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
246 + SEXT8 (insn & 0xff)), 4);
247 }
248
249 /* mov (d16,am), an */
250 void OP_FA200000 (insn, extension)
251 unsigned long insn, extension;
252 {
253 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
254 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
255 + SEXT16 (insn & 0xffff)), 4);
256 }
257
258 /* mov (d32,am), an */
259 void OP_FC200000 (insn, extension)
260 unsigned long insn, extension;
261 {
262 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
263 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
264 + ((insn & 0xffff) << 16) + extension), 4);
265 }
266
267 /* mov (d8,sp), an */
268 void OP_5C00 (insn, extension)
269 unsigned long insn, extension;
270 {
271 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
272 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
273 }
274
275 /* mov (d16,sp), an */
276 void OP_FAB00000 (insn, extension)
277 unsigned long insn, extension;
278 {
279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
281 }
282
283 /* mov (d32,sp), an */
284 void OP_FCB00000 (insn, extension)
285 unsigned long insn, extension;
286 {
287 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
288 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
289 }
290
291 /* mov (di,am), an */
292 void OP_F380 (insn, extension)
293 unsigned long insn, extension;
294 {
295 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
296 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
297 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
298 }
299
300 /* mov (abs16), an */
301 void OP_FAA00000 (insn, extension)
302 unsigned long insn, extension;
303 {
304 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
305 }
306
307 /* mov (abs32), an */
308 void OP_FCA00000 (insn, extension)
309 unsigned long insn, extension;
310 {
311 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
312 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
313 }
314
315 /* mov (d8,am), sp */
316 void OP_F8F000 (insn, extension)
317 unsigned long insn, extension;
318 {
319 State.regs[REG_SP]
320 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
321 + SEXT8 (insn & 0xff)), 4);
322 }
323
324 /* mov dm, (an) */
325 void OP_60 (insn, extension)
326 unsigned long insn, extension;
327 {
328 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
329 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
330 }
331
332 /* mov dm, (d8,an) */
333 void OP_F81000 (insn, extension)
334 unsigned long insn, extension;
335 {
336 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
337 + SEXT8 (insn & 0xff)), 4,
338 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
339 }
340
341 /* mov dm (d16,an) */
342 void OP_FA100000 (insn, extension)
343 unsigned long insn, extension;
344 {
345 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
346 + SEXT16 (insn & 0xffff)), 4,
347 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
348 }
349
350 /* mov dm (d32,an) */
351 void OP_FC100000 (insn, extension)
352 unsigned long insn, extension;
353 {
354 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
355 + ((insn & 0xffff) << 16) + extension), 4,
356 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
357 }
358
359 /* mov dm, (d8,sp) */
360 void OP_4200 (insn, extension)
361 unsigned long insn, extension;
362 {
363 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
364 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
365 }
366
367 /* mov dm, (d16,sp) */
368 void OP_FA910000 (insn, extension)
369 unsigned long insn, extension;
370 {
371 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
372 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
373 }
374
375 /* mov dm, (d32,sp) */
376 void OP_FC910000 (insn, extension)
377 unsigned long insn, extension;
378 {
379 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
380 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
381 }
382
383 /* mov dm, (di,an) */
384 void OP_F340 (insn, extension)
385 unsigned long insn, extension;
386 {
387 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
388 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
389 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
390 }
391
392 /* mov dm, (abs16) */
393 void OP_10000 (insn, extension)
394 unsigned long insn, extension;
395 {
396 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
397 }
398
399 /* mov dm, (abs32) */
400 void OP_FC810000 (insn, extension)
401 unsigned long insn, extension;
402 {
403 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
404 }
405
406 /* mov am, (an) */
407 void OP_F010 (insn, extension)
408 unsigned long insn, extension;
409 {
410 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
411 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
412 }
413
414 /* mov am, (d8,an) */
415 void OP_F83000 (insn, extension)
416 unsigned long insn, extension;
417 {
418 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
419 + SEXT8 (insn & 0xff)), 4,
420 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
421 }
422
423 /* mov am, (d16,an) */
424 void OP_FA300000 (insn, extension)
425 unsigned long insn, extension;
426 {
427 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
428 + SEXT16 (insn & 0xffff)), 4,
429 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
430 }
431
432 /* mov am, (d32,an) */
433 void OP_FC300000 (insn, extension)
434 unsigned long insn, extension;
435 {
436 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
437 + ((insn & 0xffff) << 16) + extension), 4,
438 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
439 }
440
441 /* mov am, (d8,sp) */
442 void OP_4300 (insn, extension)
443 unsigned long insn, extension;
444 {
445 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
446 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
447 }
448
449 /* mov am, (d16,sp) */
450 void OP_FA900000 (insn, extension)
451 unsigned long insn, extension;
452 {
453 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
454 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
455 }
456
457 /* mov am, (d32,sp) */
458 void OP_FC900000 (insn, extension)
459 unsigned long insn, extension;
460 {
461 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
462 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
463 }
464
465 /* mov am, (di,an) */
466 void OP_F3C0 (insn, extension)
467 unsigned long insn, extension;
468 {
469 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
470 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
471 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
472 }
473
474 /* mov am, (abs16) */
475 void OP_FA800000 (insn, extension)
476 unsigned long insn, extension;
477 {
478 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
479 }
480
481 /* mov am, (abs32) */
482 void OP_FC800000 (insn, extension)
483 unsigned long insn, extension;
484 {
485 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
486 }
487
488 /* mov sp, (d8,an) */
489 void OP_F8F400 (insn, extension)
490 unsigned long insn, extension;
491 {
492 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
493 4, State.regs[REG_SP]);
494 }
495
496 /* mov imm16, dn */
497 void OP_2C0000 (insn, extension)
498 unsigned long insn, extension;
499 {
500 unsigned long value;
501
502 value = SEXT16 (insn & 0xffff);
503 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
504 }
505
506 /* mov imm32,dn */
507 void OP_FCCC0000 (insn, extension)
508 unsigned long insn, extension;
509 {
510 unsigned long value;
511
512 value = (insn & 0xffff) << 16 | extension;
513 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
514 }
515
516 /* mov imm16, an */
517 void OP_240000 (insn, extension)
518 unsigned long insn, extension;
519 {
520 unsigned long value;
521
522 value = insn & 0xffff;
523 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
524 }
525
526 /* mov imm32, an */
527 void OP_FCDC0000 (insn, extension)
528 unsigned long insn, extension;
529 {
530 unsigned long value;
531
532 value = (insn & 0xffff) << 16 | extension;
533 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
534 }
535
536 /* movbu (am), dn */
537 void OP_F040 (insn, extension)
538 unsigned long insn, extension;
539 {
540 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
541 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
542 }
543
544 /* movbu (d8,am), dn */
545 void OP_F84000 (insn, extension)
546 unsigned long insn, extension;
547 {
548 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
549 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
550 + SEXT8 (insn & 0xff)), 1);
551 }
552
553 /* movbu (d16,am), dn */
554 void OP_FA400000 (insn, extension)
555 unsigned long insn, extension;
556 {
557 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
558 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
559 + SEXT16 (insn & 0xffff)), 1);
560 }
561
562 /* movbu (d32,am), dn */
563 void OP_FC400000 (insn, extension)
564 unsigned long insn, extension;
565 {
566 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
567 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
568 + ((insn & 0xffff) << 16) + extension), 1);
569 }
570
571 /* movbu (d8,sp), dn */
572 void OP_F8B800 (insn, extension)
573 unsigned long insn, extension;
574 {
575 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
576 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
577 }
578
579 /* movbu (d16,sp), dn */
580 void OP_FAB80000 (insn, extension)
581 unsigned long insn, extension;
582 {
583 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
584 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
585 }
586
587 /* movbu (d32,sp), dn */
588 void OP_FCB80000 (insn, extension)
589 unsigned long insn, extension;
590 {
591 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
592 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
593 }
594
595 /* movbu (di,am), dn */
596 void OP_F400 (insn, extension)
597 unsigned long insn, extension;
598 {
599 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
600 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
601 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
602 }
603
604 /* movbu (abs16), dn */
605 void OP_340000 (insn, extension)
606 unsigned long insn, extension;
607 {
608 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
609 }
610
611 /* movbu (abs32), dn */
612 void OP_FCA80000 (insn, extension)
613 unsigned long insn, extension;
614 {
615 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
616 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
617 }
618
619 /* movbu dm, (an) */
620 void OP_F050 (insn, extension)
621 unsigned long insn, extension;
622 {
623 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
624 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
625 }
626
627 /* movbu dm, (d8,an) */
628 void OP_F85000 (insn, extension)
629 unsigned long insn, extension;
630 {
631 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
632 + SEXT8 (insn & 0xff)), 1,
633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
634 }
635
636 /* movbu dm, (d16,an) */
637 void OP_FA500000 (insn, extension)
638 unsigned long insn, extension;
639 {
640 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
641 + SEXT16 (insn & 0xffff)), 1,
642 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
643 }
644
645 /* movbu dm, (d32,an) */
646 void OP_FC500000 (insn, extension)
647 unsigned long insn, extension;
648 {
649 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
650 + ((insn & 0xffff) << 16) + extension), 1,
651 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
652 }
653
654 /* movbu dm, (d8,sp) */
655 void OP_F89200 (insn, extension)
656 unsigned long insn, extension;
657 {
658 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
659 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
660 }
661
662 /* movbu dm, (d16,sp) */
663 void OP_FA920000 (insn, extension)
664 unsigned long insn, extension;
665 {
666 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
667 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
668 }
669
670 /* movbu dm (d32,sp) */
671 void OP_FC920000 (insn, extension)
672 unsigned long insn, extension;
673 {
674 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
675 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
676 }
677
678 /* movbu dm, (di,an) */
679 void OP_F440 (insn, extension)
680 unsigned long insn, extension;
681 {
682 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
683 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
684 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
685 }
686
687 /* movbu dm, (abs16) */
688 void OP_20000 (insn, extension)
689 unsigned long insn, extension;
690 {
691 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
692 }
693
694 /* movbu dm, (abs32) */
695 void OP_FC820000 (insn, extension)
696 unsigned long insn, extension;
697 {
698 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
699 }
700
701 /* movhu (am), dn */
702 void OP_F060 (insn, extension)
703 unsigned long insn, extension;
704 {
705 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
706 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
707 }
708
709 /* movhu (d8,am), dn */
710 void OP_F86000 (insn, extension)
711 unsigned long insn, extension;
712 {
713 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
714 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
715 + SEXT8 (insn & 0xff)), 2);
716 }
717
718 /* movhu (d16,am), dn */
719 void OP_FA600000 (insn, extension)
720 unsigned long insn, extension;
721 {
722 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
723 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
724 + SEXT16 (insn & 0xffff)), 2);
725 }
726
727 /* movhu (d32,am), dn */
728 void OP_FC600000 (insn, extension)
729 unsigned long insn, extension;
730 {
731 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
732 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
733 + ((insn & 0xffff) << 16) + extension), 2);
734 }
735
736 /* movhu (d8,sp) dn */
737 void OP_F8BC00 (insn, extension)
738 unsigned long insn, extension;
739 {
740 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
741 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
742 }
743
744 /* movhu (d16,sp), dn */
745 void OP_FABC0000 (insn, extension)
746 unsigned long insn, extension;
747 {
748 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
749 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
750 }
751
752 /* movhu (d32,sp), dn */
753 void OP_FCBC0000 (insn, extension)
754 unsigned long insn, extension;
755 {
756 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
757 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
758 }
759
760 /* movhu (di,am), dn */
761 void OP_F480 (insn, extension)
762 unsigned long insn, extension;
763 {
764 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
765 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
766 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
767 }
768
769 /* movhu (abs16), dn */
770 void OP_380000 (insn, extension)
771 unsigned long insn, extension;
772 {
773 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
774 }
775
776 /* movhu (abs32), dn */
777 void OP_FCAC0000 (insn, extension)
778 unsigned long insn, extension;
779 {
780 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
781 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
782 }
783
784 /* movhu dm, (an) */
785 void OP_F070 (insn, extension)
786 unsigned long insn, extension;
787 {
788 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
789 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
790 }
791
792 /* movhu dm, (d8,an) */
793 void OP_F87000 (insn, extension)
794 unsigned long insn, extension;
795 {
796 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
797 + SEXT8 (insn & 0xff)), 2,
798 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
799 }
800
801 /* movhu dm, (d16,an) */
802 void OP_FA700000 (insn, extension)
803 unsigned long insn, extension;
804 {
805 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
806 + SEXT16 (insn & 0xffff)), 2,
807 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
808 }
809
810 /* movhu dm, (d32,an) */
811 void OP_FC700000 (insn, extension)
812 unsigned long insn, extension;
813 {
814 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
815 + ((insn & 0xffff) << 16) + extension), 2,
816 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
817 }
818
819 /* movhu dm,(d8,sp) */
820 void OP_F89300 (insn, extension)
821 unsigned long insn, extension;
822 {
823 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
824 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
825 }
826
827 /* movhu dm,(d16,sp) */
828 void OP_FA930000 (insn, extension)
829 unsigned long insn, extension;
830 {
831 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
832 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
833 }
834
835 /* movhu dm,(d32,sp) */
836 void OP_FC930000 (insn, extension)
837 unsigned long insn, extension;
838 {
839 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
840 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
841 }
842
843 /* movhu dm, (di,an) */
844 void OP_F4C0 (insn, extension)
845 unsigned long insn, extension;
846 {
847 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
848 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
849 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
850 }
851
852 /* movhu dm, (abs16) */
853 void OP_30000 (insn, extension)
854 unsigned long insn, extension;
855 {
856 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
857 }
858
859 /* movhu dm, (abs32) */
860 void OP_FC830000 (insn, extension)
861 unsigned long insn, extension;
862 {
863 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
864 }
865
866 /* ext dn */
867 void OP_F2D0 (insn, extension)
868 unsigned long insn, extension;
869 {
870 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
871 State.regs[REG_MDR] = -1;
872 else
873 State.regs[REG_MDR] = 0;
874 }
875
876 /* extb dn */
877 void OP_10 (insn, extension)
878 unsigned long insn, extension;
879 {
880 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
881 }
882
883 /* extbu dn */
884 void OP_14 (insn, extension)
885 unsigned long insn, extension;
886 {
887 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
888 }
889
890 /* exth dn */
891 void OP_18 (insn, extension)
892 unsigned long insn, extension;
893 {
894 State.regs[REG_D0 + (insn & 0x3)]
895 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
896 }
897
898 /* exthu dn */
899 void OP_1C (insn, extension)
900 unsigned long insn, extension;
901 {
902 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
903 }
904
905 /* movm (sp), reg_list */
906 void OP_CE00 (insn, extension)
907 unsigned long insn, extension;
908 {
909 unsigned long sp = State.regs[REG_SP];
910 unsigned long mask;
911
912 mask = insn & 0xff;
913
914 if (mask & 0x8)
915 {
916 sp += 4;
917 State.regs[REG_LAR] = load_mem (sp, 4);
918 sp += 4;
919 State.regs[REG_LIR] = load_mem (sp, 4);
920 sp += 4;
921 State.regs[REG_MDR] = load_mem (sp, 4);
922 sp += 4;
923 State.regs[REG_A0 + 1] = load_mem (sp, 4);
924 sp += 4;
925 State.regs[REG_A0] = load_mem (sp, 4);
926 sp += 4;
927 State.regs[REG_D0 + 1] = load_mem (sp, 4);
928 sp += 4;
929 State.regs[REG_D0] = load_mem (sp, 4);
930 sp += 4;
931 }
932
933 if (mask & 0x10)
934 {
935 State.regs[REG_A0 + 3] = load_mem (sp, 4);
936 sp += 4;
937 }
938
939 if (mask & 0x20)
940 {
941 State.regs[REG_A0 + 2] = load_mem (sp, 4);
942 sp += 4;
943 }
944
945 if (mask & 0x40)
946 {
947 State.regs[REG_D0 + 3] = load_mem (sp, 4);
948 sp += 4;
949 }
950
951 if (mask & 0x80)
952 {
953 State.regs[REG_D0 + 2] = load_mem (sp, 4);
954 sp += 4;
955 }
956
957 /* And make sure to update the stack pointer. */
958 State.regs[REG_SP] = sp;
959 }
960
961 /* movm reg_list, (sp) */
962 void OP_CF00 (insn, extension)
963 unsigned long insn, extension;
964 {
965 unsigned long sp = State.regs[REG_SP];
966 unsigned long mask;
967
968 mask = insn & 0xff;
969
970 if (mask & 0x80)
971 {
972 sp -= 4;
973 store_mem (sp, 4, State.regs[REG_D0 + 2]);
974 }
975
976 if (mask & 0x40)
977 {
978 sp -= 4;
979 store_mem (sp, 4, State.regs[REG_D0 + 3]);
980 }
981
982 if (mask & 0x20)
983 {
984 sp -= 4;
985 store_mem (sp, 4, State.regs[REG_A0 + 2]);
986 }
987
988 if (mask & 0x10)
989 {
990 sp -= 4;
991 store_mem (sp, 4, State.regs[REG_A0 + 3]);
992 }
993
994 if (mask & 0x8)
995 {
996 sp -= 4;
997 store_mem (sp, 4, State.regs[REG_D0]);
998 sp -= 4;
999 store_mem (sp, 4, State.regs[REG_D0 + 1]);
1000 sp -= 4;
1001 store_mem (sp, 4, State.regs[REG_A0]);
1002 sp -= 4;
1003 store_mem (sp, 4, State.regs[REG_A0 + 1]);
1004 sp -= 4;
1005 store_mem (sp, 4, State.regs[REG_MDR]);
1006 sp -= 4;
1007 store_mem (sp, 4, State.regs[REG_LIR]);
1008 sp -= 4;
1009 store_mem (sp, 4, State.regs[REG_LAR]);
1010 sp -= 4;
1011 }
1012
1013 /* And make sure to update the stack pointer. */
1014 State.regs[REG_SP] = sp;
1015 }
1016
1017 /* clr dn */
1018 void OP_0 (insn, extension)
1019 unsigned long insn, extension;
1020 {
1021 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
1022
1023 PSW |= PSW_Z;
1024 PSW &= ~(PSW_V | PSW_C | PSW_N);
1025 }
1026
1027 /* add dm,dn */
1028 void OP_E0 (insn, extension)
1029 unsigned long insn, extension;
1030 {
1031 int z, c, n, v;
1032 unsigned long reg1, reg2, value;
1033
1034 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1035 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1036 value = reg1 + reg2;
1037 State.regs[REG_D0 + (insn & 0x3)] = value;
1038
1039 z = (value == 0);
1040 n = (value & 0x80000000);
1041 c = (reg1 < reg2);
1042 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1043 && (reg2 & 0x80000000) != (value & 0x80000000));
1044
1045 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1046 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1047 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1048 }
1049
1050 /* add dm, an */
1051 void OP_F160 (insn, extension)
1052 unsigned long insn, extension;
1053 {
1054 int z, c, n, v;
1055 unsigned long reg1, reg2, value;
1056
1057 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1058 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1059 value = reg1 + reg2;
1060 State.regs[REG_A0 + (insn & 0x3)] = value;
1061
1062 z = (value == 0);
1063 n = (value & 0x80000000);
1064 c = (reg1 < reg2);
1065 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1066 && (reg2 & 0x80000000) != (value & 0x80000000));
1067
1068 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1069 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1070 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1071 }
1072
1073 /* add am, dn */
1074 void OP_F150 (insn, extension)
1075 unsigned long insn, extension;
1076 {
1077 int z, c, n, v;
1078 unsigned long reg1, reg2, value;
1079
1080 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1081 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1082 value = reg1 + reg2;
1083 State.regs[REG_D0 + (insn & 0x3)] = value;
1084
1085 z = (value == 0);
1086 n = (value & 0x80000000);
1087 c = (reg1 < reg2);
1088 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1089 && (reg2 & 0x80000000) != (value & 0x80000000));
1090
1091 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1092 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1093 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1094 }
1095
1096 /* add am,an */
1097 void OP_F170 (insn, extension)
1098 unsigned long insn, extension;
1099 {
1100 int z, c, n, v;
1101 unsigned long reg1, reg2, value;
1102
1103 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1104 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1105 value = reg1 + reg2;
1106 State.regs[REG_A0 + (insn & 0x3)] = value;
1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < reg2);
1111 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1112 && (reg2 & 0x80000000) != (value & 0x80000000));
1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1117 }
1118
1119 /* add imm8, dn */
1120 void OP_2800 (insn, extension)
1121 unsigned long insn, extension;
1122 {
1123 int z, c, n, v;
1124 unsigned long reg1, imm, value;
1125
1126 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1127 imm = SEXT8 (insn & 0xff);
1128 value = reg1 + imm;
1129 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
1130
1131 z = (value == 0);
1132 n = (value & 0x80000000);
1133 c = (reg1 < imm);
1134 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1135 && (reg1 & 0x80000000) != (value & 0x80000000));
1136
1137 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1138 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1139 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1140 }
1141
1142 /* add imm16, dn */
1143 void OP_FAC00000 (insn, extension)
1144 unsigned long insn, extension;
1145 {
1146 int z, c, n, v;
1147 unsigned long reg1, imm, value;
1148
1149 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1150 imm = SEXT16 (insn & 0xffff);
1151 value = reg1 + imm;
1152 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1153
1154 z = (value == 0);
1155 n = (value & 0x80000000);
1156 c = (reg1 < imm);
1157 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1158 && (reg1 & 0x80000000) != (value & 0x80000000));
1159
1160 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1161 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1162 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1163 }
1164
1165 /* add imm32,dn */
1166 void OP_FCC00000 (insn, extension)
1167 unsigned long insn, extension;
1168 {
1169 int z, c, n, v;
1170 unsigned long reg1, imm, value;
1171
1172 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1173 imm = ((insn & 0xffff) << 16) | extension;
1174 value = reg1 + imm;
1175 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1176
1177 z = (value == 0);
1178 n = (value & 0x80000000);
1179 c = (reg1 < imm);
1180 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1181 && (reg1 & 0x80000000) != (value & 0x80000000));
1182
1183 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1184 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1185 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1186 }
1187
1188 /* add imm8, an */
1189 void OP_2000 (insn, extension)
1190 unsigned long insn, extension;
1191 {
1192 int z, c, n, v;
1193 unsigned long reg1, imm, value;
1194
1195 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1196 imm = SEXT8 (insn & 0xff);
1197 value = reg1 + imm;
1198 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
1199
1200 z = (value == 0);
1201 n = (value & 0x80000000);
1202 c = (reg1 < imm);
1203 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1204 && (reg1 & 0x80000000) != (value & 0x80000000));
1205
1206 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1207 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1208 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1209 }
1210
1211 /* add imm16, an */
1212 void OP_FAD00000 (insn, extension)
1213 unsigned long insn, extension;
1214 {
1215 int z, c, n, v;
1216 unsigned long reg1, imm, value;
1217
1218 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1219 imm = SEXT16 (insn & 0xffff);
1220 value = reg1 + imm;
1221 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1222
1223 z = (value == 0);
1224 n = (value & 0x80000000);
1225 c = (reg1 < imm);
1226 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1227 && (reg1 & 0x80000000) != (value & 0x80000000));
1228
1229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1230 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1231 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1232 }
1233
1234 /* add imm32, an */
1235 void OP_FCD00000 (insn, extension)
1236 unsigned long insn, extension;
1237 {
1238 int z, c, n, v;
1239 unsigned long reg1, imm, value;
1240
1241 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1242 imm = ((insn & 0xffff) << 16) | extension;
1243 value = reg1 + imm;
1244 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1245
1246 z = (value == 0);
1247 n = (value & 0x80000000);
1248 c = (reg1 < imm);
1249 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1250 && (reg1 & 0x80000000) != (value & 0x80000000));
1251
1252 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1253 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1254 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1255 }
1256
1257 /* add imm8, sp */
1258 void OP_F8FE00 (insn, extension)
1259 unsigned long insn, extension;
1260 {
1261 int z, c, n, v;
1262 unsigned long reg1, imm, value;
1263
1264 reg1 = State.regs[REG_SP];
1265 imm = SEXT8 (insn & 0xff);
1266 value = reg1 + imm;
1267 State.regs[REG_SP] = value;
1268 }
1269
1270 /* add imm16,sp */
1271 void OP_FAFE0000 (insn, extension)
1272 unsigned long insn, extension;
1273 {
1274 int z, c, n, v;
1275 unsigned long reg1, imm, value;
1276
1277 reg1 = State.regs[REG_SP];
1278 imm = SEXT16 (insn & 0xffff);
1279 value = reg1 + imm;
1280 State.regs[REG_SP] = value;
1281 }
1282
1283 /* add imm32, sp */
1284 void OP_FCFE0000 (insn, extension)
1285 unsigned long insn, extension;
1286 {
1287 int z, c, n, v;
1288 unsigned long reg1, imm, value;
1289
1290 reg1 = State.regs[REG_SP];
1291 imm = ((insn & 0xffff) << 16) | extension;
1292 value = reg1 + imm;
1293 State.regs[REG_SP] = value;
1294 }
1295
1296 /* addc dm,dn */
1297 void OP_F140 (insn, extension)
1298 unsigned long insn, extension;
1299 {
1300 int z, c, n, v;
1301 unsigned long reg1, reg2, value;
1302
1303 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1304 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1305 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1306 State.regs[REG_D0 + (insn & 0x3)] = value;
1307
1308 z = (value == 0);
1309 n = (value & 0x80000000);
1310 c = (reg1 < reg2);
1311 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1312 && (reg2 & 0x80000000) != (value & 0x80000000));
1313
1314 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1315 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1316 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1317 }
1318
1319 /* sub dm, dn */
1320 void OP_F100 (insn, extension)
1321 unsigned long insn, extension;
1322 {
1323 int z, c, n, v;
1324 unsigned long reg1, reg2, value;
1325
1326 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1327 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1328 value = reg2 - reg1;
1329
1330 z = (value == 0);
1331 n = (value & 0x80000000);
1332 c = (reg1 > reg2);
1333 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1334 && (reg2 & 0x80000000) != (value & 0x80000000));
1335
1336 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1337 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1338 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1339 State.regs[REG_D0 + (insn & 0x3)] = value;
1340 }
1341
1342 /* sub dm, an */
1343 void OP_F120 (insn, extension)
1344 unsigned long insn, extension;
1345 {
1346 int z, c, n, v;
1347 unsigned long reg1, reg2, value;
1348
1349 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1350 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1351 value = reg2 - reg1;
1352
1353 z = (value == 0);
1354 n = (value & 0x80000000);
1355 c = (reg1 > reg2);
1356 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1357 && (reg2 & 0x80000000) != (value & 0x80000000));
1358
1359 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1360 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1361 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1362 State.regs[REG_A0 + (insn & 0x3)] = value;
1363 }
1364
1365 /* sub am, dn */
1366 void OP_F110 (insn, extension)
1367 unsigned long insn, extension;
1368 {
1369 int z, c, n, v;
1370 unsigned long reg1, reg2, value;
1371
1372 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1373 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1374 value = reg2 - reg1;
1375
1376 z = (value == 0);
1377 n = (value & 0x80000000);
1378 c = (reg1 > reg2);
1379 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1380 && (reg2 & 0x80000000) != (value & 0x80000000));
1381
1382 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1383 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1384 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1385 State.regs[REG_D0 + (insn & 0x3)] = value;
1386 }
1387
1388 /* sub am, an */
1389 void OP_F130 (insn, extension)
1390 unsigned long insn, extension;
1391 {
1392 int z, c, n, v;
1393 unsigned long reg1, reg2, value;
1394
1395 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1396 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1397 value = reg2 - reg1;
1398
1399 z = (value == 0);
1400 n = (value & 0x80000000);
1401 c = (reg1 > reg2);
1402 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1403 && (reg2 & 0x80000000) != (value & 0x80000000));
1404
1405 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1406 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1407 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1408 State.regs[REG_A0 + (insn & 0x3)] = value;
1409 }
1410
1411 /* sub imm32, dn */
1412 void OP_FCC40000 (insn, extension)
1413 unsigned long insn, extension;
1414 {
1415 int z, c, n, v;
1416 unsigned long reg1, imm, value;
1417
1418 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1419 imm = ((insn & 0xffff) << 16) | extension;
1420 value = reg1 - imm;
1421
1422 z = (value == 0);
1423 n = (value & 0x80000000);
1424 c = (reg1 < imm);
1425 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1426 && (reg1 & 0x80000000) != (value & 0x80000000));
1427
1428 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1429 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1430 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1431 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1432 }
1433
1434 /* sub imm32, an */
1435 void OP_FCD40000 (insn, extension)
1436 unsigned long insn, extension;
1437 {
1438 int z, c, n, v;
1439 unsigned long reg1, imm, value;
1440
1441 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1442 imm = ((insn & 0xffff) << 16) | extension;
1443 value = reg1 - imm;
1444
1445 z = (value == 0);
1446 n = (value & 0x80000000);
1447 c = (reg1 < imm);
1448 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1449 && (reg1 & 0x80000000) != (value & 0x80000000));
1450
1451 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1452 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1453 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1454 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1455 }
1456
1457 /* subc dm, dn */
1458 void OP_F180 (insn, extension)
1459 unsigned long insn, extension;
1460 {
1461 int z, c, n, v;
1462 unsigned long reg1, reg2, value;
1463
1464 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1465 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1466 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1467
1468 z = (value == 0);
1469 n = (value & 0x80000000);
1470 c = (reg1 > reg2);
1471 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1472 && (reg2 & 0x80000000) != (value & 0x80000000));
1473
1474 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1475 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1476 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1477 State.regs[REG_D0 + (insn & 0x3)] = value;
1478 }
1479
1480 /* mul dm, dn */
1481 void OP_F240 (insn, extension)
1482 unsigned long insn, extension;
1483 {
1484 unsigned long long temp;
1485 int n, z;
1486
1487 temp = (State.regs[REG_D0 + (insn & 0x3)]
1488 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1489 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1490 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1491 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1492 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1493 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1494 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1495 }
1496
1497 /* mulu dm, dn */
1498 void OP_F250 (insn, extension)
1499 unsigned long insn, extension;
1500 {
1501 unsigned long long temp;
1502 int n, z;
1503
1504 temp = (State.regs[REG_D0 + (insn & 0x3)]
1505 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1506 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1507 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1508 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1509 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1510 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1511 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1512 }
1513
1514 /* div dm, dn */
1515 void OP_F260 (insn, extension)
1516 unsigned long insn, extension;
1517 {
1518 long long temp;
1519 int n, z;
1520
1521 temp = State.regs[REG_MDR];
1522 temp <<= 32;
1523 temp |= State.regs[REG_D0 + (insn & 0x3)];
1524 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1525 temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1526 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1527 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1528 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1529 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1530 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1531 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1532 }
1533
1534 /* divu dm, dn */
1535 void OP_F270 (insn, extension)
1536 unsigned long insn, extension;
1537 {
1538 unsigned long long temp;
1539 int n, z;
1540
1541 temp = State.regs[REG_MDR];
1542 temp <<= 32;
1543 temp |= State.regs[REG_D0 + (insn & 0x3)];
1544 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1545 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1546 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1547 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1548 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1549 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1550 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1551 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1552 }
1553
1554 /* inc dn */
1555 void OP_40 (insn, extension)
1556 unsigned long insn, extension;
1557 {
1558 int z,n,c,v;
1559 unsigned int value, imm, reg1;
1560
1561 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1562 imm = 1;
1563 value = reg1 + imm;
1564 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
1565
1566 z = (value == 0);
1567 n = (value & 0x80000000);
1568 c = (reg1 < imm);
1569 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1570 && (reg1 & 0x80000000) != (value & 0x80000000));
1571
1572 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1573 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1574 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1575 }
1576
1577 /* inc an */
1578 void OP_41 (insn, extension)
1579 unsigned long insn, extension;
1580 {
1581 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1582 }
1583
1584 /* inc4 an */
1585 void OP_50 (insn, extension)
1586 unsigned long insn, extension;
1587 {
1588 State.regs[REG_A0 + (insn & 0x3)] += 4;
1589 }
1590
1591 /* cmp imm8, dn */
1592 void OP_A000 (insn, extension)
1593 unsigned long insn, extension;
1594 {
1595 int z, c, n, v;
1596 unsigned long reg1, imm, value;
1597
1598 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1599 imm = SEXT8 (insn & 0xff);
1600 value = reg1 - imm;
1601
1602 z = (value == 0);
1603 n = (value & 0x80000000);
1604 c = (reg1 < imm);
1605 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1606 && (reg1 & 0x80000000) != (value & 0x80000000));
1607
1608 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1609 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1610 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1611 }
1612
1613 /* cmp dm, dn */
1614 void OP_A0 (insn, extension)
1615 unsigned long insn, extension;
1616 {
1617 int z, c, n, v;
1618 unsigned long reg1, reg2, value;
1619
1620 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1621 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1622 value = reg2 - reg1;
1623
1624 z = (value == 0);
1625 n = (value & 0x80000000);
1626 c = (reg1 > reg2);
1627 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1628 && (reg2 & 0x80000000) != (value & 0x80000000));
1629
1630 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1631 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1632 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1633 }
1634
1635 /* cmp dm, an */
1636 void OP_F1A0 (insn, extension)
1637 unsigned long insn, extension;
1638 {
1639 int z, c, n, v;
1640 unsigned long reg1, reg2, value;
1641
1642 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1643 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1644 value = reg2 - reg1;
1645
1646 z = (value == 0);
1647 n = (value & 0x80000000);
1648 c = (reg1 > reg2);
1649 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1650 && (reg2 & 0x80000000) != (value & 0x80000000));
1651
1652 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1653 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1654 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1655 }
1656
1657 /* cmp am, dn */
1658 void OP_F190 (insn, extension)
1659 unsigned long insn, extension;
1660 {
1661 int z, c, n, v;
1662 unsigned long reg1, reg2, value;
1663
1664 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1665 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1666 value = reg2 - reg1;
1667
1668 z = (value == 0);
1669 n = (value & 0x80000000);
1670 c = (reg1 > reg2);
1671 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1672 && (reg2 & 0x80000000) != (value & 0x80000000));
1673
1674 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1675 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1676 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1677 }
1678
1679 /* cmp imm8, an */
1680 void OP_B000 (insn, extension)
1681 unsigned long insn, extension;
1682 {
1683 int z, c, n, v;
1684 unsigned long reg1, imm, value;
1685
1686 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1687 imm = insn & 0xff;
1688 value = reg1 - imm;
1689
1690 z = (value == 0);
1691 n = (value & 0x80000000);
1692 c = (reg1 < imm);
1693 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1694 && (reg1 & 0x80000000) != (value & 0x80000000));
1695
1696 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1697 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1698 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1699 }
1700
1701 /* cmp am, an */
1702 void OP_B0 (insn, extension)
1703 unsigned long insn, extension;
1704 {
1705 int z, c, n, v;
1706 unsigned long reg1, reg2, value;
1707
1708 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1709 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1710 value = reg2 - reg1;
1711
1712 z = (value == 0);
1713 n = (value & 0x80000000);
1714 c = (reg1 > reg2);
1715 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1716 && (reg2 & 0x80000000) != (value & 0x80000000));
1717
1718 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1719 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1720 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1721 }
1722
1723 /* cmp imm16, dn */
1724 void OP_FAC80000 (insn, extension)
1725 unsigned long insn, extension;
1726 {
1727 int z, c, n, v;
1728 unsigned long reg1, imm, value;
1729
1730 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1731 imm = SEXT16 (insn & 0xffff);
1732 value = reg1 - imm;
1733
1734 z = (value == 0);
1735 n = (value & 0x80000000);
1736 c = (reg1 < imm);
1737 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1738 && (reg1 & 0x80000000) != (value & 0x80000000));
1739
1740 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1741 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1742 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1743 }
1744
1745 /* cmp imm32, dn */
1746 void OP_FCC80000 (insn, extension)
1747 unsigned long insn, extension;
1748 {
1749 int z, c, n, v;
1750 unsigned long reg1, imm, value;
1751
1752 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1753 imm = ((insn & 0xffff) << 16) | extension;
1754 value = reg1 - imm;
1755
1756 z = (value == 0);
1757 n = (value & 0x80000000);
1758 c = (reg1 < imm);
1759 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1760 && (reg1 & 0x80000000) != (value & 0x80000000));
1761
1762 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1763 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1764 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1765 }
1766
1767 /* cmp imm16, an */
1768 void OP_FAD80000 (insn, extension)
1769 unsigned long insn, extension;
1770 {
1771 int z, c, n, v;
1772 unsigned long reg1, imm, value;
1773
1774 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1775 imm = insn & 0xffff;
1776 value = reg1 - imm;
1777
1778 z = (value == 0);
1779 n = (value & 0x80000000);
1780 c = (reg1 < imm);
1781 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1782 && (reg1 & 0x80000000) != (value & 0x80000000));
1783
1784 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1785 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1786 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1787 }
1788
1789 /* cmp imm32, an */
1790 void OP_FCD80000 (insn, extension)
1791 unsigned long insn, extension;
1792 {
1793 int z, c, n, v;
1794 unsigned long reg1, imm, value;
1795
1796 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1797 imm = ((insn & 0xffff) << 16) | extension;
1798 value = reg1 - imm;
1799
1800 z = (value == 0);
1801 n = (value & 0x80000000);
1802 c = (reg1 < imm);
1803 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1804 && (reg1 & 0x80000000) != (value & 0x80000000));
1805
1806 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1807 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1808 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1809 }
1810
1811 /* and dm, dn */
1812 void OP_F200 (insn, extension)
1813 unsigned long insn, extension;
1814 {
1815 int n, z;
1816
1817 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1818 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1819 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1822 }
1823
1824 /* and imm8, dn */
1825 void OP_F8E000 (insn, extension)
1826 unsigned long insn, extension;
1827 {
1828 int n, z;
1829
1830 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1831 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1832 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1833 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1834 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1835 }
1836
1837 /* and imm16, dn */
1838 void OP_FAE00000 (insn, extension)
1839 unsigned long insn, extension;
1840 {
1841 int n, z;
1842
1843 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1844 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1845 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1846 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1847 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1848 }
1849
1850 /* and imm32, dn */
1851 void OP_FCE00000 (insn, extension)
1852 unsigned long insn, extension;
1853 {
1854 int n, z;
1855
1856 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1857 &= ((insn & 0xffff) << 16 | extension);
1858 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1859 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1862 }
1863
1864 /* and imm16, psw */
1865 void OP_FAFC0000 (insn, extension)
1866 unsigned long insn, extension;
1867 {
1868 PSW &= (insn & 0xffff);
1869 }
1870
1871 /* or dm, dn*/
1872 void OP_F210 (insn, extension)
1873 unsigned long insn, extension;
1874 {
1875 int n, z;
1876
1877 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1878 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1879 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1880 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1881 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1882 }
1883
1884 /* or imm8, dn */
1885 void OP_F8E400 (insn, extension)
1886 unsigned long insn, extension;
1887 {
1888 int n, z;
1889
1890 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1891 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1892 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1893 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1894 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1895 }
1896
1897 /* or imm16, dn*/
1898 void OP_FAE40000 (insn, extension)
1899 unsigned long insn, extension;
1900 {
1901 int n, z;
1902
1903 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1904 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1905 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1906 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1907 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1908 }
1909
1910 /* or imm32, dn */
1911 void OP_FCE40000 (insn, extension)
1912 unsigned long insn, extension;
1913 {
1914 int n, z;
1915
1916 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1917 |= ((insn & 0xffff) << 16 | extension);
1918 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1919 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1922 }
1923
1924 /* or imm16,psw */
1925 void OP_FAFD0000 (insn, extension)
1926 unsigned long insn, extension;
1927 {
1928 PSW |= (insn & 0xffff);
1929 }
1930
1931 /* xor dm, dn*/
1932 void OP_F220 (insn, extension)
1933 unsigned long insn, extension;
1934 {
1935 int n, z;
1936
1937 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1938 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1939 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1940 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1941 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1942 }
1943
1944 /* xor imm16, dn */
1945 void OP_FAE80000 (insn, extension)
1946 unsigned long insn, extension;
1947 {
1948 int n, z;
1949
1950 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1951 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1952 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1953 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1954 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1955 }
1956
1957 /* xor imm32, dn */
1958 void OP_FCE80000 (insn, extension)
1959 unsigned long insn, extension;
1960 {
1961 int n, z;
1962
1963 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1964 ^= ((insn & 0xffff) << 16 | extension);
1965 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1966 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1967 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1968 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1969 }
1970
1971 /* not dn */
1972 void OP_F230 (insn, extension)
1973 unsigned long insn, extension;
1974 {
1975 int n, z;
1976
1977 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1978 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1979 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1980 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1981 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1982 }
1983
1984 /* btst imm8, dn */
1985 void OP_F8EC00 (insn, extension)
1986 unsigned long insn, extension;
1987 {
1988 unsigned long temp;
1989 int z, n;
1990
1991 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1992 temp &= (insn & 0xff);
1993 n = (temp & 0x80000000) != 0;
1994 z = (temp == 0);
1995 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1996 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1997 }
1998
1999 /* btst imm16, dn */
2000 void OP_FAEC0000 (insn, extension)
2001 unsigned long insn, extension;
2002 {
2003 unsigned long temp;
2004 int z, n;
2005
2006 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
2007 temp &= (insn & 0xffff);
2008 n = (temp & 0x80000000) != 0;
2009 z = (temp == 0);
2010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2011 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2012 }
2013
2014 /* btst imm32, dn */
2015 void OP_FCEC0000 (insn, extension)
2016 unsigned long insn, extension;
2017 {
2018 unsigned long temp;
2019 int z, n;
2020
2021 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
2022 temp &= ((insn & 0xffff) << 16 | extension);
2023 n = (temp & 0x80000000) != 0;
2024 z = (temp == 0);
2025 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2026 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2027 }
2028
2029 /* btst imm8,(abs32) */
2030 void OP_FE020000 (insn, extension)
2031 unsigned long insn, extension;
2032 {
2033 unsigned long temp;
2034 int n, z;
2035
2036 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2037 temp &= (extension & 0xff);
2038 n = (temp & 0x80000000) != 0;
2039 z = (temp == 0);
2040 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2041 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2042 }
2043
2044 /* btst imm8,(d8,an) */
2045 void OP_FAF80000 (insn, extension)
2046 unsigned long insn, extension;
2047 {
2048 unsigned long temp;
2049 int n, z;
2050
2051 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2052 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2053 temp &= (insn & 0xff);
2054 n = (temp & 0x80000000) != 0;
2055 z = (temp == 0);
2056 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2057 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2058 }
2059
2060 /* bset dm, (an) */
2061 void OP_F080 (insn, extension)
2062 unsigned long insn, extension;
2063 {
2064 unsigned long temp;
2065 int z;
2066
2067 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2068 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
2069 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2070 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2071 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2072 PSW |= (z ? PSW_Z : 0);
2073 }
2074
2075 /* bset imm8, (abs32) */
2076 void OP_FE000000 (insn, extension)
2077 unsigned long insn, extension;
2078 {
2079 unsigned long temp;
2080 int z;
2081
2082 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
2083 z = (temp & (extension & 0xff)) == 0;
2084 temp |= (extension & 0xff);
2085 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
2086 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2087 PSW |= (z ? PSW_Z : 0);
2088 }
2089
2090 /* bset imm8,(d8,an) */
2091 void OP_FAF00000 (insn, extension)
2092 unsigned long insn, extension;
2093 {
2094 unsigned long temp;
2095 int z;
2096
2097 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2098 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2099 z = (temp & (insn & 0xff)) == 0;
2100 temp |= (insn & 0xff);
2101 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2102 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2103 PSW |= (z ? PSW_Z : 0);
2104 }
2105
2106 /* bclr dm, (an) */
2107 void OP_F090 (insn, extension)
2108 unsigned long insn, extension;
2109 {
2110 unsigned long temp;
2111 int z;
2112
2113 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2114 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
2115 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2116 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2117 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2118 PSW |= (z ? PSW_Z : 0);
2119 }
2120
2121 /* bclr imm8, (abs32) */
2122 void OP_FE010000 (insn, extension)
2123 unsigned long insn, extension;
2124 {
2125 unsigned long temp;
2126 int z;
2127
2128 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2129 z = (temp & (extension & 0xff)) == 0;
2130 temp = ~temp & (extension & 0xff);
2131 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
2132 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2133 PSW |= (z ? PSW_Z : 0);
2134 }
2135
2136 /* bclr imm8,(d8,an) */
2137 void OP_FAF40000 (insn, extension)
2138 unsigned long insn, extension;
2139 {
2140 unsigned long temp;
2141 int z;
2142
2143 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2144 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2145 z = (temp & (insn & 0xff)) == 0;
2146 temp = ~temp & (insn & 0xff);
2147 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2148 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2149 PSW |= (z ? PSW_Z : 0);
2150 }
2151
2152 /* asr dm, dn */
2153 void OP_F2B0 (insn, extension)
2154 unsigned long insn, extension;
2155 {
2156 long temp;
2157 int z, n, c;
2158
2159 temp = State.regs[REG_D0 + (insn & 0x3)];
2160 c = temp & 1;
2161 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2162 State.regs[REG_D0 + (insn & 0x3)] = temp;
2163 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2164 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2165 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2166 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2167 }
2168
2169 /* asr imm8, dn */
2170 void OP_F8C800 (insn, extension)
2171 unsigned long insn, extension;
2172 {
2173 long temp;
2174 int z, n, c;
2175
2176 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2177 c = temp & 1;
2178 temp >>= (insn & 0xff);
2179 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2180 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2181 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2182 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2183 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2184 }
2185
2186 /* lsr dm, dn */
2187 void OP_F2A0 (insn, extension)
2188 unsigned long insn, extension;
2189 {
2190 int z, n, c;
2191
2192 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2193 State.regs[REG_D0 + (insn & 0x3)]
2194 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2195 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2196 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2197 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2198 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2199 }
2200
2201 /* lsr dm, dn */
2202 void OP_F8C400 (insn, extension)
2203 unsigned long insn, extension;
2204 {
2205 int z, n, c;
2206
2207 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2208 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2209 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
2210 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
2211 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2212 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2213 }
2214
2215 /* asl dm, dn */
2216 void OP_F290 (insn, extension)
2217 unsigned long insn, extension;
2218 {
2219 int n, z;
2220
2221 State.regs[REG_D0 + (insn & 0x3)]
2222 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2223 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2224 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2225 PSW &= ~(PSW_Z | PSW_N);
2226 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2227 }
2228
2229 /* asl imm8, dn */
2230 void OP_F8C000 (insn, extension)
2231 unsigned long insn, extension;
2232 {
2233 int n, z;
2234
2235 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2236 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2237 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2238 PSW &= ~(PSW_Z | PSW_N);
2239 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2240 }
2241
2242 /* asl2 dn */
2243 void OP_54 (insn, extension)
2244 unsigned long insn, extension;
2245 {
2246 int n, z;
2247
2248 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2249 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2250 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2251 PSW &= ~(PSW_Z | PSW_N);
2252 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2253 }
2254
2255 /* ror dn */
2256 void OP_F284 (insn, extension)
2257 unsigned long insn, extension;
2258 {
2259 unsigned long value;
2260 int c,n,z;
2261
2262 value = State.regs[REG_D0 + (insn & 0x3)];
2263 if (value & 0x1)
2264 c = 1;
2265
2266 value >>= 1;
2267 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2268 State.regs[REG_D0 + (insn & 0x3)] = value;
2269 z = (value == 0);
2270 n = (value & 0x80000000) != 0;
2271 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2272 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2273 }
2274
2275 /* rol dn */
2276 void OP_F280 (insn, extension)
2277 unsigned long insn, extension;
2278 {
2279 unsigned long value;
2280 int c,n,z;
2281
2282 value = State.regs[REG_D0 + (insn & 0x3)];
2283 if (value & 0x80000000)
2284 c = 1;
2285
2286 value <<= 1;
2287 value |= ((PSW & PSW_C) != 0);
2288 State.regs[REG_D0 + (insn & 0x3)] = value;
2289 z = (value == 0);
2290 n = (value & 0x80000000) != 0;
2291 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2292 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2293 }
2294
2295 /* beq label:8 */
2296 void OP_C800 (insn, extension)
2297 unsigned long insn, extension;
2298 {
2299 /* The dispatching code will add 2 after we return, so
2300 we subtract two here to make things right. */
2301 if (PSW & PSW_Z)
2302 State.pc += SEXT8 (insn & 0xff) - 2;
2303 }
2304
2305 /* bne label:8 */
2306 void OP_C900 (insn, extension)
2307 unsigned long insn, extension;
2308 {
2309 /* The dispatching code will add 2 after we return, so
2310 we subtract two here to make things right. */
2311 if (!(PSW & PSW_Z))
2312 State.pc += SEXT8 (insn & 0xff) - 2;
2313 }
2314
2315 /* bgt label:8 */
2316 void OP_C100 (insn, extension)
2317 unsigned long insn, extension;
2318 {
2319 /* The dispatching code will add 2 after we return, so
2320 we subtract two here to make things right. */
2321 if (!((PSW & PSW_Z)
2322 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2323 State.pc += SEXT8 (insn & 0xff) - 2;
2324 }
2325
2326 /* bge label:8 */
2327 void OP_C200 (insn, extension)
2328 unsigned long insn, extension;
2329 {
2330 /* The dispatching code will add 2 after we return, so
2331 we subtract two here to make things right. */
2332 if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2333 State.pc += SEXT8 (insn & 0xff) - 2;
2334 }
2335
2336 /* ble label:8 */
2337 void OP_C300 (insn, extension)
2338 unsigned long insn, extension;
2339 {
2340 /* The dispatching code will add 2 after we return, so
2341 we subtract two here to make things right. */
2342 if ((PSW & PSW_Z)
2343 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2344 State.pc += SEXT8 (insn & 0xff) - 2;
2345 }
2346
2347 /* blt label:8 */
2348 void OP_C000 (insn, extension)
2349 unsigned long insn, extension;
2350 {
2351 /* The dispatching code will add 2 after we return, so
2352 we subtract two here to make things right. */
2353 if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2354 State.pc += SEXT8 (insn & 0xff) - 2;
2355 }
2356
2357 /* bhi label:8 */
2358 void OP_C500 (insn, extension)
2359 unsigned long insn, extension;
2360 {
2361 /* The dispatching code will add 2 after we return, so
2362 we subtract two here to make things right. */
2363 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2364 State.pc += SEXT8 (insn & 0xff) - 2;
2365 }
2366
2367 /* bcc label:8 */
2368 void OP_C600 (insn, extension)
2369 unsigned long insn, extension;
2370 {
2371 /* The dispatching code will add 2 after we return, so
2372 we subtract two here to make things right. */
2373 if (!(PSW & PSW_C))
2374 State.pc += SEXT8 (insn & 0xff) - 2;
2375 }
2376
2377 /* bls label:8 */
2378 void OP_C700 (insn, extension)
2379 unsigned long insn, extension;
2380 {
2381 /* The dispatching code will add 2 after we return, so
2382 we subtract two here to make things right. */
2383 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2384 State.pc += SEXT8 (insn & 0xff) - 2;
2385 }
2386
2387 /* bcs label:8 */
2388 void OP_C400 (insn, extension)
2389 unsigned long insn, extension;
2390 {
2391 /* The dispatching code will add 2 after we return, so
2392 we subtract two here to make things right. */
2393 if (PSW & PSW_C)
2394 State.pc += SEXT8 (insn & 0xff) - 2;
2395 }
2396
2397 /* bvc label:8 */
2398 void OP_F8E800 (insn, extension)
2399 unsigned long insn, extension;
2400 {
2401 /* The dispatching code will add 3 after we return, so
2402 we subtract two here to make things right. */
2403 if (!(PSW & PSW_V))
2404 State.pc += SEXT8 (insn & 0xff) - 3;
2405 }
2406
2407 /* bvs label:8 */
2408 void OP_F8E900 (insn, extension)
2409 unsigned long insn, extension;
2410 {
2411 /* The dispatching code will add 3 after we return, so
2412 we subtract two here to make things right. */
2413 if (PSW & PSW_V)
2414 State.pc += SEXT8 (insn & 0xff) - 3;
2415 }
2416
2417 /* bnc label:8 */
2418 void OP_F8EA00 (insn, extension)
2419 unsigned long insn, extension;
2420 {
2421 /* The dispatching code will add 3 after we return, so
2422 we subtract two here to make things right. */
2423 if (!(PSW & PSW_N))
2424 State.pc += SEXT8 (insn & 0xff) - 3;
2425 }
2426
2427 /* bns label:8 */
2428 void OP_F8EB00 (insn, extension)
2429 unsigned long insn, extension;
2430 {
2431 /* The dispatching code will add 3 after we return, so
2432 we subtract two here to make things right. */
2433 if (PSW & PSW_N)
2434 State.pc += SEXT8 (insn & 0xff) - 3;
2435 }
2436
2437 /* bra label:8 */
2438 void OP_CA00 (insn, extension)
2439 unsigned long insn, extension;
2440 {
2441 /* The dispatching code will add 2 after we return, so
2442 we subtract two here to make things right. */
2443 State.pc += SEXT8 (insn & 0xff) - 2;
2444 }
2445
2446 /* leq */
2447 void OP_D8 (insn, extension)
2448 unsigned long insn, extension;
2449 {
2450 abort ();
2451 }
2452
2453 /* lne */
2454 void OP_D9 (insn, extension)
2455 unsigned long insn, extension;
2456 {
2457 abort ();
2458 }
2459
2460 /* lgt */
2461 void OP_D1 (insn, extension)
2462 unsigned long insn, extension;
2463 {
2464 abort ();
2465 }
2466
2467 /* lge */
2468 void OP_D2 (insn, extension)
2469 unsigned long insn, extension;
2470 {
2471 abort ();
2472 }
2473
2474 /* lle */
2475 void OP_D3 (insn, extension)
2476 unsigned long insn, extension;
2477 {
2478 abort ();
2479 }
2480
2481 /* llt */
2482 void OP_D0 (insn, extension)
2483 unsigned long insn, extension;
2484 {
2485 abort ();
2486 }
2487
2488 /* lhi */
2489 void OP_D5 (insn, extension)
2490 unsigned long insn, extension;
2491 {
2492 abort ();
2493 }
2494
2495 /* lcc */
2496 void OP_D6 (insn, extension)
2497 unsigned long insn, extension;
2498 {
2499 abort ();
2500 }
2501
2502 /* lls */
2503 void OP_D7 (insn, extension)
2504 unsigned long insn, extension;
2505 {
2506 abort ();
2507 }
2508
2509 /* lcs */
2510 void OP_D4 (insn, extension)
2511 unsigned long insn, extension;
2512 {
2513 abort ();
2514 }
2515
2516 /* lra */
2517 void OP_DA (insn, extension)
2518 unsigned long insn, extension;
2519 {
2520 abort ();
2521 }
2522
2523 /* setlb */
2524 void OP_DB (insn, extension)
2525 unsigned long insn, extension;
2526 {
2527 abort ();
2528 }
2529
2530 /* jmp (an) */
2531 void OP_F0F4 (insn, extension)
2532 unsigned long insn, extension;
2533 {
2534 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2535 }
2536
2537 /* jmp label:16 */
2538 void OP_CC0000 (insn, extension)
2539 unsigned long insn, extension;
2540 {
2541 State.pc += SEXT16 (insn & 0xffff) - 3;
2542 }
2543
2544 /* jmp label:32 */
2545 void OP_DC000000 (insn, extension)
2546 unsigned long insn, extension;
2547 {
2548 State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2549 }
2550
2551 /* call label:16,reg_list,imm8 */
2552 void OP_CD000000 (insn, extension)
2553 unsigned long insn, extension;
2554 {
2555 unsigned int next_pc, sp, adjust;
2556 unsigned long mask;
2557
2558 sp = State.regs[REG_SP];
2559 next_pc = State.pc + 2;
2560 State.mem[sp] = next_pc & 0xff;
2561 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2562 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2563 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2564
2565 mask = insn & 0xff;
2566
2567 adjust = 0;
2568 if (mask & 0x80)
2569 {
2570 adjust -= 4;
2571 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2572 }
2573
2574 if (mask & 0x40)
2575 {
2576 adjust -= 4;
2577 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2578 }
2579
2580 if (mask & 0x20)
2581 {
2582 adjust -= 4;
2583 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2584 }
2585
2586 if (mask & 0x10)
2587 {
2588 adjust -= 4;
2589 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2590 }
2591
2592 if (mask & 0x8)
2593 {
2594 adjust -= 4;
2595 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2596 adjust -= 4;
2597 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2598 adjust -= 4;
2599 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2600 adjust -= 4;
2601 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2602 adjust -= 4;
2603 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2604 adjust -= 4;
2605 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2606 adjust -= 4;
2607 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2608 adjust -= 4;
2609 }
2610
2611 /* And make sure to update the stack pointer. */
2612 State.regs[REG_SP] -= extension;
2613 State.regs[REG_MDR] = next_pc;
2614 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2615 }
2616
2617 /* call label:32,reg_list,imm8*/
2618 void OP_DD000000 (insn, extension)
2619 unsigned long insn, extension;
2620 {
2621 unsigned int next_pc, sp, adjust;
2622 unsigned long mask;
2623
2624 sp = State.regs[REG_SP];
2625 next_pc = State.pc + 2;
2626 State.mem[sp] = next_pc & 0xff;
2627 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2628 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2629 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2630
2631 mask = (extension & 0xff00) >> 8;
2632
2633 adjust = 0;
2634 if (mask & 0x80)
2635 {
2636 adjust -= 4;
2637 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2638 }
2639
2640 if (mask & 0x40)
2641 {
2642 adjust -= 4;
2643 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2644 }
2645
2646 if (mask & 0x20)
2647 {
2648 adjust -= 4;
2649 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2650 }
2651
2652 if (mask & 0x10)
2653 {
2654 adjust -= 4;
2655 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2656 }
2657
2658 if (mask & 0x8)
2659 {
2660 adjust -= 4;
2661 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2662 adjust -= 4;
2663 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2664 adjust -= 4;
2665 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2666 adjust -= 4;
2667 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2668 adjust -= 4;
2669 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2670 adjust -= 4;
2671 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2672 adjust -= 4;
2673 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2674 adjust -= 4;
2675 }
2676
2677 /* And make sure to update the stack pointer. */
2678 State.regs[REG_SP] -= (extension & 0xff);
2679 State.regs[REG_MDR] = next_pc;
2680 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2681 }
2682
2683 /* calls (an) */
2684 void OP_F0F0 (insn, extension)
2685 unsigned long insn, extension;
2686 {
2687 unsigned int next_pc, sp;
2688
2689 sp = State.regs[REG_SP];
2690 next_pc = State.pc + 2;
2691 State.mem[sp] = next_pc & 0xff;
2692 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2693 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2694 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2695 State.regs[REG_MDR] = next_pc;
2696 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2697 }
2698
2699 /* calls label:16 */
2700 void OP_FAFF0000 (insn, extension)
2701 unsigned long insn, extension;
2702 {
2703 unsigned int next_pc, sp;
2704
2705 sp = State.regs[REG_SP];
2706 next_pc = State.pc + 4;
2707 State.mem[sp] = next_pc & 0xff;
2708 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2709 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2710 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2711 State.regs[REG_MDR] = next_pc;
2712 State.pc += SEXT16 (insn & 0xffff) - 4;
2713 }
2714
2715 /* calls label:32 */
2716 void OP_FCFF0000 (insn, extension)
2717 unsigned long insn, extension;
2718 {
2719 unsigned int next_pc, sp;
2720
2721 sp = State.regs[REG_SP];
2722 next_pc = State.pc + 6;
2723 State.mem[sp] = next_pc & 0xff;
2724 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2725 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2726 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2727 State.regs[REG_MDR] = next_pc;
2728 State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2729 }
2730
2731 /* ret reg_list, imm8 */
2732 void OP_DF0000 (insn, extension)
2733 unsigned long insn, extension;
2734 {
2735 unsigned int sp;
2736 unsigned long mask;
2737
2738 State.regs[REG_SP] += insn & 0xff;
2739 State.pc = State.regs[REG_MDR] - 3;
2740 sp = State.regs[REG_SP];
2741
2742 mask = (insn & 0xff00) >> 8;
2743
2744 if (mask & 0x8)
2745 {
2746 sp += 4;
2747 State.regs[REG_LAR] = load_mem (sp, 4);
2748 sp += 4;
2749 State.regs[REG_LIR] = load_mem (sp, 4);
2750 sp += 4;
2751 State.regs[REG_MDR] = load_mem (sp, 4);
2752 sp += 4;
2753 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2754 sp += 4;
2755 State.regs[REG_A0] = load_mem (sp, 4);
2756 sp += 4;
2757 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2758 sp += 4;
2759 State.regs[REG_D0] = load_mem (sp, 4);
2760 sp += 4;
2761 }
2762
2763 if (mask & 0x10)
2764 {
2765 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2766 sp += 4;
2767 }
2768
2769 if (mask & 0x20)
2770 {
2771 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2772 sp += 4;
2773 }
2774
2775 if (mask & 0x40)
2776 {
2777 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2778 sp += 4;
2779 }
2780
2781 if (mask & 0x80)
2782 {
2783 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2784 sp += 4;
2785 }
2786 }
2787
2788 /* retf reg_list,imm8 */
2789 void OP_DE0000 (insn, extension)
2790 unsigned long insn, extension;
2791 {
2792 unsigned int sp;
2793 unsigned long mask;
2794
2795 State.regs[REG_SP] += insn & 0xff;
2796 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2797 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2798 State.pc -= 3;
2799
2800 sp = State.regs[REG_SP];
2801
2802 mask = (insn & 0xff00) >> 8;
2803
2804 if (mask & 0x8)
2805 {
2806 sp += 4;
2807 State.regs[REG_LAR] = load_mem (sp, 4);
2808 sp += 4;
2809 State.regs[REG_LIR] = load_mem (sp, 4);
2810 sp += 4;
2811 State.regs[REG_MDR] = load_mem (sp, 4);
2812 sp += 4;
2813 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2814 sp += 4;
2815 State.regs[REG_A0] = load_mem (sp, 4);
2816 sp += 4;
2817 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2818 sp += 4;
2819 State.regs[REG_D0] = load_mem (sp, 4);
2820 sp += 4;
2821 }
2822
2823 if (mask & 0x10)
2824 {
2825 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2826 sp += 4;
2827 }
2828
2829 if (mask & 0x20)
2830 {
2831 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2832 sp += 4;
2833 }
2834
2835 if (mask & 0x40)
2836 {
2837 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2838 sp += 4;
2839 }
2840
2841 if (mask & 0x80)
2842 {
2843 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2844 sp += 4;
2845 }
2846 }
2847
2848 /* rets */
2849 void OP_F0FC (insn, extension)
2850 unsigned long insn, extension;
2851 {
2852 unsigned int sp;
2853
2854 sp = State.regs[REG_SP];
2855 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2856 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2857 State.pc -= 2;
2858 }
2859
2860 /* rti */
2861 void OP_F0FD (insn, extension)
2862 unsigned long insn, extension;
2863 {
2864 abort ();
2865 }
2866
2867 /* trap */
2868 void OP_F0FE (insn, extension)
2869 unsigned long insn, extension;
2870 {
2871 /* We use this for simulated system calls; we may need to change
2872 it to a reserved instruction if we conflict with uses at
2873 Matsushita. */
2874 int save_errno = errno;
2875 errno = 0;
2876
2877 /* Registers passed to trap 0 */
2878
2879 /* Function number. */
2880 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2881
2882 /* Parameters. */
2883 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2884 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2885 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2886
2887 /* Registers set by trap 0 */
2888
2889 #define RETVAL State.regs[0] /* return value */
2890 #define RETERR State.regs[1] /* return error code */
2891
2892 /* Turn a pointer in a register into a pointer into real memory. */
2893
2894 #define MEMPTR(x) (State.mem + x)
2895
2896 switch (FUNC)
2897 {
2898 #if !defined(__GO32__) && !defined(_WIN32)
2899 case SYS_fork:
2900 RETVAL = fork ();
2901 break;
2902 case SYS_execve:
2903 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2904 (char **)MEMPTR (PARM3));
2905 break;
2906 case SYS_execv:
2907 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2908 break;
2909 #endif
2910
2911 case SYS_read:
2912 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2913 MEMPTR (PARM2), PARM3);
2914 break;
2915 case SYS_write:
2916 if (PARM1 == 1)
2917 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2918 MEMPTR (PARM2), PARM3);
2919 else
2920 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2921 MEMPTR (PARM2), PARM3);
2922 break;
2923 case SYS_lseek:
2924 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2925 break;
2926 case SYS_close:
2927 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2928 break;
2929 case SYS_open:
2930 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2931 break;
2932 case SYS_exit:
2933 /* EXIT - caller can look in PARM1 to work out the
2934 reason */
2935 if (PARM1 == 0xdead || PARM1 == 0x1)
2936 State.exception = SIGABRT;
2937 else
2938 State.exception = SIGQUIT;
2939 break;
2940
2941 case SYS_stat: /* added at hmsi */
2942 /* stat system call */
2943 {
2944 struct stat host_stat;
2945 reg_t buf;
2946
2947 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2948
2949 buf = PARM2;
2950
2951 /* Just wild-assed guesses. */
2952 store_mem (buf, 2, host_stat.st_dev);
2953 store_mem (buf + 2, 2, host_stat.st_ino);
2954 store_mem (buf + 4, 4, host_stat.st_mode);
2955 store_mem (buf + 8, 2, host_stat.st_nlink);
2956 store_mem (buf + 10, 2, host_stat.st_uid);
2957 store_mem (buf + 12, 2, host_stat.st_gid);
2958 store_mem (buf + 14, 2, host_stat.st_rdev);
2959 store_mem (buf + 16, 4, host_stat.st_size);
2960 store_mem (buf + 20, 4, host_stat.st_atime);
2961 store_mem (buf + 28, 4, host_stat.st_mtime);
2962 store_mem (buf + 36, 4, host_stat.st_ctime);
2963 }
2964 break;
2965
2966 case SYS_chown:
2967 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2968 break;
2969 case SYS_chmod:
2970 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2971 break;
2972 case SYS_time:
2973 RETVAL = time (MEMPTR (PARM1));
2974 break;
2975 case SYS_times:
2976 {
2977 struct tms tms;
2978 RETVAL = times (&tms);
2979 store_mem (PARM1, 4, tms.tms_utime);
2980 store_mem (PARM1 + 4, 4, tms.tms_stime);
2981 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2982 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2983 break;
2984 }
2985 case SYS_gettimeofday:
2986 {
2987 struct timeval t;
2988 struct timezone tz;
2989 RETVAL = gettimeofday (&t, &tz);
2990 store_mem (PARM1, 4, t.tv_sec);
2991 store_mem (PARM1 + 4, 4, t.tv_usec);
2992 store_mem (PARM2, 4, tz.tz_minuteswest);
2993 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2994 break;
2995 }
2996 case SYS_utime:
2997 /* Cast the second argument to void *, to avoid type mismatch
2998 if a prototype is present. */
2999 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
3000 break;
3001 default:
3002 abort ();
3003 }
3004 RETERR = errno;
3005 errno = save_errno;
3006 }
3007
3008 /* rtm */
3009 void OP_F0FF (insn, extension)
3010 unsigned long insn, extension;
3011 {
3012 abort ();
3013 }
3014
3015 /* nop */
3016 void OP_CB (insn, extension)
3017 unsigned long insn, extension;
3018 {
3019 }
3020
3021 /* putx */
3022 void OP_F500 (insn, extension)
3023 unsigned long insn, extension;
3024 {
3025 }
3026
3027 /* getx */
3028 void OP_F6F0 (insn, extension)
3029 unsigned long insn, extension;
3030 {
3031 }
3032
3033 /* mulq */
3034 void OP_F600 (insn, extension)
3035 unsigned long insn, extension;
3036 {
3037 }
3038
3039 /* mulq */
3040 void OP_F90000 (insn, extension)
3041 unsigned long insn, extension;
3042 {
3043 }
3044
3045 /* mulq */
3046 void OP_FB000000 (insn, extension)
3047 unsigned long insn, extension;
3048 {
3049 }
3050
3051 /* mulq */
3052 void OP_FD000000 (insn, extension)
3053 unsigned long insn, extension;
3054 {
3055 }
3056
3057 /* mulqu */
3058 void OP_F610 (insn, extension)
3059 unsigned long insn, extension;
3060 {
3061 }
3062
3063 /* mulqu */
3064 void OP_F91400 (insn, extension)
3065 unsigned long insn, extension;
3066 {
3067 }
3068
3069 /* mulqu */
3070 void OP_FB140000 (insn, extension)
3071 unsigned long insn, extension;
3072 {
3073 }
3074
3075 /* mulqu */
3076 void OP_FD140000 (insn, extension)
3077 unsigned long insn, extension;
3078 {
3079 }
3080
3081 /* sat16 */
3082 void OP_F640 (insn, extension)
3083 unsigned long insn, extension;
3084 {
3085 }
3086
3087 /* sat24 */
3088 void OP_F650 (insn, extension)
3089 unsigned long insn, extension;
3090 {
3091 }
3092
3093 /* bsch */
3094 void OP_F670 (insn, extension)
3095 unsigned long insn, extension;
3096 {
3097 }
GDB Binutils - Deliverables
This page took 0.157058 seconds and 5 git commands to generate.