sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov imm8, dn */
  66 void OP_8000 ()
  67 {
  68   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
  69 }
  70
  71 /* mov dm, dn */
  72 void OP_80 ()
  73 {
  74   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
  75 }
  76
  77 /* mov dm, an */
  78 void OP_F1E0 ()
  79 {
  80   State.regs[REG_A0 + ((insn & 0xc) >> 2)] = State.regs[REG_D0 + (insn & 0x3)];
  81 }
  82
  83 /* mov am, dn */
  84 void OP_F1D0 ()
  85 {
  86   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  87 }
  88
  89 /* mov imm8, an */
  90 void OP_9000 ()
  91 {
  92   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
  93 }
  94
  95 /* mov am, an */
  96 void OP_90 ()
  97 {
  98   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  99 }
 100
 101 /* mov sp, an */
 102 void OP_3C ()
 103 {
 104   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
 105 }
 106
 107 /* mov am, sp */
 108 void OP_F2F0 ()
 109 {
 110   State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 111 }
 112
 113 /* mov psw, dn */
 114 void OP_F2E4 ()
 115 {
 116   State.regs[REG_D0 + (insn & 0x3)] = PSW;
 117 }
 118
 119 /* mov dm, psw */
 120 void OP_F2F3 ()
 121 {
 122   PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 123 }
 124
 125 /* mov mdr, dn */
 126 void OP_F2E0 ()
 127 {
 128   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
 129 }
 130
 131 /* mov dm, mdr */
 132 void OP_F2F2 ()
 133 {
 134   State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 135 }
 136
 137 /* mov (am), dn */
 138 void OP_70 ()
 139 {
 140   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 141     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 142 }
 143
 144 /* mov (d8,am), dn */
 145 void OP_F80000 ()
 146 {
 147   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 148     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 149                  + SEXT8 (insn & 0xff)), 4);
 150 }
 151
 152 /* mov (d16,am), dn */
 153 void OP_FA000000 ()
 154 {
 155   State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
 156     = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 157                  + SEXT16 (insn & 0xffff)), 4);
 158 }
 159
 160 /* mov */
 161 void OP_FC000000 ()
 162 {
 163 }
 164
 165 /* mov (d8,sp), dn */
 166 void OP_5800 ()
 167 {
 168   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 169     = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
 170 }
 171
 172 /* mov (d16,sp), dn */
 173 void OP_FAB40000 ()
 174 {
 175   State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
 176     = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
 177 }
 178
 179 /* mov */
 180 void OP_FCB40000 ()
 181 {
 182 }
 183
 184 /* mov (di,am), dn */
 185 void OP_F300 ()
 186 {
 187   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 188     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 189                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 190 }
 191
 192 /* mov (abs16), dn */
 193 void OP_300000 ()
 194 {
 195   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
 196 }
 197
 198 /* mov */
 199 void OP_FCA40000 ()
 200 {
 201 }
 202
 203 /* mov (am), an */
 204 void OP_F000 ()
 205 {
 206   State.regs[REG_A0 + ((insn & 0xc) >> 2)]
 207     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 208 }
 209
 210 /* mov (d8,am), an */
 211 void OP_F82000 ()
 212 {
 213   State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
 214     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 215                  + SEXT8 (insn & 0xff)), 4);
 216 }
 217
 218 /* mov (d16,am), an */
 219 void OP_FA200000 ()
 220 {
 221   State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
 222     = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 223                  + SEXT16 (insn & 0xffff)), 4);
 224 }
 225
 226 /* mov */
 227 void OP_FC200000 ()
 228 {
 229 }
 230
 231 /* mov (d8,sp), an */
 232 void OP_5C00 ()
 233 {
 234   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 235     = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
 236 }
 237
 238 /* mov (d16,sp), an */
 239 void OP_FAB00000 ()
 240 {
 241   State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 242     = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
 243 }
 244
 245 /* mov */
 246 void OP_FCB00000 ()
 247 {
 248 }
 249
 250 /* mov (di,am), an*/
 251 void OP_F380 ()
 252 {
 253   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 254     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 255                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 256 }
 257
 258 /* mov (abs16), an */
 259 void OP_FAA00000 ()
 260 {
 261   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
 262 }
 263
 264 /* mov */
 265 void OP_FCA00000 ()
 266 {
 267 }
 268
 269 /* mov (d8,am), sp */
 270 void OP_F8F000 ()
 271 {
 272   State.regs[REG_SP]
 273     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 274                  + SEXT8 (insn & 0xff)), 4);
 275 }
 276
 277 /* mov dm, (an) */
 278 void OP_60 ()
 279 {
 280   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 281              State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
 282 }
 283
 284 /* mov dm, (d8,an) */
 285 void OP_F81000 ()
 286 {
 287   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 288               + SEXT8 (insn & 0xff)), 4,
 289              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 290 }
 291
 292 /* mov dm (d16,an) */
 293 void OP_FA100000 ()
 294 {
 295   store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 296               + SEXT16 (insn & 0xffff)), 4,
 297              State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 298 }
 299
 300 /* mov */
 301 void OP_FC100000 ()
 302 {
 303 }
 304
 305 /* mov dm, (d8,sp) */
 306 void OP_4200 ()
 307 {
 308   store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
 309              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 310 }
 311
 312 /* mov dm, (d16,sp) */
 313 void OP_FA910000 ()
 314 {
 315   store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
 316              State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 317 }
 318
 319 /* mov */
 320 void OP_FC910000 ()
 321 {
 322 }
 323
 324 /* mov dm, (di,an) */
 325 void OP_F340 ()
 326 {
 327   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 328               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 329              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 330 }
 331
 332 /* mov dm, (abs16) */
 333 void OP_10000 ()
 334 {
 335   store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 336 }
 337
 338 /* mov */
 339 void OP_FC810000 ()
 340 {
 341 }
 342
 343 /* mov am, (an) */
 344 void OP_F010 ()
 345 {
 346   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 347              State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
 348 }
 349
 350 /* mov am, (d8,an) */
 351 void OP_F83000 ()
 352 {
 353   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 354               + SEXT8 (insn & 0xff)), 4,
 355              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 356 }
 357
 358 /* mov am (d16,an) */
 359 void OP_FA300000 ()
 360 {
 361   store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
 362               + SEXT16 (insn & 0xffff)), 4,
 363              State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
 364 }
 365
 366 /* mov */
 367 void OP_FC300000 ()
 368 {
 369 }
 370
 371 /* mov am, (d8,sp) */
 372 void OP_4300 ()
 373 {
 374   store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
 375              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 376 }
 377
 378 /* mov am, (d16,sp) */
 379 void OP_FA900000 ()
 380 {
 381   store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
 382              State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
 383 }
 384
 385 /* mov */
 386 void OP_FC900000 ()
 387 {
 388 }
 389
 390 /* mov am, (di,an) */
 391 void OP_F3C0 ()
 392 {
 393   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 394               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 395              State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
 396 }
 397
 398 /* mov am, (abs16) */
 399 void OP_FA800000 ()
 400 {
 401   store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
 402 }
 403
 404 /* mov */
 405 void OP_FC800000 ()
 406 {
 407 }
 408
 409 /* mov sp, (d8,an) */
 410 void OP_F8F400 ()
 411 {
 412   store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
 413              4, State.regs[REG_SP]);
 414 }
 415
 416 /* mov imm16, dn */
 417 void OP_2C0000 ()
 418 {
 419   unsigned long value;
 420
 421   value = SEXT16 (insn & 0xffff);
 422   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 423 }
 424
 425 /* mov */
 426 void OP_FCCC0000 ()
 427 {
 428 }
 429
 430 /* mov imm16, an */
 431 void OP_240000 ()
 432 {
 433   unsigned long value;
 434
 435   value = insn & 0xffff;
 436   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 437 }
 438
 439 /* mov imm32, an*/
 440 void OP_FCDC0000 ()
 441 {
 442   unsigned long value;
 443
 444   value = (insn & 0xffff) << 16 | extension;
 445   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 446 }
 447
 448 /* movbu (am), dn */
 449 void OP_F040 ()
 450 {
 451   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 452     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
 453 }
 454
 455 /* movbu (d8,am), dn */
 456 void OP_F84000 ()
 457 {
 458   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 459     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 460                  + SEXT8 (insn & 0xff)), 1);
 461 }
 462
 463 /* movbu (d16,am), dn */
 464 void OP_FA400000 ()
 465 {
 466   State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
 467     = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 468                  + SEXT16 (insn & 0xffff)), 1);
 469 }
 470
 471 /* movbu */
 472 void OP_FC400000 ()
 473 {
 474 }
 475
 476 /* movbu (d8,sp), dn */
 477 void OP_F8B800 ()
 478 {
 479   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 480     = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
 481 }
 482
 483 /* movbu (d16,sp), dn */
 484 void OP_FAB80000 ()
 485 {
 486   State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
 487     = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
 488 }
 489
 490 /* movbu */
 491 void OP_FCB80000 ()
 492 {
 493 }
 494
 495 /* movbu (di,am), dn */
 496 void OP_F400 ()
 497 {
 498   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 499     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 500                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
 501 }
 502
 503 /* movbu (abs16), dn */
 504 void OP_340000 ()
 505 {
 506   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
 507 }
 508
 509 /* movbu */
 510 void OP_FCA80000 ()
 511 {
 512 }
 513
 514 /* movbu dm, (an) */
 515 void OP_F050 ()
 516 {
 517   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 518              State.regs[REG_D0 + (insn & 0x3)]);
 519 }
 520
 521 /* movbu dm, (d8,an) */
 522 void OP_F85000 ()
 523 {
 524   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 525               + SEXT8 (insn & 0xff)), 1,
 526              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 527 }
 528
 529 /* movbu dm, (d16,an) */
 530 void OP_FA500000 ()
 531 {
 532   store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 533               + SEXT8 (insn & 0xffff)), 1,
 534              State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 535 }
 536
 537 /* movbu */
 538 void OP_FC500000 ()
 539 {
 540 }
 541
 542 /* movbu dm, (d8,sp) */
 543 void OP_F89200 ()
 544 {
 545   store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
 546              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 547 }
 548
 549 /* movbu dm, (d16,sp) */
 550 void OP_FA920000 ()
 551 {
 552   store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
 553              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 554 }
 555
 556 /* movbu */
 557 void OP_FC920000 ()
 558 {
 559 }
 560
 561 /* movbu dm, (di,an) */
 562 void OP_F440 ()
 563 {
 564   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 565               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
 566              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 567 }
 568
 569 /* movbu dm, (abs16) */
 570 void OP_20000 ()
 571 {
 572   store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 573 }
 574
 575 /* movbu */
 576 void OP_FC820000 ()
 577 {
 578 }
 579
 580 /* movhu (am), dn */
 581 void OP_F060 ()
 582 {
 583   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 584     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
 585 }
 586
 587 /* movhu (d8,am), dn */
 588 void OP_F86000 ()
 589 {
 590   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 591     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 592                  + SEXT8 (insn & 0xff)), 2);
 593 }
 594
 595 /* movhu (d16,am), dn */
 596 void OP_FA600000 ()
 597 {
 598   State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
 599     = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 600                  + SEXT16 (insn & 0xffff)), 2);
 601 }
 602
 603 /* movhu */
 604 void OP_FC600000 ()
 605 {
 606 }
 607
 608 /* movhu (d8,sp) dn */
 609 void OP_F8BC00 ()
 610 {
 611   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 612     = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
 613 }
 614
 615 /* movhu (d16,sp), dn */
 616 void OP_FABC0000 ()
 617 {
 618   State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
 619     = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
 620 }
 621
 622 /* movhu */
 623 void OP_FCBC0000 ()
 624 {
 625 }
 626
 627 /* movhu (di,am), dn */
 628 void OP_F480 ()
 629 {
 630   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 631     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 632                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
 633 }
 634
 635 /* movhu (abs16), dn */
 636 void OP_380000 ()
 637 {
 638   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
 639 }
 640
 641 /* movhu */
 642 void OP_FCAC0000 ()
 643 {
 644 }
 645
 646 /* movhu dm, (an) */
 647 void OP_F070 ()
 648 {
 649   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 2,
 650              State.regs[REG_D0 + (insn & 0x3)]);
 651 }
 652
 653 /* movhu dm, (d8,an) */
 654 void OP_F87000 ()
 655 {
 656   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 657               + SEXT8 (insn & 0xff)), 2,
 658              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 659 }
 660
 661 /* movhu dm, (d16,an) */
 662 void OP_FA700000 ()
 663 {
 664   store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
 665               + SEXT16 (insn & 0xffff)), 2,
 666              State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 667 }
 668
 669 /* movhu */
 670 void OP_FC700000 ()
 671 {
 672 }
 673
 674 /* movhu dm,(d8,sp) */
 675 void OP_F89300 ()
 676 {
 677   store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
 678              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 679 }
 680
 681 /* movhu dm,(d16,sp) */
 682 void OP_FA930000 ()
 683 {
 684   store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
 685              State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 686 }
 687
 688 /* movhu */
 689 void OP_FC930000 ()
 690 {
 691 }
 692
 693 /* movhu dm, (di,an) */
 694 void OP_F4C0 ()
 695 {
 696   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 697               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
 698              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 699 }
 700
 701 /* movhu dm, (abs16) */
 702 void OP_30000 ()
 703 {
 704   store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 705 }
 706
 707 /* movhu */
 708 void OP_FC830000 ()
 709 {
 710 }
 711
 712 /* ext dn */
 713 void OP_F2D0 ()
 714 {
 715   if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
 716     State.regs[REG_MDR] = -1;
 717   else
 718     State.regs[REG_MDR] = 0;
 719 }
 720
 721 /* extb dn */
 722 void OP_10 ()
 723 {
 724   State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
 725 }
 726
 727 /* extbu dn */
 728 void OP_14 ()
 729 {
 730   State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
 731 }
 732
 733 /* exth dn */
 734 void OP_18 ()
 735 {
 736   State.regs[REG_D0 + (insn & 0x3)]
 737     = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
 738 }
 739
 740 /* exthu dn */
 741 void OP_1C ()
 742 {
 743   State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
 744 }
 745
 746 /* movm (sp), reg_list */
 747 void OP_CE00 ()
 748 {
 749   unsigned long sp = State.regs[REG_SP];
 750   unsigned long mask;
 751
 752   mask = insn & 0xff;
 753
 754   if (mask & 0x8)
 755     {
 756       sp += 4;
 757       State.regs[REG_LAR] = load_mem (sp, 4);
 758       sp += 4;
 759       State.regs[REG_LIR] = load_mem (sp, 4);
 760       sp += 4;
 761       State.regs[REG_MDR] = load_mem (sp, 4);
 762       sp += 4;
 763       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 764       sp += 4;
 765       State.regs[REG_A0] = load_mem (sp, 4);
 766       sp += 4;
 767       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 768       sp += 4;
 769       State.regs[REG_D0] = load_mem (sp, 4);
 770       sp += 4;
 771     }
 772
 773   if (mask & 0x10)
 774     {
 775       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 776       sp += 4;
 777     }
 778
 779   if (mask & 0x20)
 780     {
 781       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 782       sp += 4;
 783     }
 784
 785   if (mask & 0x40)
 786     {
 787       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 788       sp += 4;
 789     }
 790
 791   if (mask & 0x80)
 792     {
 793       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 794       sp += 4;
 795     }
 796
 797   /* And make sure to update the stack pointer.  */
 798   State.regs[REG_SP] = sp;
 799 }
 800
 801 /* movm reg_list, (sp) */
 802 void OP_CF00 ()
 803 {
 804   unsigned long sp = State.regs[REG_SP];
 805   unsigned long mask;
 806
 807   mask = insn & 0xff;
 808
 809   if (mask & 0x80)
 810     {
 811       sp -= 4;
 812       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 813     }
 814
 815   if (mask & 0x40)
 816     {
 817       sp -= 4;
 818       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 819     }
 820
 821   if (mask & 0x20)
 822     {
 823       sp -= 4;
 824       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 825     }
 826
 827   if (mask & 0x10)
 828     {
 829       sp -= 4;
 830       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 831     }
 832
 833   if (mask & 0x8)
 834     {
 835       sp -= 4;
 836       State.regs[REG_D0] = load_mem (sp, 4);
 837       sp -= 4;
 838       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 839       sp -= 4;
 840       State.regs[REG_A0] = load_mem (sp, 4);
 841       sp -= 4;
 842       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 843       sp -= 4;
 844       State.regs[REG_MDR] = load_mem (sp, 4);
 845       sp -= 4;
 846       State.regs[REG_LIR] = load_mem (sp, 4);
 847       sp -= 4;
 848       State.regs[REG_LAR] = load_mem (sp, 4);
 849       sp -= 4;
 850     }
 851
 852   /* And make sure to update the stack pointer.  */
 853   State.regs[REG_SP] = sp;
 854 }
 855
 856 /* clr dn */
 857 void OP_0 ()
 858 {
 859   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 860
 861   PSW |= PSW_Z;
 862   PSW &= ~(PSW_V | PSW_C | PSW_N);
 863 }
 864
 865 /* add dm,dn*/
 866 void OP_E0 ()
 867 {
 868   int z, c, n, v;
 869   unsigned long reg1, reg2, value;
 870
 871   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 872   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 873   value = reg1 + reg2;
 874   State.regs[REG_D0 + (insn & 0x3)] = value;
 875
 876   z = (value == 0);
 877   n = (value & 0x80000000);
 878   c = (reg1 < reg2);
 879   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 880        && (reg2 & 0x8000000) != (value & 0x80000000));
 881
 882   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 883   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 884           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 885 }
 886
 887 /* add dm, an */
 888 void OP_F160 ()
 889 {
 890   int z, c, n, v;
 891   unsigned long reg1, reg2, value;
 892
 893   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 894   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 895   value = reg1 + reg2;
 896   State.regs[REG_A0 + (insn & 0x3)] = value;
 897
 898   z = (value == 0);
 899   n = (value & 0x80000000);
 900   c = (reg1 < reg2);
 901   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 902        && (reg2 & 0x8000000) != (value & 0x80000000));
 903
 904   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 905   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 906           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 907 }
 908
 909 /* add am, dn*/
 910 void OP_F150 ()
 911 {
 912   int z, c, n, v;
 913   unsigned long reg1, reg2, value;
 914
 915   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 916   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 917   value = reg1 + reg2;
 918   State.regs[REG_D0 + (insn & 0x3)] = value;
 919
 920   z = (value == 0);
 921   n = (value & 0x80000000);
 922   c = (reg1 < reg2);
 923   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 924        && (reg2 & 0x8000000) != (value & 0x80000000));
 925
 926   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 927   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 928           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 929 }
 930
 931 /* add am,an */
 932 void OP_F170 ()
 933 {
 934   int z, c, n, v;
 935   unsigned long reg1, reg2, value;
 936
 937   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 938   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 939   value = reg1 + reg2;
 940   State.regs[REG_A0 + (insn & 0x3)] = value;
 941
 942   z = (value == 0);
 943   n = (value & 0x80000000);
 944   c = (reg1 < reg2);
 945   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 946        && (reg2 & 0x8000000) != (value & 0x80000000));
 947
 948   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 949   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 950           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 951 }
 952
 953 /* add imm8, dn */
 954 void OP_2800 ()
 955 {
 956   int z, c, n, v;
 957   unsigned long reg1, imm, value;
 958
 959   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 960   imm = SEXT8 (insn & 0xff);
 961   value = reg1 + imm;
 962   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 963
 964   z = (value == 0);
 965   n = (value & 0x80000000);
 966   c = (reg1 < imm);
 967   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 968        && (imm & 0x8000000) != (value & 0x80000000));
 969
 970   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 971   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 972           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 973 }
 974
 975 /* add imm16, dn */
 976 void OP_FAC00000 ()
 977 {
 978   int z, c, n, v;
 979   unsigned long reg1, imm, value;
 980
 981   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 982   imm = SEXT16 (insn & 0xffff);
 983   value = reg1 + imm;
 984   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 985
 986   z = (value == 0);
 987   n = (value & 0x80000000);
 988   c = (reg1 < imm);
 989   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 990        && (imm & 0x8000000) != (value & 0x80000000));
 991
 992   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 993   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 994           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 995 }
 996
 997 /* add imm32,dn */
 998 void OP_FCC00000 ()
 999 {
1000   int z, c, n, v;
1001   unsigned long reg1, imm, value;
1002
1003   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
1004   imm = ((insn & 0xffff) << 16) | extension;
1005   value = reg1 + imm;
1006   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
1007
1008   z = (value == 0);
1009   n = (value & 0x80000000);
1010   c = (reg1 < imm);
1011   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1012        && (imm & 0x8000000) != (value & 0x80000000));
1013
1014   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1015   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1016           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1017 }
1018
1019 /* add imm8, an */
1020 void OP_2000 ()
1021 {
1022   int z, c, n, v;
1023   unsigned long reg1, imm, value;
1024
1025   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
1026   imm = insn & 0xff;
1027   value = reg1 + imm;
1028   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
1029
1030   z = (value == 0);
1031   n = (value & 0x80000000);
1032   c = (reg1 < imm);
1033   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1034        && (imm & 0x8000000) != (value & 0x80000000));
1035
1036   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1037   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1038           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1039 }
1040
1041 /* add imm16, an */
1042 void OP_FAD00000 ()
1043 {
1044   int z, c, n, v;
1045   unsigned long reg1, imm, value;
1046
1047   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
1048   imm = 0xffff;
1049   value = reg1 + imm;
1050   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
1051
1052   z = (value == 0);
1053   n = (value & 0x80000000);
1054   c = (reg1 < imm);
1055   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1056        && (imm & 0x8000000) != (value & 0x80000000));
1057
1058   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1059   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1060           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1061 }
1062
1063 /* add imm32, an */
1064 void OP_FCD00000 ()
1065 {
1066   int z, c, n, v;
1067   unsigned long reg1, imm, value;
1068
1069   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
1070   imm = ((insn & 0xffff) << 16) | extension;
1071   value = reg1 + imm;
1072   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
1073
1074   z = (value == 0);
1075   n = (value & 0x80000000);
1076   c = (reg1 < imm);
1077   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1078        && (imm & 0x8000000) != (value & 0x80000000));
1079
1080   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1081   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1082           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1083 }
1084
1085 /* add imm8, sp*/
1086 void OP_F8FE00 ()
1087 {
1088   int z, c, n, v;
1089   unsigned long reg1, imm, value;
1090
1091   reg1 = State.regs[REG_SP];
1092   imm = SEXT8 (insn & 0xff);
1093   value = reg1 + imm;
1094   State.regs[REG_SP] = value;
1095
1096   z = (value == 0);
1097   n = (value & 0x80000000);
1098   c = (reg1 < imm);
1099   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1100        && (imm & 0x8000000) != (value & 0x80000000));
1101
1102   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1103   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1104           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1105 }
1106
1107 /* add imm16,sp */
1108 void OP_FAFE0000 ()
1109 {
1110   int z, c, n, v;
1111   unsigned long reg1, imm, value;
1112
1113   reg1 = State.regs[REG_SP];
1114   imm = SEXT16 (insn & 0xffff);
1115   value = reg1 + imm;
1116   State.regs[REG_SP] = value;
1117
1118   z = (value == 0);
1119   n = (value & 0x80000000);
1120   c = (reg1 < imm);
1121   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1122        && (imm & 0x8000000) != (value & 0x80000000));
1123
1124   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1125   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1126           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1127 }
1128
1129 /* add */
1130 void OP_FCFE0000 ()
1131 {
1132   int z, c, n, v;
1133   unsigned long reg1, imm, value;
1134
1135   reg1 = State.regs[REG_SP];
1136   imm = ((insn & 0xffff) << 16) | extension;
1137   value = reg1 + imm;
1138   State.regs[REG_SP] = value;
1139
1140   z = (value == 0);
1141   n = (value & 0x80000000);
1142   c = (reg1 < imm);
1143   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1144        && (imm & 0x8000000) != (value & 0x80000000));
1145
1146   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1147   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1148           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1149 }
1150
1151 /* addc */
1152 void OP_F140 ()
1153 {
1154   int z, c, n, v;
1155   unsigned long reg1, reg2, value;
1156
1157   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1158   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1159   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1160   State.regs[REG_D0 + (insn & 0x3)] = value;
1161
1162   z = (value == 0);
1163   n = (value & 0x80000000);
1164   c = (reg1 < reg2);
1165   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1166        && (reg2 & 0x8000000) != (value & 0x80000000));
1167
1168   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1169   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1170           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1171 }
1172
1173 /* sub dm, dn */
1174 void OP_F100 ()
1175 {
1176   int z, c, n, v;
1177   unsigned long reg1, reg2, value;
1178
1179   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1180   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1181   value = reg2 - reg1;
1182
1183   z = (value == 0);
1184   n = (value & 0x80000000);
1185   c = (reg1 < reg2);
1186   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1187        && (reg2 & 0x8000000) != (value & 0x80000000));
1188
1189   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1190   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1191           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1192   State.regs[REG_D0 + (insn & 0x3)] = value;
1193 }
1194
1195 /* sub dm, an */
1196 void OP_F120 ()
1197 {
1198   int z, c, n, v;
1199   unsigned long reg1, reg2, value;
1200
1201   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1202   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1203   value = reg2 - reg1;
1204
1205   z = (value == 0);
1206   n = (value & 0x80000000);
1207   c = (reg1 < reg2);
1208   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1209        && (reg2 & 0x8000000) != (value & 0x80000000));
1210
1211   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1212   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1213           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1214   State.regs[REG_A0 + (insn & 0x3)] = value;
1215 }
1216
1217 /* sub am, dn */
1218 void OP_F110 ()
1219 {
1220   int z, c, n, v;
1221   unsigned long reg1, reg2, value;
1222
1223   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1224   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1225   value = reg2 - reg1;
1226
1227   z = (value == 0);
1228   n = (value & 0x80000000);
1229   c = (reg1 < reg2);
1230   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1231        && (reg2 & 0x8000000) != (value & 0x80000000));
1232
1233   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1234   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1235           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1236   State.regs[REG_D0 + (insn & 0x3)] = value;
1237 }
1238
1239 /* sub am, an */
1240 void OP_F130 ()
1241 {
1242   int z, c, n, v;
1243   unsigned long reg1, reg2, value;
1244
1245   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1246   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1247   value = reg2 - reg1;
1248
1249   z = (value == 0);
1250   n = (value & 0x80000000);
1251   c = (reg1 < reg2);
1252   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1253        && (reg2 & 0x8000000) != (value & 0x80000000));
1254
1255   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1256   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1257           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1258   State.regs[REG_A0 + (insn & 0x3)] = value;
1259 }
1260
1261 /* sub */
1262 void OP_FCC40000 ()
1263 {
1264   int z, c, n, v;
1265   unsigned long reg1, imm, value;
1266
1267   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1268   imm = ((insn & 0xffff) << 16) | extension;
1269   value = reg1 - imm;
1270
1271   z = (value == 0);
1272   n = (value & 0x80000000);
1273   c = (reg1 < imm);
1274   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1275        && (imm & 0x8000000) != (value & 0x80000000));
1276
1277   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1278   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1279           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1280   State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
1281 }
1282
1283 /* sub */
1284 void OP_FCD40000 ()
1285 {
1286   int z, c, n, v;
1287   unsigned long reg1, imm, value;
1288
1289   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1290   imm = ((insn & 0xffff) << 16) | extension;
1291   value = reg1 - imm;
1292
1293   z = (value == 0);
1294   n = (value & 0x80000000);
1295   c = (reg1 < imm);
1296   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1297        && (imm & 0x8000000) != (value & 0x80000000));
1298
1299   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1300   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1301           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1302   State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
1303 }
1304
1305 /* subc */
1306 void OP_F180 ()
1307 {
1308   int z, c, n, v;
1309   unsigned long reg1, reg2, value;
1310
1311   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1312   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1313   value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1314
1315   z = (value == 0);
1316   n = (value & 0x80000000);
1317   c = (reg1 < reg2);
1318   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1319        && (reg2 & 0x8000000) != (value & 0x80000000));
1320
1321   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1322   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1323           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1324   State.regs[REG_D0 + (insn & 0x3)] = value;
1325 }
1326
1327 /* mul */
1328 void OP_F240 ()
1329 {
1330   unsigned long long temp;
1331   int n, z;
1332
1333   temp = (State.regs[REG_D0 + (insn & 0x3)]
1334           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1335   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1336   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1337   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1338   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1339   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1340   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1341 }
1342
1343 /* mulu */
1344 void OP_F250 ()
1345 {
1346   unsigned long long temp;
1347   int n, z;
1348
1349   temp = (State.regs[REG_D0 + (insn & 0x3)]
1350           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1351   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1352   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1353   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1354   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1355   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1356   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1357 }
1358
1359 /* div */
1360 void OP_F260 ()
1361 {
1362   long long temp;
1363   int n, z;
1364
1365   temp = State.regs[REG_MDR];
1366   temp <<= 32;
1367   temp |= State.regs[REG_D0 + (insn & 0x3)];
1368   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1369   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1370   temp = (State.regs[REG_D0 + (insn & 0x3)]
1371           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1372   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1373   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1374   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1375   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1376   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1377   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1378 }
1379
1380 /* divu */
1381 void OP_F270 ()
1382 {
1383   unsigned long long temp;
1384   int n, z;
1385
1386   temp = State.regs[REG_MDR];
1387   temp <<= 32;
1388   temp |= State.regs[REG_D0 + (insn & 0x3)];
1389   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1390   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1391   temp = (State.regs[REG_D0 + (insn & 0x3)]
1392           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1393   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1394   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1395   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1396   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1397   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1398   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1399 }
1400
1401 /* inc dn */
1402 void OP_40 ()
1403 {
1404   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
1405 }
1406
1407 /* inc an */
1408 void OP_41 ()
1409 {
1410   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1411 }
1412
1413 /* inc4 an */
1414 void OP_50 ()
1415 {
1416   State.regs[REG_A0 + (insn & 0x3)] += 4;
1417 }
1418
1419 /* cmp imm8, dn */
1420 void OP_A000 ()
1421 {
1422   int z, c, n, v;
1423   unsigned long reg1, imm, value;
1424
1425   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1426   imm = SEXT8 (insn & 0xff);
1427   value = reg1 - imm;
1428
1429   z = (value == 0);
1430   n = (value & 0x80000000);
1431   c = (reg1 < imm);
1432   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1433        && (imm & 0x8000000) != (value & 0x80000000));
1434
1435   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1436   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1437           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1438 }
1439
1440 /* cmp dm, dn */
1441 void OP_A0 ()
1442 {
1443   int z, c, n, v;
1444   unsigned long reg1, reg2, value;
1445
1446   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1447   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1448   value = reg2 - reg1;
1449
1450   z = (value == 0);
1451   n = (value & 0x80000000);
1452   c = (reg1 < reg2);
1453   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1454        && (reg2 & 0x8000000) != (value & 0x80000000));
1455
1456   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1457   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1458           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1459 }
1460
1461 /* cmp dm, an */
1462 void OP_F1A0 ()
1463 {
1464   int z, c, n, v;
1465   unsigned long reg1, reg2, value;
1466
1467   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1468   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1469   value = reg2 - reg1;
1470
1471   z = (value == 0);
1472   n = (value & 0x80000000);
1473   c = (reg1 < reg2);
1474   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1475        && (reg2 & 0x8000000) != (value & 0x80000000));
1476
1477   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1478   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1479           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1480 }
1481
1482 /* cmp am, dn */
1483 void OP_F190 ()
1484 {
1485   int z, c, n, v;
1486   unsigned long reg1, reg2, value;
1487
1488   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1489   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1490   value = reg2 - reg1;
1491
1492   z = (value == 0);
1493   n = (value & 0x80000000);
1494   c = (reg1 < reg2);
1495   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1496        && (reg2 & 0x8000000) != (value & 0x80000000));
1497
1498   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1499   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1500           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1501 }
1502
1503 /* cmp imm8, an */
1504 void OP_B000 ()
1505 {
1506   int z, c, n, v;
1507   unsigned long reg1, imm, value;
1508
1509   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1510   imm = insn & 0xff;
1511   value = reg1 - imm;
1512
1513   z = (value == 0);
1514   n = (value & 0x80000000);
1515   c = (reg1 < imm);
1516   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1517        && (imm & 0x8000000) != (value & 0x80000000));
1518
1519   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1520   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1521           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1522 }
1523
1524 /* cmp am, an */
1525 void OP_B0 ()
1526 {
1527   int z, c, n, v;
1528   unsigned long reg1, reg2, value;
1529
1530   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1531   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1532   value = reg2 - reg1;
1533
1534   z = (value == 0);
1535   n = (value & 0x80000000);
1536   c = (reg1 < reg2);
1537   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1538        && (reg2 & 0x8000000) != (value & 0x80000000));
1539
1540   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1541   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1542           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1543 }
1544
1545 /* cmp imm16, dn */
1546 void OP_FAC80000 ()
1547 {
1548   int z, c, n, v;
1549   unsigned long reg1, imm, value;
1550
1551   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1552   imm = SEXT16 (insn & 0xffff);
1553   value = reg1 - imm;
1554
1555   z = (value == 0);
1556   n = (value & 0x80000000);
1557   c = (reg1 < imm);
1558   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1559        && (imm & 0x8000000) != (value & 0x80000000));
1560
1561   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1562   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1563           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1564 }
1565
1566 /* cmp imm32, dn */
1567 void OP_FCC80000 ()
1568 {
1569   int z, c, n, v;
1570   unsigned long reg1, imm, value;
1571
1572   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1573   imm = ((insn & 0xffff) << 16) | extension;
1574   value = reg1 - imm;
1575
1576   z = (value == 0);
1577   n = (value & 0x80000000);
1578   c = (reg1 < imm);
1579   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1580        && (imm & 0x8000000) != (value & 0x80000000));
1581
1582   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1583   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1584           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1585 }
1586
1587 /* cmp imm16, an */
1588 void OP_FAD80000 ()
1589 {
1590   int z, c, n, v;
1591   unsigned long reg1, imm, value;
1592
1593   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1594   imm = insn & 0xffff;
1595   value = reg1 - imm;
1596
1597   z = (value == 0);
1598   n = (value & 0x80000000);
1599   c = (reg1 < imm);
1600   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1601        && (imm & 0x8000000) != (value & 0x80000000));
1602
1603   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1604   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1605           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1606 }
1607
1608 /* cmp imm32, an */
1609 void OP_FCD80000 ()
1610 {
1611   int z, c, n, v;
1612   unsigned long reg1, imm, value;
1613
1614   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1615   imm = ((insn & 0xffff) << 16) | extension;
1616   value = reg1 - imm;
1617
1618   z = (value == 0);
1619   n = (value & 0x80000000);
1620   c = (reg1 < imm);
1621   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1622        && (imm & 0x8000000) != (value & 0x80000000));
1623
1624   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1625   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1626           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1627 }
1628
1629 /* and dm, dn */
1630 void OP_F200 ()
1631 {
1632   int n, z;
1633
1634   State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1635   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1636   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1637   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1638   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1639 }
1640
1641 /* and imm8, dn */
1642 void OP_F8E000 ()
1643 {
1644   int n, z;
1645
1646   State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1647   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1648   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1649   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1650   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1651 }
1652
1653 /* and imm16, dn */
1654 void OP_FAE00000 ()
1655 {
1656   int n, z;
1657
1658   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1659   z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1660   n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1661   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1662   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1663 }
1664
1665 /* and */
1666 void OP_FCE00000 ()
1667 {
1668 }
1669
1670 /* and imm16, psw */
1671 void OP_FAFC0000 ()
1672 {
1673   PSW &= (insn & 0xffff);
1674 }
1675
1676 /* or dm, dn*/
1677 void OP_F210 ()
1678 {
1679   int n, z;
1680
1681   State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1682   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1683   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1684   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1685   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1686 }
1687
1688 /* or imm8, dn */
1689 void OP_F8E400 ()
1690 {
1691   int n, z;
1692
1693   State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1694   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1695   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1696   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1697   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1698 }
1699
1700 /* or imm16, dn*/
1701 void OP_FAE40000 ()
1702 {
1703   int n, z;
1704
1705   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1706   z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1707   n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1708   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1709   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1710 }
1711
1712 /* or */
1713 void OP_FCE40000 ()
1714 {
1715 }
1716
1717 /* or imm16,psw */
1718 void OP_FAFD0000 ()
1719 {
1720   PSW |= (insn & 0xffff);
1721 }
1722
1723 /* xor dm, dn*/
1724 void OP_F220 ()
1725 {
1726   int n, z;
1727
1728   State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1729   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1730   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1731   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1732   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1733 }
1734
1735 /* xor imm16, dn */
1736 void OP_FAE80000 ()
1737 {
1738   int n, z;
1739
1740   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1741   z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1742   n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1743   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1745 }
1746
1747 /* xor */
1748 void OP_FCE80000 ()
1749 {
1750 }
1751
1752 /* not */
1753 void OP_F230 ()
1754 {
1755   int n, z;
1756
1757   State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1758   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1759   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1760   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1761   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1762 }
1763
1764 /* btst imm8, dn */
1765 void OP_F8EC00 ()
1766 {
1767   unsigned long temp;
1768   int z, n;
1769
1770   temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1771   temp &= (insn & 0xff);
1772   n = (temp & 0x80000000) != 0;
1773   z = (temp == 0);
1774   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1775   PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1776 }
1777
1778 /* btst imm16, dn */
1779 void OP_FAEC0000 ()
1780 {
1781   unsigned long temp;
1782   int z, n;
1783
1784   temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1785   temp &= (insn & 0xffff);
1786   n = (temp & 0x80000000) != 0;
1787   z = (temp == 0);
1788   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1789   PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1790 }
1791
1792 /* btst */
1793 void OP_FCEC0000 ()
1794 {
1795 }
1796
1797 /* btst */
1798 void OP_FE020000 ()
1799 {
1800 }
1801
1802 /* btst imm8,(d8,an) */
1803 void OP_FAF80000 ()
1804 {
1805   unsigned long temp;
1806   int n, z;
1807
1808   temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1809                     + SEXT8 ((insn & 0xff00) >> 8)), 1);
1810   temp &= (insn & 0xff);
1811   n = (temp & 0x80000000) != 0;
1812   z = (temp == 0);
1813   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1814   PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1815 }
1816
1817 /* bset dm, (an) */
1818 void OP_F080 ()
1819 {
1820   unsigned long temp;
1821   int z;
1822
1823   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1824   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1825   temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1826   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1827   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1828   PSW |= (z ? PSW_Z : 0);
1829 }
1830
1831 /* bset */
1832 void OP_FE000000 ()
1833 {
1834 }
1835
1836 /* bset imm8,(d8,an) */
1837 void OP_FAF00000 ()
1838 {
1839   unsigned long temp;
1840   int z;
1841
1842   temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1843                     + SEXT8 ((insn & 0xff00) >> 8)), 1);
1844   z = (temp & (insn & 0xff)) == 0;
1845   temp |= (insn & 0xff);
1846   store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1847   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1848   PSW |= (z ? PSW_Z : 0);
1849 }
1850
1851 /* bclr dm, (an) */
1852 void OP_F090 ()
1853 {
1854   unsigned long temp;
1855   int z;
1856
1857   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1858   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1859   temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1860   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1861   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1862   PSW |= (z ? PSW_Z : 0);
1863 }
1864
1865 /* bclr */
1866 void OP_FE010000 ()
1867 {
1868 }
1869
1870 /* bclr imm8,(d8,an) */
1871 void OP_FAF40000 ()
1872 {
1873   unsigned long temp;
1874   int z;
1875
1876   temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1877                     + SEXT8 ((insn & 0xff00) >> 8)), 1);
1878   z = (temp & (insn & 0xff)) == 0;
1879   temp = ~temp & (insn & 0xff);
1880   store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1881   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1882   PSW |= (z ? PSW_Z : 0);
1883 }
1884
1885 /* asr dm, dn */
1886 void OP_F2B0 ()
1887 {
1888   long temp;
1889   int z, n, c;
1890
1891   temp = State.regs[REG_D0 + (insn & 0x3)];
1892   c = temp & 1;
1893   temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1894   State.regs[REG_D0 + (insn & 0x3)] = temp;
1895   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1896   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1897   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1898   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1899 }
1900
1901 /* asr imm8, dn */
1902 void OP_F8C800 ()
1903 {
1904   long temp;
1905   int z, n, c;
1906
1907   temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1908   c = temp & 1;
1909   temp >>= (insn & 0xff);
1910   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
1911   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1912   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1913   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1914   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1915 }
1916
1917 /* lsr dm, dn */
1918 void OP_F2A0 ()
1919 {
1920   int z, n, c;
1921
1922   c = State.regs[REG_D0 + (insn & 0x3)] & 1;
1923   State.regs[REG_D0 + (insn & 0x3)]
1924     >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1925   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1926   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1927   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1928   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1929 }
1930
1931 /* lsr dm, dn */
1932 void OP_F8C400 ()
1933 {
1934   int z, n, c;
1935
1936   c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
1937   State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>=  (insn & 0xff);
1938   z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
1939   n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x8000000) != 0;
1940   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1941   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1942 }
1943
1944 /* asl dm, dn */
1945 void OP_F290 ()
1946 {
1947   int n, z;
1948
1949   State.regs[REG_D0 + (insn & 0x3)]
1950     <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1951   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1952   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1953   PSW &= ~(PSW_Z | PSW_N);
1954   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1955 }
1956
1957 /* asl imm8, dn */
1958 void OP_F8C000 ()
1959 {
1960   int n, z;
1961
1962   State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
1963   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1964   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1965   PSW &= ~(PSW_Z | PSW_N);
1966   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1967 }
1968
1969 /* asl2 dn */
1970 void OP_54 ()
1971 {
1972   int n, z;
1973
1974   State.regs[REG_D0 + (insn & 0x3)] <<= 2;
1975   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1976   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1977   PSW &= ~(PSW_Z | PSW_N);
1978   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1979 }
1980
1981 /* ror dn */
1982 void OP_F284 ()
1983 {
1984   unsigned long value;
1985   int c,n,z;
1986
1987   value = State.regs[REG_D0 + (insn & 0x3)];
1988   if (value & 0x1)
1989     c = 1;
1990
1991   value >>= 1;
1992   value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1993   State.regs[REG_D0 + (insn & 0x3)] = value;
1994   z = (value == 0);
1995   n = (value & 0x8000000) != 0;
1996   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1997   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1998 }
1999
2000 /* rol dn */
2001 void OP_F280 ()
2002 {
2003   unsigned long value;
2004   int c,n,z;
2005
2006   value = State.regs[REG_D0 + (insn & 0x3)];
2007   if (value & 0x80000000)
2008     c = 1;
2009
2010   value <<= 1;
2011   value |= ((PSW & PSW_C) != 0);
2012   State.regs[REG_D0 + (insn & 0x3)] = value;
2013   z = (value == 0);
2014   n = (value & 0x8000000) != 0;
2015   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2016   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2017 }
2018
2019 /* beq label:8 */
2020 void OP_C800 ()
2021 {
2022   /* The dispatching code will add 2 after we return, so
2023      we subtract two here to make things right.  */
2024   if (PSW & PSW_Z)
2025     State.pc += SEXT8 (insn & 0xff) - 2;
2026 }
2027
2028 /* bne label:8 */
2029 void OP_C900 ()
2030 {
2031   /* The dispatching code will add 2 after we return, so
2032      we subtract two here to make things right.  */
2033   if (!(PSW & PSW_Z))
2034     State.pc += SEXT8 (insn & 0xff) - 2;
2035 }
2036
2037 /* bgt label:8 */
2038 void OP_C100 ()
2039 {
2040   /* The dispatching code will add 2 after we return, so
2041      we subtract two here to make things right.  */
2042   if (!((PSW & PSW_Z)
2043         || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2044     State.pc += SEXT8 (insn & 0xff) - 2;
2045 }
2046
2047 /* bge label:8 */
2048 void OP_C200 ()
2049 {
2050   /* The dispatching code will add 2 after we return, so
2051      we subtract two here to make things right.  */
2052   if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2053     State.pc += SEXT8 (insn & 0xff) - 2;
2054 }
2055
2056 /* ble label:8 */
2057 void OP_C300 ()
2058 {
2059   /* The dispatching code will add 2 after we return, so
2060      we subtract two here to make things right.  */
2061   if ((PSW & PSW_Z)
2062        || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2063     State.pc += SEXT8 (insn & 0xff) - 2;
2064 }
2065
2066 /* blt label:8 */
2067 void OP_C000 ()
2068 {
2069   /* The dispatching code will add 2 after we return, so
2070      we subtract two here to make things right.  */
2071   if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2072     State.pc += SEXT8 (insn & 0xff) - 2;
2073 }
2074
2075 /* bhi label:8 */
2076 void OP_C500 ()
2077 {
2078   /* The dispatching code will add 2 after we return, so
2079      we subtract two here to make things right.  */
2080   if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2081     State.pc += SEXT8 (insn & 0xff) - 2;
2082 }
2083
2084 /* bcc label:8 */
2085 void OP_C600 ()
2086 {
2087   /* The dispatching code will add 2 after we return, so
2088      we subtract two here to make things right.  */
2089   if (!(PSW & PSW_C))
2090     State.pc += SEXT8 (insn & 0xff) - 2;
2091 }
2092
2093 /* bls label:8 */
2094 void OP_C700 ()
2095 {
2096   /* The dispatching code will add 2 after we return, so
2097      we subtract two here to make things right.  */
2098   if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2099     State.pc += SEXT8 (insn & 0xff) - 2;
2100 }
2101
2102 /* bcs label:8 */
2103 void OP_C400 ()
2104 {
2105   /* The dispatching code will add 2 after we return, so
2106      we subtract two here to make things right.  */
2107   if (PSW & PSW_C)
2108     State.pc += SEXT8 (insn & 0xff) - 2;
2109 }
2110
2111 /* bvc label:8 */
2112 void OP_F8E800 ()
2113 {
2114   /* The dispatching code will add 3 after we return, so
2115      we subtract two here to make things right.  */
2116   if (!(PSW & PSW_V))
2117     State.pc += SEXT8 (insn & 0xff) - 3;
2118 }
2119
2120 /* bvs label:8 */
2121 void OP_F8E900 ()
2122 {
2123   /* The dispatching code will add 3 after we return, so
2124      we subtract two here to make things right.  */
2125   if (PSW & PSW_V)
2126     State.pc += SEXT8 (insn & 0xff) - 3;
2127 }
2128
2129 /* bnc label:8 */
2130 void OP_F8EA00 ()
2131 {
2132   /* The dispatching code will add 3 after we return, so
2133      we subtract two here to make things right.  */
2134   if (!(PSW & PSW_N))
2135     State.pc += SEXT8 (insn & 0xff) - 3;
2136 }
2137
2138 /* bns label:8 */
2139 void OP_F8EB00 ()
2140 {
2141   /* The dispatching code will add 3 after we return, so
2142      we subtract two here to make things right.  */
2143   if (PSW & PSW_N)
2144     State.pc += SEXT8 (insn & 0xff) - 3;
2145 }
2146
2147 /* bra label:8 */
2148 void OP_CA00 ()
2149 {
2150   /* The dispatching code will add 2 after we return, so
2151      we subtract two here to make things right.  */
2152   State.pc += SEXT8 (insn & 0xff) - 2;
2153 }
2154
2155 /* leq */
2156 void OP_D8 ()
2157 {
2158  abort ();
2159 }
2160
2161 /* lne */
2162 void OP_D9 ()
2163 {
2164  abort ();
2165 }
2166
2167 /* lgt */
2168 void OP_D1 ()
2169 {
2170  abort ();
2171 }
2172
2173 /* lge */
2174 void OP_D2 ()
2175 {
2176  abort ();
2177 }
2178
2179 /* lle */
2180 void OP_D3 ()
2181 {
2182  abort ();
2183 }
2184
2185 /* llt */
2186 void OP_D0 ()
2187 {
2188  abort ();
2189 }
2190
2191 /* lhi */
2192 void OP_D5 ()
2193 {
2194  abort ();
2195 }
2196
2197 /* lcc */
2198 void OP_D6 ()
2199 {
2200  abort ();
2201 }
2202
2203 /* lls */
2204 void OP_D7 ()
2205 {
2206  abort ();
2207 }
2208
2209 /* lcs */
2210 void OP_D4 ()
2211 {
2212  abort ();
2213 }
2214
2215 /* lra */
2216 void OP_DA ()
2217 {
2218  abort ();
2219 }
2220
2221 /* setlb */
2222 void OP_DB ()
2223 {
2224  abort ();
2225 }
2226
2227 /* jmp (an) */
2228 void OP_F0F4 ()
2229 {
2230   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2231 }
2232
2233 /* jmp label:16 */
2234 void OP_CC0000 ()
2235 {
2236   State.pc += SEXT16 (insn & 0xffff) - 3;
2237 }
2238
2239 /* jmp label:32 */
2240 void OP_DC000000 ()
2241 {
2242   State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2243 }
2244
2245 /* call label:16,reg_list,imm8 */
2246 void OP_CD000000 ()
2247 {
2248   unsigned int next_pc, sp, adjust;
2249   unsigned long mask;
2250
2251   sp = State.regs[REG_SP];
2252   next_pc = State.pc + 2;
2253   State.mem[sp] = next_pc & 0xff;
2254   State.mem[sp+1] = next_pc & 0xff00;
2255   State.mem[sp+2] = next_pc & 0xff0000;
2256   State.mem[sp+3] = next_pc & 0xff000000;
2257
2258   mask = insn & 0xff;
2259
2260   adjust = 0;
2261   if (mask & 0x80)
2262     {
2263       adjust -= 4;
2264       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2265     }
2266
2267   if (mask & 0x40)
2268     {
2269       adjust -= 4;
2270       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2271     }
2272
2273   if (mask & 0x20)
2274     {
2275       adjust -= 4;
2276       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2277     }
2278
2279   if (mask & 0x10)
2280     {
2281       adjust -= 4;
2282       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2283     }
2284
2285   if (mask & 0x8)
2286     {
2287       adjust -= 4;
2288       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2289       adjust -= 4;
2290       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2291       adjust -= 4;
2292       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2293       adjust -= 4;
2294       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2295       adjust -= 4;
2296       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2297       adjust -= 4;
2298       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2299       adjust -= 4;
2300       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2301       adjust -= 4;
2302     }
2303
2304   /* And make sure to update the stack pointer.  */
2305   State.regs[REG_SP] -= extension;
2306   State.regs[REG_MDR] = next_pc;
2307   State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2308 }
2309
2310 /* call label:32,reg_list,imm8*/
2311 void OP_DD000000 ()
2312 {
2313   unsigned int next_pc, sp, adjust;
2314   unsigned long mask;
2315
2316   sp = State.regs[REG_SP];
2317   next_pc = State.pc + 2;
2318   State.mem[sp] = next_pc & 0xff;
2319   State.mem[sp+1] = next_pc & 0xff00;
2320   State.mem[sp+2] = next_pc & 0xff0000;
2321   State.mem[sp+3] = next_pc & 0xff000000;
2322
2323   mask = (extension & 0xff00) >> 8;
2324
2325   adjust = 0;
2326   if (mask & 0x80)
2327     {
2328       adjust -= 4;
2329       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2330     }
2331
2332   if (mask & 0x40)
2333     {
2334       adjust -= 4;
2335       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2336     }
2337
2338   if (mask & 0x20)
2339     {
2340       adjust -= 4;
2341       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2342     }
2343
2344   if (mask & 0x10)
2345     {
2346       adjust -= 4;
2347       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2348     }
2349
2350   if (mask & 0x8)
2351     {
2352       adjust -= 4;
2353       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2354       adjust -= 4;
2355       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2356       adjust -= 4;
2357       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2358       adjust -= 4;
2359       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2360       adjust -= 4;
2361       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2362       adjust -= 4;
2363       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2364       adjust -= 4;
2365       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2366       adjust -= 4;
2367     }
2368
2369   /* And make sure to update the stack pointer.  */
2370   State.regs[REG_SP] -= (extension & 0xff);
2371   State.regs[REG_MDR] = next_pc;
2372   State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2373 }
2374
2375 /* calls (an) */
2376 void OP_F0F0 ()
2377 {
2378   unsigned int next_pc, sp;
2379
2380   sp = State.regs[REG_SP];
2381   next_pc = State.pc + 2;
2382   State.mem[sp] = next_pc & 0xff;
2383   State.mem[sp+1] = next_pc & 0xff00;
2384   State.mem[sp+2] = next_pc & 0xff0000;
2385   State.mem[sp+3] = next_pc & 0xff000000;
2386   State.regs[REG_MDR] = next_pc;
2387   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2388 }
2389
2390 /* calls label:16 */
2391 void OP_FAFF0000 ()
2392 {
2393   unsigned int next_pc, sp;
2394
2395   sp = State.regs[REG_SP];
2396   next_pc = State.pc + 4;
2397   State.mem[sp] = next_pc & 0xff;
2398   State.mem[sp+1] = next_pc & 0xff00;
2399   State.mem[sp+2] = next_pc & 0xff0000;
2400   State.mem[sp+3] = next_pc & 0xff000000;
2401   State.regs[REG_MDR] = next_pc;
2402   State.pc += SEXT16 (insn & 0xffff) - 4;
2403 }
2404
2405 /* calls label:32 */
2406 void OP_FCFF0000 ()
2407 {
2408   unsigned int next_pc, sp;
2409
2410   sp = State.regs[REG_SP];
2411   next_pc = State.pc + 6;
2412   State.mem[sp] = next_pc & 0xff;
2413   State.mem[sp+1] = next_pc & 0xff00;
2414   State.mem[sp+2] = next_pc & 0xff0000;
2415   State.mem[sp+3] = next_pc & 0xff000000;
2416   State.regs[REG_MDR] = next_pc;
2417   State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2418 }
2419
2420 /* ret */
2421 void OP_DF0000 ()
2422 {
2423   unsigned int sp;
2424   unsigned long mask;
2425
2426   State.regs[REG_SP] += insn & 0xff;
2427   State.pc = State.regs[REG_MDR] - 3;
2428   sp = State.regs[REG_SP];
2429
2430   mask = (insn & 0xff00) >> 8;
2431
2432   if (mask & 0x8)
2433     {
2434       sp += 4;
2435       State.regs[REG_LAR] = load_mem (sp, 4);
2436       sp += 4;
2437       State.regs[REG_LIR] = load_mem (sp, 4);
2438       sp += 4;
2439       State.regs[REG_MDR] = load_mem (sp, 4);
2440       sp += 4;
2441       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2442       sp += 4;
2443       State.regs[REG_A0] = load_mem (sp, 4);
2444       sp += 4;
2445       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2446       sp += 4;
2447       State.regs[REG_D0] = load_mem (sp, 4);
2448       sp += 4;
2449     }
2450
2451   if (mask & 0x10)
2452     {
2453       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2454       sp += 4;
2455     }
2456
2457   if (mask & 0x20)
2458     {
2459       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2460       sp += 4;
2461     }
2462
2463   if (mask & 0x40)
2464     {
2465       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2466       sp += 4;
2467     }
2468
2469   if (mask & 0x80)
2470     {
2471       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2472       sp += 4;
2473     }
2474 }
2475
2476 /* retf reg_list,imm8 */
2477 void OP_DE0000 ()
2478 {
2479   unsigned int sp;
2480   unsigned long mask;
2481
2482   State.regs[REG_SP] += insn & 0xff;
2483   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2484               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2485   State.pc -= 3;
2486
2487   sp = State.regs[REG_SP];
2488
2489   mask = (insn & 0xff00) >> 8;
2490
2491   if (mask & 0x8)
2492     {
2493       sp += 4;
2494       State.regs[REG_LAR] = load_mem (sp, 4);
2495       sp += 4;
2496       State.regs[REG_LIR] = load_mem (sp, 4);
2497       sp += 4;
2498       State.regs[REG_MDR] = load_mem (sp, 4);
2499       sp += 4;
2500       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2501       sp += 4;
2502       State.regs[REG_A0] = load_mem (sp, 4);
2503       sp += 4;
2504       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2505       sp += 4;
2506       State.regs[REG_D0] = load_mem (sp, 4);
2507       sp += 4;
2508     }
2509
2510   if (mask & 0x10)
2511     {
2512       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2513       sp += 4;
2514     }
2515
2516   if (mask & 0x20)
2517     {
2518       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2519       sp += 4;
2520     }
2521
2522   if (mask & 0x40)
2523     {
2524       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2525       sp += 4;
2526     }
2527
2528   if (mask & 0x80)
2529     {
2530       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2531       sp += 4;
2532     }
2533 }
2534
2535 /* rets */
2536 void OP_F0FC ()
2537 {
2538   unsigned int sp;
2539
2540   sp = State.regs[REG_SP];
2541   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2542               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2543   State.pc -= 2;
2544 }
2545
2546 /* rti */
2547 void OP_F0FD ()
2548 {
2549   abort ();
2550 }
2551
2552 /* trap */
2553 void OP_F0FE ()
2554 {
2555  abort ();
2556 }
2557
2558 /* rtm */
2559 void OP_F0FF ()
2560 {
2561  abort ();
2562 }
2563
2564 /* nop */
2565 void OP_CB ()
2566 {
2567 }
2568
2569 /* putx */
2570 void OP_F500 ()
2571 {
2572 }
2573
2574 /* getx */
2575 void OP_F6F0 ()
2576 {
2577 }
2578
2579 /* mulq */
2580 void OP_F600 ()
2581 {
2582 }
2583
2584 /* mulq */
2585 void OP_F90000 ()
2586 {
2587 }
2588
2589 /* mulq */
2590 void OP_FB000000 ()
2591 {
2592 }
2593
2594 /* mulq */
2595 void OP_FD000000 ()
2596 {
2597 }
2598
2599 /* mulqu */
2600 void OP_F610 ()
2601 {
2602 }
2603
2604 /* mulqu */
2605 void OP_F91400 ()
2606 {
2607 }
2608
2609 /* mulqu */
2610 void OP_FB140000 ()
2611 {
2612 }
2613
2614 /* mulqu */
2615 void OP_FD140000 ()
2616 {
2617 }
2618
2619 /* sat16 */
2620 void OP_F640 ()
2621 {
2622 }
2623
2624 /* sat24 */
2625 void OP_F650 ()
2626 {
2627 }
2628
2629 /* bsch */
2630 void OP_F670 ()
2631 {
2632 }