7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
25 void OP_8000 (insn
, extension
)
26 unsigned long insn
, extension
;
28 State
.regs
[REG_D0
+ REG0_8 (insn
)] = SEXT8 (insn
& 0xff);
32 void OP_80 (insn
, extension
)
33 unsigned long insn
, extension
;
35 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
39 void OP_F1E0 (insn
, extension
)
40 unsigned long insn
, extension
;
42 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
46 void OP_F1D0 (insn
, extension
)
47 unsigned long insn
, extension
;
49 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
53 void OP_9000 (insn
, extension
)
54 unsigned long insn
, extension
;
56 State
.regs
[REG_A0
+ REG0_8 (insn
)] = insn
& 0xff;
60 void OP_90 (insn
, extension
)
61 unsigned long insn
, extension
;
63 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
67 void OP_3C (insn
, extension
)
68 unsigned long insn
, extension
;
70 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_SP
];
74 void OP_F2F0 (insn
, extension
)
75 unsigned long insn
, extension
;
77 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ REG1 (insn
)];
81 void OP_F2E4 (insn
, extension
)
82 unsigned long insn
, extension
;
84 State
.regs
[REG_D0
+ REG0 (insn
)] = PSW
;
88 void OP_F2F3 (insn
, extension
)
89 unsigned long insn
, extension
;
91 PSW
= State
.regs
[REG_D0
+ REG1 (insn
)];
95 void OP_F2E0 (insn
, extension
)
96 unsigned long insn
, extension
;
98 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_MDR
];
102 void OP_F2F2 (insn
, extension
)
103 unsigned long insn
, extension
;
105 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ REG1 (insn
)];
109 void OP_70 (insn
, extension
)
110 unsigned long insn
, extension
;
112 State
.regs
[REG_D0
+ REG1 (insn
)]
113 = load_word (State
.regs
[REG_A0
+ REG0 (insn
)]);
116 /* mov (d8,am), dn */
117 void OP_F80000 (insn
, extension
)
118 unsigned long insn
, extension
;
120 State
.regs
[REG_D0
+ REG1_8 (insn
)]
121 = load_word ((State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff)));
124 /* mov (d16,am), dn */
125 void OP_FA000000 (insn
, extension
)
126 unsigned long insn
, extension
;
128 State
.regs
[REG_D0
+ REG1_16 (insn
)]
129 = load_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
130 + SEXT16 (insn
& 0xffff)));
133 /* mov (d32,am), dn */
134 void OP_FC000000 (insn
, extension
)
135 unsigned long insn
, extension
;
137 State
.regs
[REG_D0
+ REG1_16 (insn
)]
138 = load_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
139 + ((insn
& 0xffff) << 16) + extension
));
142 /* mov (d8,sp), dn */
143 void OP_5800 (insn
, extension
)
144 unsigned long insn
, extension
;
146 State
.regs
[REG_D0
+ REG0_8 (insn
)]
147 = load_word (State
.regs
[REG_SP
] + (insn
& 0xff));
150 /* mov (d16,sp), dn */
151 void OP_FAB40000 (insn
, extension
)
152 unsigned long insn
, extension
;
154 State
.regs
[REG_D0
+ REG0_16 (insn
)]
155 = load_word (State
.regs
[REG_SP
] + (insn
& 0xffff));
158 /* mov (d32,sp), dn */
159 void OP_FCB40000 (insn
, extension
)
160 unsigned long insn
, extension
;
162 State
.regs
[REG_D0
+ REG0_16 (insn
)]
163 = load_word (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
));
166 /* mov (di,am), dn */
167 void OP_F300 (insn
, extension
)
168 unsigned long insn
, extension
;
170 State
.regs
[REG_D0
+ REG0_4 (insn
)]
171 = load_word ((State
.regs
[REG_A0
+ REG0 (insn
)]
172 + State
.regs
[REG_D0
+ REG1 (insn
)]));
175 /* mov (abs16), dn */
176 void OP_300000 (insn
, extension
)
177 unsigned long insn
, extension
;
179 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_word ((insn
& 0xffff));
182 /* mov (abs32), dn */
183 void OP_FCA40000 (insn
, extension
)
184 unsigned long insn
, extension
;
186 State
.regs
[REG_D0
+ REG0_16 (insn
)]
187 = load_word ((((insn
& 0xffff) << 16) + extension
));
191 void OP_F000 (insn
, extension
)
192 unsigned long insn
, extension
;
194 State
.regs
[REG_A0
+ REG1 (insn
)]
195 = load_word (State
.regs
[REG_A0
+ REG0 (insn
)]);
198 /* mov (d8,am), an */
199 void OP_F82000 (insn
, extension
)
200 unsigned long insn
, extension
;
202 State
.regs
[REG_A0
+ REG1_8 (insn
)]
203 = load_word ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
204 + SEXT8 (insn
& 0xff)));
207 /* mov (d16,am), an */
208 void OP_FA200000 (insn
, extension
)
209 unsigned long insn
, extension
;
211 State
.regs
[REG_A0
+ REG1_16 (insn
)]
212 = load_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
213 + SEXT16 (insn
& 0xffff)));
216 /* mov (d32,am), an */
217 void OP_FC200000 (insn
, extension
)
218 unsigned long insn
, extension
;
220 State
.regs
[REG_A0
+ REG1_16 (insn
)]
221 = load_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
222 + ((insn
& 0xffff) << 16) + extension
));
225 /* mov (d8,sp), an */
226 void OP_5C00 (insn
, extension
)
227 unsigned long insn
, extension
;
229 State
.regs
[REG_A0
+ REG0_8 (insn
)]
230 = load_word (State
.regs
[REG_SP
] + (insn
& 0xff));
233 /* mov (d16,sp), an */
234 void OP_FAB00000 (insn
, extension
)
235 unsigned long insn
, extension
;
237 State
.regs
[REG_A0
+ REG0_16 (insn
)]
238 = load_word (State
.regs
[REG_SP
] + (insn
& 0xffff));
241 /* mov (d32,sp), an */
242 void OP_FCB00000 (insn
, extension
)
243 unsigned long insn
, extension
;
245 State
.regs
[REG_A0
+ REG0_16 (insn
)]
246 = load_word (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
));
249 /* mov (di,am), an */
250 void OP_F380 (insn
, extension
)
251 unsigned long insn
, extension
;
253 State
.regs
[REG_A0
+ REG0_4 (insn
)]
254 = load_word ((State
.regs
[REG_A0
+ REG0 (insn
)]
255 + State
.regs
[REG_D0
+ REG1 (insn
)]));
258 /* mov (abs16), an */
259 void OP_FAA00000 (insn
, extension
)
260 unsigned long insn
, extension
;
262 State
.regs
[REG_A0
+ REG0_16 (insn
)] = load_word ((insn
& 0xffff));
265 /* mov (abs32), an */
266 void OP_FCA00000 (insn
, extension
)
267 unsigned long insn
, extension
;
269 State
.regs
[REG_A0
+ REG0_16 (insn
)]
270 = load_word ((((insn
& 0xffff) << 16) + extension
));
273 /* mov (d8,am), sp */
274 void OP_F8F000 (insn
, extension
)
275 unsigned long insn
, extension
;
278 = load_word ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
279 + SEXT8 (insn
& 0xff)));
283 void OP_60 (insn
, extension
)
284 unsigned long insn
, extension
;
286 store_word (State
.regs
[REG_A0
+ REG0 (insn
)],
287 State
.regs
[REG_D0
+ REG1 (insn
)]);
290 /* mov dm, (d8,an) */
291 void OP_F81000 (insn
, extension
)
292 unsigned long insn
, extension
;
294 store_word ((State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff)),
295 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
298 /* mov dm (d16,an) */
299 void OP_FA100000 (insn
, extension
)
300 unsigned long insn
, extension
;
302 store_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)] + SEXT16 (insn
& 0xffff)),
303 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
306 /* mov dm (d32,an) */
307 void OP_FC100000 (insn
, extension
)
308 unsigned long insn
, extension
;
310 store_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
311 + ((insn
& 0xffff) << 16) + extension
),
312 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
315 /* mov dm, (d8,sp) */
316 void OP_4200 (insn
, extension
)
317 unsigned long insn
, extension
;
319 store_word (State
.regs
[REG_SP
] + (insn
& 0xff),
320 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
323 /* mov dm, (d16,sp) */
324 void OP_FA910000 (insn
, extension
)
325 unsigned long insn
, extension
;
327 store_word (State
.regs
[REG_SP
] + (insn
& 0xffff),
328 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
331 /* mov dm, (d32,sp) */
332 void OP_FC910000 (insn
, extension
)
333 unsigned long insn
, extension
;
335 store_word (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
),
336 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
339 /* mov dm, (di,an) */
340 void OP_F340 (insn
, extension
)
341 unsigned long insn
, extension
;
343 store_word ((State
.regs
[REG_A0
+ REG0 (insn
)]
344 + State
.regs
[REG_D0
+ REG1 (insn
)]),
345 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
348 /* mov dm, (abs16) */
349 void OP_10000 (insn
, extension
)
350 unsigned long insn
, extension
;
352 store_word ((insn
& 0xffff), State
.regs
[REG_D0
+ REG1_16 (insn
)]);
355 /* mov dm, (abs32) */
356 void OP_FC810000 (insn
, extension
)
357 unsigned long insn
, extension
;
359 store_word ((((insn
& 0xffff) << 16) + extension
),
360 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
364 void OP_F010 (insn
, extension
)
365 unsigned long insn
, extension
;
367 store_word (State
.regs
[REG_A0
+ REG0 (insn
)],
368 State
.regs
[REG_A0
+ REG1 (insn
)]);
371 /* mov am, (d8,an) */
372 void OP_F83000 (insn
, extension
)
373 unsigned long insn
, extension
;
375 store_word ((State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff)),
376 State
.regs
[REG_A0
+ REG1_8 (insn
)]);
379 /* mov am, (d16,an) */
380 void OP_FA300000 (insn
, extension
)
381 unsigned long insn
, extension
;
383 store_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)] + SEXT16 (insn
& 0xffff)),
384 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
387 /* mov am, (d32,an) */
388 void OP_FC300000 (insn
, extension
)
389 unsigned long insn
, extension
;
391 store_word ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
392 + ((insn
& 0xffff) << 16) + extension
),
393 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
396 /* mov am, (d8,sp) */
397 void OP_4300 (insn
, extension
)
398 unsigned long insn
, extension
;
400 store_word (State
.regs
[REG_SP
] + (insn
& 0xff),
401 State
.regs
[REG_A0
+ REG1_8 (insn
)]);
404 /* mov am, (d16,sp) */
405 void OP_FA900000 (insn
, extension
)
406 unsigned long insn
, extension
;
408 store_word (State
.regs
[REG_SP
] + (insn
& 0xffff),
409 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
412 /* mov am, (d32,sp) */
413 void OP_FC900000 (insn
, extension
)
414 unsigned long insn
, extension
;
416 store_word (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
),
417 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
420 /* mov am, (di,an) */
421 void OP_F3C0 (insn
, extension
)
422 unsigned long insn
, extension
;
424 store_word ((State
.regs
[REG_A0
+ REG0 (insn
)]
425 + State
.regs
[REG_D0
+ REG1 (insn
)]),
426 State
.regs
[REG_A0
+ REG0_4 (insn
)]);
429 /* mov am, (abs16) */
430 void OP_FA800000 (insn
, extension
)
431 unsigned long insn
, extension
;
433 store_word ((insn
& 0xffff), State
.regs
[REG_A0
+ REG1_16 (insn
)]);
436 /* mov am, (abs32) */
437 void OP_FC800000 (insn
, extension
)
438 unsigned long insn
, extension
;
440 store_word ((((insn
& 0xffff) << 16) + extension
), State
.regs
[REG_A0
+ REG1_16 (insn
)]);
443 /* mov sp, (d8,an) */
444 void OP_F8F400 (insn
, extension
)
445 unsigned long insn
, extension
;
447 store_word (State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff),
452 void OP_2C0000 (insn
, extension
)
453 unsigned long insn
, extension
;
457 value
= SEXT16 (insn
& 0xffff);
458 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
462 void OP_FCCC0000 (insn
, extension
)
463 unsigned long insn
, extension
;
467 value
= ((insn
& 0xffff) << 16) + extension
;
468 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
472 void OP_240000 (insn
, extension
)
473 unsigned long insn
, extension
;
477 value
= insn
& 0xffff;
478 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
482 void OP_FCDC0000 (insn
, extension
)
483 unsigned long insn
, extension
;
487 value
= ((insn
& 0xffff) << 16) + extension
;
488 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
492 void OP_F040 (insn
, extension
)
493 unsigned long insn
, extension
;
495 State
.regs
[REG_D0
+ REG1 (insn
)]
496 = load_byte (State
.regs
[REG_A0
+ REG0 (insn
)]);
499 /* movbu (d8,am), dn */
500 void OP_F84000 (insn
, extension
)
501 unsigned long insn
, extension
;
503 State
.regs
[REG_D0
+ REG1_8 (insn
)]
504 = load_byte ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
505 + SEXT8 (insn
& 0xff)));
508 /* movbu (d16,am), dn */
509 void OP_FA400000 (insn
, extension
)
510 unsigned long insn
, extension
;
512 State
.regs
[REG_D0
+ REG1_16 (insn
)]
513 = load_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
514 + SEXT16 (insn
& 0xffff)));
517 /* movbu (d32,am), dn */
518 void OP_FC400000 (insn
, extension
)
519 unsigned long insn
, extension
;
521 State
.regs
[REG_D0
+ REG1_16 (insn
)]
522 = load_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
523 + ((insn
& 0xffff) << 16) + extension
));
526 /* movbu (d8,sp), dn */
527 void OP_F8B800 (insn
, extension
)
528 unsigned long insn
, extension
;
530 State
.regs
[REG_D0
+ REG0_8 (insn
)]
531 = load_byte ((State
.regs
[REG_SP
] + (insn
& 0xff)));
534 /* movbu (d16,sp), dn */
535 void OP_FAB80000 (insn
, extension
)
536 unsigned long insn
, extension
;
538 State
.regs
[REG_D0
+ REG0_16 (insn
)]
539 = load_byte ((State
.regs
[REG_SP
] + (insn
& 0xffff)));
542 /* movbu (d32,sp), dn */
543 void OP_FCB80000 (insn
, extension
)
544 unsigned long insn
, extension
;
546 State
.regs
[REG_D0
+ REG0_16 (insn
)]
547 = load_byte (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
));
550 /* movbu (di,am), dn */
551 void OP_F400 (insn
, extension
)
552 unsigned long insn
, extension
;
554 State
.regs
[REG_D0
+ REG0_4 (insn
)]
555 = load_byte ((State
.regs
[REG_A0
+ REG0 (insn
)]
556 + State
.regs
[REG_D0
+ REG1 (insn
)]));
559 /* movbu (abs16), dn */
560 void OP_340000 (insn
, extension
)
561 unsigned long insn
, extension
;
563 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_byte ((insn
& 0xffff));
566 /* movbu (abs32), dn */
567 void OP_FCA80000 (insn
, extension
)
568 unsigned long insn
, extension
;
570 State
.regs
[REG_D0
+ REG0_16 (insn
)]
571 = load_byte ((((insn
& 0xffff) << 16) + extension
));
575 void OP_F050 (insn
, extension
)
576 unsigned long insn
, extension
;
578 store_byte (State
.regs
[REG_A0
+ REG0 (insn
)],
579 State
.regs
[REG_D0
+ REG1 (insn
)]);
582 /* movbu dm, (d8,an) */
583 void OP_F85000 (insn
, extension
)
584 unsigned long insn
, extension
;
586 store_byte ((State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff)),
587 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
590 /* movbu dm, (d16,an) */
591 void OP_FA500000 (insn
, extension
)
592 unsigned long insn
, extension
;
594 store_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)] + SEXT16 (insn
& 0xffff)),
595 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
598 /* movbu dm, (d32,an) */
599 void OP_FC500000 (insn
, extension
)
600 unsigned long insn
, extension
;
602 store_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
603 + ((insn
& 0xffff) << 16) + extension
),
604 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
607 /* movbu dm, (d8,sp) */
608 void OP_F89200 (insn
, extension
)
609 unsigned long insn
, extension
;
611 store_byte (State
.regs
[REG_SP
] + (insn
& 0xff),
612 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
615 /* movbu dm, (d16,sp) */
616 void OP_FA920000 (insn
, extension
)
617 unsigned long insn
, extension
;
619 store_byte (State
.regs
[REG_SP
] + (insn
& 0xffff),
620 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
623 /* movbu dm (d32,sp) */
624 void OP_FC920000 (insn
, extension
)
625 unsigned long insn
, extension
;
627 store_byte (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
),
628 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
631 /* movbu dm, (di,an) */
632 void OP_F440 (insn
, extension
)
633 unsigned long insn
, extension
;
635 store_byte ((State
.regs
[REG_A0
+ REG0 (insn
)]
636 + State
.regs
[REG_D0
+ REG1 (insn
)]),
637 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
640 /* movbu dm, (abs16) */
641 void OP_20000 (insn
, extension
)
642 unsigned long insn
, extension
;
644 store_byte ((insn
& 0xffff), State
.regs
[REG_D0
+ REG1_16 (insn
)]);
647 /* movbu dm, (abs32) */
648 void OP_FC820000 (insn
, extension
)
649 unsigned long insn
, extension
;
651 store_byte ((((insn
& 0xffff) << 16) + extension
), State
.regs
[REG_D0
+ REG1_16 (insn
)]);
655 void OP_F060 (insn
, extension
)
656 unsigned long insn
, extension
;
658 State
.regs
[REG_D0
+ REG1 (insn
)]
659 = load_half (State
.regs
[REG_A0
+ REG0 (insn
)]);
662 /* movhu (d8,am), dn */
663 void OP_F86000 (insn
, extension
)
664 unsigned long insn
, extension
;
666 State
.regs
[REG_D0
+ REG1_8 (insn
)]
667 = load_half ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
668 + SEXT8 (insn
& 0xff)));
671 /* movhu (d16,am), dn */
672 void OP_FA600000 (insn
, extension
)
673 unsigned long insn
, extension
;
675 State
.regs
[REG_D0
+ REG1_16 (insn
)]
676 = load_half ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
677 + SEXT16 (insn
& 0xffff)));
680 /* movhu (d32,am), dn */
681 void OP_FC600000 (insn
, extension
)
682 unsigned long insn
, extension
;
684 State
.regs
[REG_D0
+ REG1_16 (insn
)]
685 = load_half ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
686 + ((insn
& 0xffff) << 16) + extension
));
689 /* movhu (d8,sp) dn */
690 void OP_F8BC00 (insn
, extension
)
691 unsigned long insn
, extension
;
693 State
.regs
[REG_D0
+ REG0_8 (insn
)]
694 = load_half ((State
.regs
[REG_SP
] + (insn
& 0xff)));
697 /* movhu (d16,sp), dn */
698 void OP_FABC0000 (insn
, extension
)
699 unsigned long insn
, extension
;
701 State
.regs
[REG_D0
+ REG0_16 (insn
)]
702 = load_half ((State
.regs
[REG_SP
] + (insn
& 0xffff)));
705 /* movhu (d32,sp), dn */
706 void OP_FCBC0000 (insn
, extension
)
707 unsigned long insn
, extension
;
709 State
.regs
[REG_D0
+ REG0_16 (insn
)]
710 = load_half (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
));
713 /* movhu (di,am), dn */
714 void OP_F480 (insn
, extension
)
715 unsigned long insn
, extension
;
717 State
.regs
[REG_D0
+ REG0_4 (insn
)]
718 = load_half ((State
.regs
[REG_A0
+ REG0 (insn
)]
719 + State
.regs
[REG_D0
+ REG1 (insn
)]));
722 /* movhu (abs16), dn */
723 void OP_380000 (insn
, extension
)
724 unsigned long insn
, extension
;
726 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_half ((insn
& 0xffff));
729 /* movhu (abs32), dn */
730 void OP_FCAC0000 (insn
, extension
)
731 unsigned long insn
, extension
;
733 State
.regs
[REG_D0
+ REG0_16 (insn
)]
734 = load_half ((((insn
& 0xffff) << 16) + extension
));
738 void OP_F070 (insn
, extension
)
739 unsigned long insn
, extension
;
741 store_half (State
.regs
[REG_A0
+ REG0 (insn
)],
742 State
.regs
[REG_D0
+ REG1 (insn
)]);
745 /* movhu dm, (d8,an) */
746 void OP_F87000 (insn
, extension
)
747 unsigned long insn
, extension
;
749 store_half ((State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff)),
750 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
753 /* movhu dm, (d16,an) */
754 void OP_FA700000 (insn
, extension
)
755 unsigned long insn
, extension
;
757 store_half ((State
.regs
[REG_A0
+ REG0_16 (insn
)] + SEXT16 (insn
& 0xffff)),
758 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
761 /* movhu dm, (d32,an) */
762 void OP_FC700000 (insn
, extension
)
763 unsigned long insn
, extension
;
765 store_half ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
766 + ((insn
& 0xffff) << 16) + extension
),
767 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
770 /* movhu dm,(d8,sp) */
771 void OP_F89300 (insn
, extension
)
772 unsigned long insn
, extension
;
774 store_half (State
.regs
[REG_SP
] + (insn
& 0xff),
775 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
778 /* movhu dm,(d16,sp) */
779 void OP_FA930000 (insn
, extension
)
780 unsigned long insn
, extension
;
782 store_half (State
.regs
[REG_SP
] + (insn
& 0xffff),
783 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
786 /* movhu dm,(d32,sp) */
787 void OP_FC930000 (insn
, extension
)
788 unsigned long insn
, extension
;
790 store_half (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
),
791 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
794 /* movhu dm, (di,an) */
795 void OP_F4C0 (insn
, extension
)
796 unsigned long insn
, extension
;
798 store_half ((State
.regs
[REG_A0
+ REG0 (insn
)]
799 + State
.regs
[REG_D0
+ REG1 (insn
)]),
800 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
803 /* movhu dm, (abs16) */
804 void OP_30000 (insn
, extension
)
805 unsigned long insn
, extension
;
807 store_half ((insn
& 0xffff), State
.regs
[REG_D0
+ REG1_16 (insn
)]);
810 /* movhu dm, (abs32) */
811 void OP_FC830000 (insn
, extension
)
812 unsigned long insn
, extension
;
814 store_half ((((insn
& 0xffff) << 16) + extension
), State
.regs
[REG_D0
+ REG1_16 (insn
)]);
818 void OP_F2D0 (insn
, extension
)
819 unsigned long insn
, extension
;
821 if (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000)
822 State
.regs
[REG_MDR
] = -1;
824 State
.regs
[REG_MDR
] = 0;
828 void OP_10 (insn
, extension
)
829 unsigned long insn
, extension
;
831 State
.regs
[REG_D0
+ REG0 (insn
)] = SEXT8 (State
.regs
[REG_D0
+ REG0 (insn
)]);
835 void OP_14 (insn
, extension
)
836 unsigned long insn
, extension
;
838 State
.regs
[REG_D0
+ REG0 (insn
)] &= 0xff;
842 void OP_18 (insn
, extension
)
843 unsigned long insn
, extension
;
845 State
.regs
[REG_D0
+ REG0 (insn
)]
846 = SEXT16 (State
.regs
[REG_D0
+ REG0 (insn
)]);
850 void OP_1C (insn
, extension
)
851 unsigned long insn
, extension
;
853 State
.regs
[REG_D0
+ REG0 (insn
)] &= 0xffff;
856 /* movm (sp), reg_list */
857 void OP_CE00 (insn
, extension
)
858 unsigned long insn
, extension
;
860 unsigned long sp
= State
.regs
[REG_SP
];
868 State
.regs
[REG_LAR
] = load_word (sp
);
870 State
.regs
[REG_LIR
] = load_word (sp
);
872 State
.regs
[REG_MDR
] = load_word (sp
);
874 State
.regs
[REG_A0
+ 1] = load_word (sp
);
876 State
.regs
[REG_A0
] = load_word (sp
);
878 State
.regs
[REG_D0
+ 1] = load_word (sp
);
880 State
.regs
[REG_D0
] = load_word (sp
);
886 State
.regs
[REG_A0
+ 3] = load_word (sp
);
892 State
.regs
[REG_A0
+ 2] = load_word (sp
);
898 State
.regs
[REG_D0
+ 3] = load_word (sp
);
904 State
.regs
[REG_D0
+ 2] = load_word (sp
);
908 /* And make sure to update the stack pointer. */
909 State
.regs
[REG_SP
] = sp
;
912 /* movm reg_list, (sp) */
913 void OP_CF00 (insn
, extension
)
914 unsigned long insn
, extension
;
916 unsigned long sp
= State
.regs
[REG_SP
];
924 store_word (sp
, State
.regs
[REG_D0
+ 2]);
930 store_word (sp
, State
.regs
[REG_D0
+ 3]);
936 store_word (sp
, State
.regs
[REG_A0
+ 2]);
942 store_word (sp
, State
.regs
[REG_A0
+ 3]);
948 store_word (sp
, State
.regs
[REG_D0
]);
950 store_word (sp
, State
.regs
[REG_D0
+ 1]);
952 store_word (sp
, State
.regs
[REG_A0
]);
954 store_word (sp
, State
.regs
[REG_A0
+ 1]);
956 store_word (sp
, State
.regs
[REG_MDR
]);
958 store_word (sp
, State
.regs
[REG_LIR
]);
960 store_word (sp
, State
.regs
[REG_LAR
]);
964 /* And make sure to update the stack pointer. */
965 State
.regs
[REG_SP
] = sp
;
969 void OP_0 (insn
, extension
)
970 unsigned long insn
, extension
;
972 State
.regs
[REG_D0
+ REG1 (insn
)] = 0;
975 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
979 void OP_E0 (insn
, extension
)
980 unsigned long insn
, extension
;
983 unsigned long reg1
, reg2
, value
;
985 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
986 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
988 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
991 n
= (value
& 0x80000000);
992 c
= (value
< reg1
) || (value
< reg2
);
993 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
994 && (reg2
& 0x80000000) != (value
& 0x80000000));
996 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
997 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
998 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1002 void OP_F160 (insn
, extension
)
1003 unsigned long insn
, extension
;
1006 unsigned long reg1
, reg2
, value
;
1008 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1009 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1010 value
= reg1
+ reg2
;
1011 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1014 n
= (value
& 0x80000000);
1015 c
= (value
< reg1
) || (value
< reg2
);
1016 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1017 && (reg2
& 0x80000000) != (value
& 0x80000000));
1019 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1020 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1021 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1025 void OP_F150 (insn
, extension
)
1026 unsigned long insn
, extension
;
1029 unsigned long reg1
, reg2
, value
;
1031 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1032 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1033 value
= reg1
+ reg2
;
1034 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1037 n
= (value
& 0x80000000);
1038 c
= (value
< reg1
) || (value
< reg2
);
1039 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1040 && (reg2
& 0x80000000) != (value
& 0x80000000));
1042 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1043 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1044 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1048 void OP_F170 (insn
, extension
)
1049 unsigned long insn
, extension
;
1052 unsigned long reg1
, reg2
, value
;
1054 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1055 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1056 value
= reg1
+ reg2
;
1057 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1060 n
= (value
& 0x80000000);
1061 c
= (value
< reg1
) || (value
< reg2
);
1062 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1063 && (reg2
& 0x80000000) != (value
& 0x80000000));
1065 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1066 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1067 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1071 void OP_2800 (insn
, extension
)
1072 unsigned long insn
, extension
;
1075 unsigned long reg1
, imm
, value
;
1077 reg1
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1078 imm
= SEXT8 (insn
& 0xff);
1080 State
.regs
[REG_D0
+ REG0_8 (insn
)] = value
;
1083 n
= (value
& 0x80000000);
1084 c
= (value
< reg1
) || (value
< imm
);
1085 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1086 && (reg1
& 0x80000000) != (value
& 0x80000000));
1088 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1089 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1090 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1094 void OP_FAC00000 (insn
, extension
)
1095 unsigned long insn
, extension
;
1098 unsigned long reg1
, imm
, value
;
1100 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1101 imm
= SEXT16 (insn
& 0xffff);
1103 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1106 n
= (value
& 0x80000000);
1107 c
= (value
< reg1
) || (value
< imm
);
1108 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1109 && (reg1
& 0x80000000) != (value
& 0x80000000));
1111 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1112 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1113 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1117 void OP_FCC00000 (insn
, extension
)
1118 unsigned long insn
, extension
;
1121 unsigned long reg1
, imm
, value
;
1123 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1124 imm
= ((insn
& 0xffff) << 16) + extension
;
1126 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1129 n
= (value
& 0x80000000);
1130 c
= (value
< reg1
) || (value
< imm
);
1131 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1132 && (reg1
& 0x80000000) != (value
& 0x80000000));
1134 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1135 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1136 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1140 void OP_2000 (insn
, extension
)
1141 unsigned long insn
, extension
;
1144 unsigned long reg1
, imm
, value
;
1146 reg1
= State
.regs
[REG_A0
+ REG0_8 (insn
)];
1147 imm
= SEXT8 (insn
& 0xff);
1149 State
.regs
[REG_A0
+ REG0_8 (insn
)] = value
;
1152 n
= (value
& 0x80000000);
1153 c
= (value
< reg1
) || (value
< imm
);
1154 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1155 && (reg1
& 0x80000000) != (value
& 0x80000000));
1157 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1158 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1159 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1163 void OP_FAD00000 (insn
, extension
)
1164 unsigned long insn
, extension
;
1167 unsigned long reg1
, imm
, value
;
1169 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1170 imm
= SEXT16 (insn
& 0xffff);
1172 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1175 n
= (value
& 0x80000000);
1176 c
= (value
< reg1
) || (value
< imm
);
1177 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1178 && (reg1
& 0x80000000) != (value
& 0x80000000));
1180 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1181 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1182 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1186 void OP_FCD00000 (insn
, extension
)
1187 unsigned long insn
, extension
;
1190 unsigned long reg1
, imm
, value
;
1192 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1193 imm
= ((insn
& 0xffff) << 16) + extension
;
1195 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1198 n
= (value
& 0x80000000);
1199 c
= (value
< reg1
) || (value
< imm
);
1200 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1201 && (reg1
& 0x80000000) != (value
& 0x80000000));
1203 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1204 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1205 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1209 void OP_F8FE00 (insn
, extension
)
1210 unsigned long insn
, extension
;
1212 unsigned long reg1
, imm
, value
;
1214 reg1
= State
.regs
[REG_SP
];
1215 imm
= SEXT8 (insn
& 0xff);
1217 State
.regs
[REG_SP
] = value
;
1221 void OP_FAFE0000 (insn
, extension
)
1222 unsigned long insn
, extension
;
1224 unsigned long reg1
, imm
, value
;
1226 reg1
= State
.regs
[REG_SP
];
1227 imm
= SEXT16 (insn
& 0xffff);
1229 State
.regs
[REG_SP
] = value
;
1233 void OP_FCFE0000 (insn
, extension
)
1234 unsigned long insn
, extension
;
1236 unsigned long reg1
, imm
, value
;
1238 reg1
= State
.regs
[REG_SP
];
1239 imm
= ((insn
& 0xffff) << 16) + extension
;
1241 State
.regs
[REG_SP
] = value
;
1245 void OP_F140 (insn
, extension
)
1246 unsigned long insn
, extension
;
1249 unsigned long reg1
, reg2
, value
;
1251 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1252 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1253 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1254 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1257 n
= (value
& 0x80000000);
1258 c
= (value
< reg1
) || (value
< reg2
);
1259 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1260 && (reg2
& 0x80000000) != (value
& 0x80000000));
1262 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1263 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1264 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1268 void OP_F100 (insn
, extension
)
1269 unsigned long insn
, extension
;
1272 unsigned long reg1
, reg2
, value
;
1274 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1275 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1276 value
= reg2
- reg1
;
1277 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1280 n
= (value
& 0x80000000);
1282 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1283 && (reg2
& 0x80000000) != (value
& 0x80000000));
1285 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1286 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1287 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1291 void OP_F120 (insn
, extension
)
1292 unsigned long insn
, extension
;
1295 unsigned long reg1
, reg2
, value
;
1297 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1298 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1299 value
= reg2
- reg1
;
1300 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1303 n
= (value
& 0x80000000);
1305 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1306 && (reg2
& 0x80000000) != (value
& 0x80000000));
1308 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1309 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1310 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1314 void OP_F110 (insn
, extension
)
1315 unsigned long insn
, extension
;
1318 unsigned long reg1
, reg2
, value
;
1320 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1321 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1322 value
= reg2
- reg1
;
1323 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1326 n
= (value
& 0x80000000);
1328 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1329 && (reg2
& 0x80000000) != (value
& 0x80000000));
1331 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1332 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1333 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1337 void OP_F130 (insn
, extension
)
1338 unsigned long insn
, extension
;
1341 unsigned long reg1
, reg2
, value
;
1343 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1344 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1345 value
= reg2
- reg1
;
1346 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1349 n
= (value
& 0x80000000);
1351 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1352 && (reg2
& 0x80000000) != (value
& 0x80000000));
1354 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1355 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1356 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1360 void OP_FCC40000 (insn
, extension
)
1361 unsigned long insn
, extension
;
1364 unsigned long reg1
, imm
, value
;
1366 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1367 imm
= ((insn
& 0xffff) << 16) + extension
;
1369 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1372 n
= (value
& 0x80000000);
1374 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1375 && (reg1
& 0x80000000) != (value
& 0x80000000));
1377 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1378 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1379 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1383 void OP_FCD40000 (insn
, extension
)
1384 unsigned long insn
, extension
;
1387 unsigned long reg1
, imm
, value
;
1389 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1390 imm
= ((insn
& 0xffff) << 16) + extension
;
1392 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1395 n
= (value
& 0x80000000);
1397 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1398 && (reg1
& 0x80000000) != (value
& 0x80000000));
1400 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1401 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1402 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1406 void OP_F180 (insn
, extension
)
1407 unsigned long insn
, extension
;
1410 unsigned long reg1
, reg2
, value
;
1412 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1413 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1414 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1415 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1418 n
= (value
& 0x80000000);
1420 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1421 && (reg2
& 0x80000000) != (value
& 0x80000000));
1423 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1424 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1425 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1429 void OP_F240 (insn
, extension
)
1430 unsigned long insn
, extension
;
1432 unsigned long long temp
;
1435 temp
= ((signed long)State
.regs
[REG_D0
+ REG0 (insn
)]
1436 * (signed long)State
.regs
[REG_D0
+ REG1 (insn
)]);
1437 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1438 State
.regs
[REG_MDR
] = (temp
& 0xffffffff00000000LL
) >> 32;;
1439 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1440 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1441 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1442 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1446 void OP_F250 (insn
, extension
)
1447 unsigned long insn
, extension
;
1449 unsigned long long temp
;
1452 temp
= (State
.regs
[REG_D0
+ REG0 (insn
)]
1453 * State
.regs
[REG_D0
+ REG1 (insn
)]);
1454 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1455 State
.regs
[REG_MDR
] = (temp
& 0xffffffff00000000LL
) >> 32;
1456 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1457 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1458 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1459 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1463 void OP_F260 (insn
, extension
)
1464 unsigned long insn
, extension
;
1469 temp
= State
.regs
[REG_MDR
];
1471 temp
|= State
.regs
[REG_D0
+ REG0 (insn
)];
1472 State
.regs
[REG_MDR
] = temp
% (long)State
.regs
[REG_D0
+ REG1 (insn
)];
1473 temp
/= (long)State
.regs
[REG_D0
+ REG1 (insn
)];
1474 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1475 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1476 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1477 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1478 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1482 void OP_F270 (insn
, extension
)
1483 unsigned long insn
, extension
;
1485 unsigned long long temp
;
1488 temp
= State
.regs
[REG_MDR
];
1490 temp
|= State
.regs
[REG_D0
+ REG0 (insn
)];
1491 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ REG1 (insn
)];
1492 temp
/= State
.regs
[REG_D0
+ REG1 (insn
)];
1493 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1494 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1495 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1496 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1497 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1501 void OP_40 (insn
, extension
)
1502 unsigned long insn
, extension
;
1505 unsigned int value
, imm
, reg1
;
1507 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1510 State
.regs
[REG_D0
+ REG1 (insn
)] = value
;
1513 n
= (value
& 0x80000000);
1515 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1516 && (reg1
& 0x80000000) != (value
& 0x80000000));
1518 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1519 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1520 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1524 void OP_41 (insn
, extension
)
1525 unsigned long insn
, extension
;
1527 State
.regs
[REG_A0
+ REG1 (insn
)] += 1;
1531 void OP_50 (insn
, extension
)
1532 unsigned long insn
, extension
;
1534 State
.regs
[REG_A0
+ REG0 (insn
)] += 4;
1538 void OP_A000 (insn
, extension
)
1539 unsigned long insn
, extension
;
1542 unsigned long reg1
, imm
, value
;
1544 reg1
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1545 imm
= SEXT8 (insn
& 0xff);
1549 n
= (value
& 0x80000000);
1551 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1552 && (reg1
& 0x80000000) != (value
& 0x80000000));
1554 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1555 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1556 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1560 void OP_A0 (insn
, extension
)
1561 unsigned long insn
, extension
;
1564 unsigned long reg1
, reg2
, value
;
1566 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1567 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1568 value
= reg2
- reg1
;
1571 n
= (value
& 0x80000000);
1573 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1574 && (reg2
& 0x80000000) != (value
& 0x80000000));
1576 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1577 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1578 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1582 void OP_F1A0 (insn
, extension
)
1583 unsigned long insn
, extension
;
1586 unsigned long reg1
, reg2
, value
;
1588 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1589 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1590 value
= reg2
- reg1
;
1593 n
= (value
& 0x80000000);
1595 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1596 && (reg2
& 0x80000000) != (value
& 0x80000000));
1598 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1599 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1600 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1604 void OP_F190 (insn
, extension
)
1605 unsigned long insn
, extension
;
1608 unsigned long reg1
, reg2
, value
;
1610 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1611 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1612 value
= reg2
- reg1
;
1615 n
= (value
& 0x80000000);
1617 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1618 && (reg2
& 0x80000000) != (value
& 0x80000000));
1620 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1621 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1622 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1626 void OP_B000 (insn
, extension
)
1627 unsigned long insn
, extension
;
1630 unsigned long reg1
, imm
, value
;
1632 reg1
= State
.regs
[REG_A0
+ REG0_8 (insn
)];
1637 n
= (value
& 0x80000000);
1639 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1640 && (reg1
& 0x80000000) != (value
& 0x80000000));
1642 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1643 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1644 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1648 void OP_B0 (insn
, extension
)
1649 unsigned long insn
, extension
;
1652 unsigned long reg1
, reg2
, value
;
1654 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1655 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1656 value
= reg2
- reg1
;
1659 n
= (value
& 0x80000000);
1661 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1662 && (reg2
& 0x80000000) != (value
& 0x80000000));
1664 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1665 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1666 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1670 void OP_FAC80000 (insn
, extension
)
1671 unsigned long insn
, extension
;
1674 unsigned long reg1
, imm
, value
;
1676 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1677 imm
= SEXT16 (insn
& 0xffff);
1681 n
= (value
& 0x80000000);
1683 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1684 && (reg1
& 0x80000000) != (value
& 0x80000000));
1686 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1687 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1688 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1692 void OP_FCC80000 (insn
, extension
)
1693 unsigned long insn
, extension
;
1696 unsigned long reg1
, imm
, value
;
1698 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1699 imm
= ((insn
& 0xffff) << 16) + extension
;
1703 n
= (value
& 0x80000000);
1705 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1706 && (reg1
& 0x80000000) != (value
& 0x80000000));
1708 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1709 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1710 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1714 void OP_FAD80000 (insn
, extension
)
1715 unsigned long insn
, extension
;
1718 unsigned long reg1
, imm
, value
;
1720 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1721 imm
= insn
& 0xffff;
1725 n
= (value
& 0x80000000);
1727 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1728 && (reg1
& 0x80000000) != (value
& 0x80000000));
1730 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1731 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1732 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1736 void OP_FCD80000 (insn
, extension
)
1737 unsigned long insn
, extension
;
1740 unsigned long reg1
, imm
, value
;
1742 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1743 imm
= ((insn
& 0xffff) << 16) + extension
;
1747 n
= (value
& 0x80000000);
1749 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1750 && (reg1
& 0x80000000) != (value
& 0x80000000));
1752 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1753 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1754 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1758 void OP_F200 (insn
, extension
)
1759 unsigned long insn
, extension
;
1763 State
.regs
[REG_D0
+ REG0 (insn
)] &= State
.regs
[REG_D0
+ REG1 (insn
)];
1764 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1765 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1766 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1767 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1771 void OP_F8E000 (insn
, extension
)
1772 unsigned long insn
, extension
;
1776 State
.regs
[REG_D0
+ REG0_8 (insn
)] &= (insn
& 0xff);
1777 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
1778 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
1779 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1780 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1784 void OP_FAE00000 (insn
, extension
)
1785 unsigned long insn
, extension
;
1789 State
.regs
[REG_D0
+ REG0_16 (insn
)] &= (insn
& 0xffff);
1790 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1791 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1792 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1793 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1797 void OP_FCE00000 (insn
, extension
)
1798 unsigned long insn
, extension
;
1802 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1803 &= ((insn
& 0xffff) << 16) + extension
;
1804 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1805 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1806 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1807 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1810 /* and imm16, psw */
1811 void OP_FAFC0000 (insn
, extension
)
1812 unsigned long insn
, extension
;
1814 PSW
&= (insn
& 0xffff);
1818 void OP_F210 (insn
, extension
)
1819 unsigned long insn
, extension
;
1823 State
.regs
[REG_D0
+ REG0 (insn
)] |= State
.regs
[REG_D0
+ REG1 (insn
)];
1824 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1825 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1826 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1827 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1831 void OP_F8E400 (insn
, extension
)
1832 unsigned long insn
, extension
;
1836 State
.regs
[REG_D0
+ REG0_8 (insn
)] |= insn
& 0xff;
1837 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
1838 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
1839 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1840 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1844 void OP_FAE40000 (insn
, extension
)
1845 unsigned long insn
, extension
;
1849 State
.regs
[REG_D0
+ REG0_16 (insn
)] |= insn
& 0xffff;
1850 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1851 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1852 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1853 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1857 void OP_FCE40000 (insn
, extension
)
1858 unsigned long insn
, extension
;
1862 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1863 |= ((insn
& 0xffff) << 16) + extension
;
1864 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1865 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1866 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1867 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1871 void OP_FAFD0000 (insn
, extension
)
1872 unsigned long insn
, extension
;
1874 PSW
|= (insn
& 0xffff);
1878 void OP_F220 (insn
, extension
)
1879 unsigned long insn
, extension
;
1883 State
.regs
[REG_D0
+ REG0 (insn
)] ^= State
.regs
[REG_D0
+ REG1 (insn
)];
1884 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1885 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1886 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1887 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1891 void OP_FAE80000 (insn
, extension
)
1892 unsigned long insn
, extension
;
1896 State
.regs
[REG_D0
+ REG0_16 (insn
)] ^= insn
& 0xffff;
1897 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1898 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1899 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1900 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1904 void OP_FCE80000 (insn
, extension
)
1905 unsigned long insn
, extension
;
1909 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1910 ^= ((insn
& 0xffff) << 16) + extension
;
1911 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1912 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1913 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1914 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1918 void OP_F230 (insn
, extension
)
1919 unsigned long insn
, extension
;
1923 State
.regs
[REG_D0
+ REG0 (insn
)] = ~State
.regs
[REG_D0
+ REG0 (insn
)];
1924 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1925 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1926 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1927 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1931 void OP_F8EC00 (insn
, extension
)
1932 unsigned long insn
, extension
;
1937 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1938 temp
&= (insn
& 0xff);
1939 n
= (temp
& 0x80000000) != 0;
1941 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1942 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1945 /* btst imm16, dn */
1946 void OP_FAEC0000 (insn
, extension
)
1947 unsigned long insn
, extension
;
1952 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1953 temp
&= (insn
& 0xffff);
1954 n
= (temp
& 0x80000000) != 0;
1956 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1957 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1960 /* btst imm32, dn */
1961 void OP_FCEC0000 (insn
, extension
)
1962 unsigned long insn
, extension
;
1967 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1968 temp
&= ((insn
& 0xffff) << 16) + extension
;
1969 n
= (temp
& 0x80000000) != 0;
1971 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1972 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1975 /* btst imm8,(abs32) */
1976 void OP_FE020000 (insn
, extension
)
1977 unsigned long insn
, extension
;
1982 temp
= load_byte (((insn
& 0xffff) << 16) | (extension
>> 8));
1983 temp
&= (extension
& 0xff);
1984 n
= (temp
& 0x80000000) != 0;
1986 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1987 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1990 /* btst imm8,(d8,an) */
1991 void OP_FAF80000 (insn
, extension
)
1992 unsigned long insn
, extension
;
1997 temp
= load_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
1998 + SEXT8 ((insn
& 0xff00) >> 8)));
1999 temp
&= (insn
& 0xff);
2000 n
= (temp
& 0x80000000) != 0;
2002 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2003 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2007 void OP_F080 (insn
, extension
)
2008 unsigned long insn
, extension
;
2013 temp
= load_byte (State
.regs
[REG_A0
+ REG0 (insn
)]);
2014 z
= (temp
& State
.regs
[REG_D0
+ REG1 (insn
)]) == 0;
2015 temp
|= State
.regs
[REG_D0
+ REG1 (insn
)];
2016 store_byte (State
.regs
[REG_A0
+ REG0 (insn
)], temp
);
2017 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2018 PSW
|= (z
? PSW_Z
: 0);
2021 /* bset imm8, (abs32) */
2022 void OP_FE000000 (insn
, extension
)
2023 unsigned long insn
, extension
;
2028 temp
= load_byte (((insn
& 0xffff) << 16 | (extension
>> 8)));
2029 z
= (temp
& (extension
& 0xff)) == 0;
2030 temp
|= (extension
& 0xff);
2031 store_byte ((((insn
& 0xffff) << 16) | (extension
>> 8)), temp
);
2032 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2033 PSW
|= (z
? PSW_Z
: 0);
2036 /* bset imm8,(d8,an) */
2037 void OP_FAF00000 (insn
, extension
)
2038 unsigned long insn
, extension
;
2043 temp
= load_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2044 + SEXT8 ((insn
& 0xff00) >> 8)));
2045 z
= (temp
& (insn
& 0xff)) == 0;
2046 temp
|= (insn
& 0xff);
2047 store_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2048 + SEXT8 ((insn
& 0xff00) >> 8)), temp
);
2049 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2050 PSW
|= (z
? PSW_Z
: 0);
2054 void OP_F090 (insn
, extension
)
2055 unsigned long insn
, extension
;
2060 temp
= load_byte (State
.regs
[REG_A0
+ REG0 (insn
)]);
2061 z
= (temp
& State
.regs
[REG_D0
+ REG1 (insn
)]) == 0;
2062 temp
= temp
& ~State
.regs
[REG_D0
+ REG1 (insn
)];
2063 store_byte (State
.regs
[REG_A0
+ REG0 (insn
)], temp
);
2064 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2065 PSW
|= (z
? PSW_Z
: 0);
2068 /* bclr imm8, (abs32) */
2069 void OP_FE010000 (insn
, extension
)
2070 unsigned long insn
, extension
;
2075 temp
= load_byte (((insn
& 0xffff) << 16) | (extension
>> 8));
2076 z
= (temp
& (extension
& 0xff)) == 0;
2077 temp
= temp
& ~(extension
& 0xff);
2078 store_byte (((insn
& 0xffff) << 16) | (extension
>> 8), temp
);
2079 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2080 PSW
|= (z
? PSW_Z
: 0);
2083 /* bclr imm8,(d8,an) */
2084 void OP_FAF40000 (insn
, extension
)
2085 unsigned long insn
, extension
;
2090 temp
= load_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2091 + SEXT8 ((insn
& 0xff00) >> 8)));
2092 z
= (temp
& (insn
& 0xff)) == 0;
2093 temp
= temp
& ~(insn
& 0xff);
2094 store_byte ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2095 + SEXT8 ((insn
& 0xff00) >> 8)), temp
);
2096 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2097 PSW
|= (z
? PSW_Z
: 0);
2101 void OP_F2B0 (insn
, extension
)
2102 unsigned long insn
, extension
;
2107 temp
= State
.regs
[REG_D0
+ REG0 (insn
)];
2109 temp
>>= State
.regs
[REG_D0
+ REG1 (insn
)];
2110 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
;
2111 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2112 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2113 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2114 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2118 void OP_F8C800 (insn
, extension
)
2119 unsigned long insn
, extension
;
2124 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
2126 temp
>>= (insn
& 0xff);
2127 State
.regs
[REG_D0
+ REG0_8 (insn
)] = temp
;
2128 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2129 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2130 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2131 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2135 void OP_F2A0 (insn
, extension
)
2136 unsigned long insn
, extension
;
2140 c
= State
.regs
[REG_D0
+ REG0 (insn
)] & 1;
2141 State
.regs
[REG_D0
+ REG0 (insn
)]
2142 >>= State
.regs
[REG_D0
+ REG1 (insn
)];
2143 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2144 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2145 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2146 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2150 void OP_F8C400 (insn
, extension
)
2151 unsigned long insn
, extension
;
2155 c
= State
.regs
[REG_D0
+ REG0_8 (insn
)] & 1;
2156 State
.regs
[REG_D0
+ REG0_8 (insn
)] >>= (insn
& 0xff);
2157 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2158 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2159 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2160 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2164 void OP_F290 (insn
, extension
)
2165 unsigned long insn
, extension
;
2169 State
.regs
[REG_D0
+ REG0 (insn
)]
2170 <<= State
.regs
[REG_D0
+ REG1 (insn
)];
2171 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2172 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2173 PSW
&= ~(PSW_Z
| PSW_N
);
2174 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2178 void OP_F8C000 (insn
, extension
)
2179 unsigned long insn
, extension
;
2183 State
.regs
[REG_D0
+ REG0_8 (insn
)] <<= (insn
& 0xff);
2184 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2185 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2186 PSW
&= ~(PSW_Z
| PSW_N
);
2187 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2191 void OP_54 (insn
, extension
)
2192 unsigned long insn
, extension
;
2196 State
.regs
[REG_D0
+ REG0 (insn
)] <<= 2;
2197 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2198 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2199 PSW
&= ~(PSW_Z
| PSW_N
);
2200 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2204 void OP_F284 (insn
, extension
)
2205 unsigned long insn
, extension
;
2207 unsigned long value
;
2210 value
= State
.regs
[REG_D0
+ REG0 (insn
)];
2214 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
2215 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
2217 n
= (value
& 0x80000000) != 0;
2218 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2219 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2223 void OP_F280 (insn
, extension
)
2224 unsigned long insn
, extension
;
2226 unsigned long value
;
2229 value
= State
.regs
[REG_D0
+ REG0 (insn
)];
2230 c
= (value
& 0x80000000) ? 1 : 0;
2233 value
|= ((PSW
& PSW_C
) != 0);
2234 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
2236 n
= (value
& 0x80000000) != 0;
2237 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2238 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2242 void OP_C800 (insn
, extension
)
2243 unsigned long insn
, extension
;
2245 /* The dispatching code will add 2 after we return, so
2246 we subtract two here to make things right. */
2248 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2252 void OP_C900 (insn
, extension
)
2253 unsigned long insn
, extension
;
2255 /* The dispatching code will add 2 after we return, so
2256 we subtract two here to make things right. */
2258 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2262 void OP_C100 (insn
, extension
)
2263 unsigned long insn
, extension
;
2265 /* The dispatching code will add 2 after we return, so
2266 we subtract two here to make things right. */
2268 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))))
2269 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2273 void OP_C200 (insn
, extension
)
2274 unsigned long insn
, extension
;
2276 /* The dispatching code will add 2 after we return, so
2277 we subtract two here to make things right. */
2278 if (!(((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2279 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2283 void OP_C300 (insn
, extension
)
2284 unsigned long insn
, extension
;
2286 /* The dispatching code will add 2 after we return, so
2287 we subtract two here to make things right. */
2289 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2290 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2294 void OP_C000 (insn
, extension
)
2295 unsigned long insn
, extension
;
2297 /* The dispatching code will add 2 after we return, so
2298 we subtract two here to make things right. */
2299 if (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))
2300 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2304 void OP_C500 (insn
, extension
)
2305 unsigned long insn
, extension
;
2307 /* The dispatching code will add 2 after we return, so
2308 we subtract two here to make things right. */
2309 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2310 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2314 void OP_C600 (insn
, extension
)
2315 unsigned long insn
, extension
;
2317 /* The dispatching code will add 2 after we return, so
2318 we subtract two here to make things right. */
2320 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2324 void OP_C700 (insn
, extension
)
2325 unsigned long insn
, extension
;
2327 /* The dispatching code will add 2 after we return, so
2328 we subtract two here to make things right. */
2329 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2330 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2334 void OP_C400 (insn
, extension
)
2335 unsigned long insn
, extension
;
2337 /* The dispatching code will add 2 after we return, so
2338 we subtract two here to make things right. */
2340 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2344 void OP_F8E800 (insn
, extension
)
2345 unsigned long insn
, extension
;
2347 /* The dispatching code will add 3 after we return, so
2348 we subtract two here to make things right. */
2350 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2354 void OP_F8E900 (insn
, extension
)
2355 unsigned long insn
, extension
;
2357 /* The dispatching code will add 3 after we return, so
2358 we subtract two here to make things right. */
2360 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2364 void OP_F8EA00 (insn
, extension
)
2365 unsigned long insn
, extension
;
2367 /* The dispatching code will add 3 after we return, so
2368 we subtract two here to make things right. */
2370 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2374 void OP_F8EB00 (insn
, extension
)
2375 unsigned long insn
, extension
;
2377 /* The dispatching code will add 3 after we return, so
2378 we subtract two here to make things right. */
2380 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2384 void OP_CA00 (insn
, extension
)
2385 unsigned long insn
, extension
;
2387 /* The dispatching code will add 2 after we return, so
2388 we subtract two here to make things right. */
2389 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2393 void OP_D8 (insn
, extension
)
2394 unsigned long insn
, extension
;
2396 /* The dispatching code will add 1 after we return, so
2397 we subtract one here to make things right. */
2399 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2403 void OP_D9 (insn
, extension
)
2404 unsigned long insn
, extension
;
2406 /* The dispatching code will add 1 after we return, so
2407 we subtract one here to make things right. */
2409 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2413 void OP_D1 (insn
, extension
)
2414 unsigned long insn
, extension
;
2416 /* The dispatching code will add 1 after we return, so
2417 we subtract one here to make things right. */
2419 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))))
2420 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2424 void OP_D2 (insn
, extension
)
2425 unsigned long insn
, extension
;
2427 /* The dispatching code will add 1 after we return, so
2428 we subtract one here to make things right. */
2429 if (!(((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2430 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2434 void OP_D3 (insn
, extension
)
2435 unsigned long insn
, extension
;
2437 /* The dispatching code will add 1 after we return, so
2438 we subtract one here to make things right. */
2440 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2441 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2445 void OP_D0 (insn
, extension
)
2446 unsigned long insn
, extension
;
2448 /* The dispatching code will add 1 after we return, so
2449 we subtract one here to make things right. */
2450 if (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))
2451 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2455 void OP_D5 (insn
, extension
)
2456 unsigned long insn
, extension
;
2458 /* The dispatching code will add 1 after we return, so
2459 we subtract one here to make things right. */
2460 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2461 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2465 void OP_D6 (insn
, extension
)
2466 unsigned long insn
, extension
;
2468 /* The dispatching code will add 1 after we return, so
2469 we subtract one here to make things right. */
2471 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2475 void OP_D7 (insn
, extension
)
2476 unsigned long insn
, extension
;
2478 /* The dispatching code will add 1 after we return, so
2479 we subtract one here to make things right. */
2480 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2481 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2485 void OP_D4 (insn
, extension
)
2486 unsigned long insn
, extension
;
2488 /* The dispatching code will add 1 after we return, so
2489 we subtract one here to make things right. */
2491 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2495 void OP_DA (insn
, extension
)
2496 unsigned long insn
, extension
;
2498 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2502 void OP_DB (insn
, extension
)
2503 unsigned long insn
, extension
;
2505 State
.regs
[REG_LIR
] = load_mem_big (State
.regs
[REG_PC
] + 1, 4);
2506 State
.regs
[REG_LAR
] = State
.regs
[REG_PC
] + 5;
2510 void OP_F0F4 (insn
, extension
)
2511 unsigned long insn
, extension
;
2513 State
.regs
[REG_PC
] = State
.regs
[REG_A0
+ REG0 (insn
)] - 2;
2517 void OP_CC0000 (insn
, extension
)
2518 unsigned long insn
, extension
;
2520 State
.regs
[REG_PC
] += SEXT16 (insn
& 0xffff) - 3;
2524 void OP_DC000000 (insn
, extension
)
2525 unsigned long insn
, extension
;
2527 State
.regs
[REG_PC
] += (((insn
& 0xffffff) << 8) + extension
) - 5;
2530 /* call label:16,reg_list,imm8 */
2531 void OP_CD000000 (insn
, extension
)
2532 unsigned long insn
, extension
;
2534 unsigned int next_pc
, sp
;
2537 sp
= State
.regs
[REG_SP
];
2538 next_pc
= State
.regs
[REG_PC
] + 5;
2539 State
.mem
[sp
] = next_pc
& 0xff;
2540 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2541 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2542 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2549 store_word (sp
, State
.regs
[REG_D0
+ 2]);
2555 store_word (sp
, State
.regs
[REG_D0
+ 3]);
2561 store_word (sp
, State
.regs
[REG_A0
+ 2]);
2567 store_word (sp
, State
.regs
[REG_A0
+ 3]);
2573 store_word (sp
, State
.regs
[REG_D0
]);
2575 store_word (sp
, State
.regs
[REG_D0
+ 1]);
2577 store_word (sp
, State
.regs
[REG_A0
]);
2579 store_word (sp
, State
.regs
[REG_A0
+ 1]);
2581 store_word (sp
, State
.regs
[REG_MDR
]);
2583 store_word (sp
, State
.regs
[REG_LIR
]);
2585 store_word (sp
, State
.regs
[REG_LAR
]);
2589 /* Update the stack pointer. */
2590 State
.regs
[REG_SP
] = sp
- extension
;
2591 State
.regs
[REG_MDR
] = next_pc
;
2592 State
.regs
[REG_PC
] += SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2595 /* call label:32,reg_list,imm8*/
2596 void OP_DD000000 (insn
, extension
)
2597 unsigned long insn
, extension
;
2599 unsigned int next_pc
, sp
, adjust
;
2602 sp
= State
.regs
[REG_SP
];
2603 next_pc
= State
.regs
[REG_PC
] + 7;
2604 State
.mem
[sp
] = next_pc
& 0xff;
2605 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2606 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2607 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2609 mask
= (extension
& 0xff00) >> 8;
2614 store_word (sp
, State
.regs
[REG_D0
+ 2]);
2620 store_word (sp
, State
.regs
[REG_D0
+ 3]);
2626 store_word (sp
, State
.regs
[REG_A0
+ 2]);
2632 store_word (sp
, State
.regs
[REG_A0
+ 3]);
2638 store_word (sp
, State
.regs
[REG_D0
]);
2640 store_word (sp
, State
.regs
[REG_D0
+ 1]);
2642 store_word (sp
, State
.regs
[REG_A0
]);
2644 store_word (sp
, State
.regs
[REG_A0
+ 1]);
2646 store_word (sp
, State
.regs
[REG_MDR
]);
2648 store_word (sp
, State
.regs
[REG_LIR
]);
2650 store_word (sp
, State
.regs
[REG_LAR
]);
2654 /* Update the stack pointer. */
2655 State
.regs
[REG_SP
] = sp
- (extension
& 0xff);
2656 State
.regs
[REG_MDR
] = next_pc
;
2657 State
.regs
[REG_PC
] += (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2661 void OP_F0F0 (insn
, extension
)
2662 unsigned long insn
, extension
;
2664 unsigned int next_pc
, sp
;
2666 sp
= State
.regs
[REG_SP
];
2667 next_pc
= State
.regs
[REG_PC
] + 2;
2668 State
.mem
[sp
] = next_pc
& 0xff;
2669 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2670 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2671 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2672 State
.regs
[REG_MDR
] = next_pc
;
2673 State
.regs
[REG_PC
] = State
.regs
[REG_A0
+ REG0 (insn
)] - 2;
2676 /* calls label:16 */
2677 void OP_FAFF0000 (insn
, extension
)
2678 unsigned long insn
, extension
;
2680 unsigned int next_pc
, sp
;
2682 sp
= State
.regs
[REG_SP
];
2683 next_pc
= State
.regs
[REG_PC
] + 4;
2684 State
.mem
[sp
] = next_pc
& 0xff;
2685 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2686 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2687 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2688 State
.regs
[REG_MDR
] = next_pc
;
2689 State
.regs
[REG_PC
] += SEXT16 (insn
& 0xffff) - 4;
2692 /* calls label:32 */
2693 void OP_FCFF0000 (insn
, extension
)
2694 unsigned long insn
, extension
;
2696 unsigned int next_pc
, sp
;
2698 sp
= State
.regs
[REG_SP
];
2699 next_pc
= State
.regs
[REG_PC
] + 6;
2700 State
.mem
[sp
] = next_pc
& 0xff;
2701 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2702 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2703 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2704 State
.regs
[REG_MDR
] = next_pc
;
2705 State
.regs
[REG_PC
] += (((insn
& 0xffff) << 16) + extension
) - 6;
2708 /* ret reg_list, imm8 */
2709 void OP_DF0000 (insn
, extension
)
2710 unsigned long insn
, extension
;
2712 unsigned int sp
, offset
;
2715 State
.regs
[REG_SP
] += insn
& 0xff;
2716 sp
= State
.regs
[REG_SP
];
2719 mask
= (insn
& 0xff00) >> 8;
2723 State
.regs
[REG_D0
+ 2] = load_word (sp
+ offset
);
2729 State
.regs
[REG_D0
+ 3] = load_word (sp
+ offset
);
2735 State
.regs
[REG_A0
+ 2] = load_word (sp
+ offset
);
2741 State
.regs
[REG_A0
+ 3] = load_word (sp
+ offset
);
2747 State
.regs
[REG_D0
] = load_word (sp
+ offset
);
2749 State
.regs
[REG_D0
+ 1] = load_word (sp
+ offset
);
2751 State
.regs
[REG_A0
] = load_word (sp
+ offset
);
2753 State
.regs
[REG_A0
+ 1] = load_word (sp
+ offset
);
2755 State
.regs
[REG_MDR
] = load_word (sp
+ offset
);
2757 State
.regs
[REG_LIR
] = load_word (sp
+ offset
);
2759 State
.regs
[REG_LAR
] = load_word (sp
+ offset
);
2763 /* Restore the PC value. */
2764 State
.regs
[REG_PC
] = (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2765 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2766 State
.regs
[REG_PC
] -= 3;
2769 /* retf reg_list,imm8 */
2770 void OP_DE0000 (insn
, extension
)
2771 unsigned long insn
, extension
;
2773 unsigned int sp
, offset
;
2776 State
.regs
[REG_SP
] += (insn
& 0xff);
2777 sp
= State
.regs
[REG_SP
];
2778 State
.regs
[REG_PC
] = State
.regs
[REG_MDR
] - 3;
2781 mask
= (insn
& 0xff00) >> 8;
2785 State
.regs
[REG_D0
+ 2] = load_word (sp
+ offset
);
2791 State
.regs
[REG_D0
+ 3] = load_word (sp
+ offset
);
2797 State
.regs
[REG_A0
+ 2] = load_word (sp
+ offset
);
2803 State
.regs
[REG_A0
+ 3] = load_word (sp
+ offset
);
2809 State
.regs
[REG_D0
] = load_word (sp
+ offset
);
2811 State
.regs
[REG_D0
+ 1] = load_word (sp
+ offset
);
2813 State
.regs
[REG_A0
] = load_word (sp
+ offset
);
2815 State
.regs
[REG_A0
+ 1] = load_word (sp
+ offset
);
2817 State
.regs
[REG_MDR
] = load_word (sp
+ offset
);
2819 State
.regs
[REG_LIR
] = load_word (sp
+ offset
);
2821 State
.regs
[REG_LAR
] = load_word (sp
+ offset
);
2827 void OP_F0FC (insn
, extension
)
2828 unsigned long insn
, extension
;
2832 sp
= State
.regs
[REG_SP
];
2833 State
.regs
[REG_PC
] = (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2834 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2835 State
.regs
[REG_PC
] -= 2;
2839 void OP_F0FD (insn
, extension
)
2840 unsigned long insn
, extension
;
2842 unsigned int sp
, next_pc
;
2844 PSW
= State
.mem
[sp
] | (State
.mem
[sp
+ 1] << 8);
2845 State
.regs
[REG_PC
] = (State
.mem
[sp
+4] | (State
.mem
[sp
+5] << 8)
2846 | (State
.mem
[sp
+6] << 16) | (State
.mem
[sp
+7] << 24));
2847 State
.regs
[REG_SP
] += 8;
2851 void OP_F0FE (insn
, extension
)
2852 unsigned long insn
, extension
;
2854 unsigned int sp
, next_pc
;
2856 sp
= State
.regs
[REG_SP
];
2857 next_pc
= State
.regs
[REG_PC
] + 2;
2858 State
.mem
[sp
] = next_pc
& 0xff;
2859 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2860 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2861 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2862 State
.regs
[REG_PC
] = 0x40000010 - 2;
2866 void OP_F020 (insn
, extension
)
2867 unsigned long insn
, extension
;
2869 /* We use this for simulated system calls; we may need to change
2870 it to a reserved instruction if we conflict with uses at
2872 int save_errno
= errno
;
2875 /* Registers passed to trap 0 */
2877 /* Function number. */
2878 #define FUNC (State.regs[0])
2881 #define PARM1 (State.regs[1])
2882 #define PARM2 (load_word (State.regs[REG_SP] + 12))
2883 #define PARM3 (load_word (State.regs[REG_SP] + 16))
2885 /* Registers set by trap 0 */
2887 #define RETVAL State.regs[0] /* return value */
2888 #define RETERR State.regs[1] /* return error code */
2890 /* Turn a pointer in a register into a pointer into real memory. */
2892 #define MEMPTR(x) (State.mem + x)
2896 #if !defined(__GO32__) && !defined(_WIN32)
2901 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2902 (char **)MEMPTR (PARM3
));
2906 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2912 RETVAL
= mn10300_callback
->read (mn10300_callback
, PARM1
,
2913 MEMPTR (PARM2
), PARM3
);
2916 RETVAL
= (int)mn10300_callback
->write (mn10300_callback
, PARM1
,
2917 MEMPTR (PARM2
), PARM3
);
2920 RETVAL
= mn10300_callback
->lseek (mn10300_callback
, PARM1
, PARM2
, PARM3
);
2923 RETVAL
= mn10300_callback
->close (mn10300_callback
, PARM1
);
2926 RETVAL
= mn10300_callback
->open (mn10300_callback
, MEMPTR (PARM1
), PARM2
);
2929 /* EXIT - caller can look in PARM1 to work out the
2931 if (PARM1
== 0xdead)
2932 State
.exception
= SIGABRT
;
2934 State
.exception
= SIGQUIT
;
2938 case SYS_stat
: /* added at hmsi */
2939 /* stat system call */
2941 struct stat host_stat
;
2944 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2948 /* Just wild-assed guesses. */
2949 store_half (buf
, host_stat
.st_dev
);
2950 store_half (buf
+ 2, host_stat
.st_ino
);
2951 store_word (buf
+ 4, host_stat
.st_mode
);
2952 store_half (buf
+ 8, host_stat
.st_nlink
);
2953 store_half (buf
+ 10, host_stat
.st_uid
);
2954 store_half (buf
+ 12, host_stat
.st_gid
);
2955 store_half (buf
+ 14, host_stat
.st_rdev
);
2956 store_word (buf
+ 16, host_stat
.st_size
);
2957 store_word (buf
+ 20, host_stat
.st_atime
);
2958 store_word (buf
+ 28, host_stat
.st_mtime
);
2959 store_word (buf
+ 36, host_stat
.st_ctime
);
2964 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2967 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2971 RETVAL
= time ((void*) MEMPTR (PARM1
));
2978 RETVAL
= times (&tms
);
2979 store_word (PARM1
, tms
.tms_utime
);
2980 store_word (PARM1
+ 4, tms
.tms_stime
);
2981 store_word (PARM1
+ 8, tms
.tms_cutime
);
2982 store_word (PARM1
+ 12, tms
.tms_cstime
);
2986 case SYS_gettimeofday
:
2990 RETVAL
= gettimeofday (&t
, &tz
);
2991 store_word (PARM1
, t
.tv_sec
);
2992 store_word (PARM1
+ 4, t
.tv_usec
);
2993 store_word (PARM2
, tz
.tz_minuteswest
);
2994 store_word (PARM2
+ 4, tz
.tz_dsttime
);
2999 /* Cast the second argument to void *, to avoid type mismatch
3000 if a prototype is present. */
3001 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
3012 void OP_F0FF (insn
, extension
)
3013 unsigned long insn
, extension
;
3019 void OP_CB (insn
, extension
)
3020 unsigned long insn
, extension
;
3025 void OP_F500 (insn
, extension
)
3026 unsigned long insn
, extension
;
3028 State
.regs
[REG_MDRQ
] = State
.regs
[REG_D0
+ REG0 (insn
)];
3032 void OP_F6F0 (insn
, extension
)
3033 unsigned long insn
, extension
;
3036 z
= (State
.regs
[REG_MDRQ
] == 0);
3037 n
= ((State
.regs
[REG_MDRQ
] & 0x80000000) != 0);
3038 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_MDRQ
];
3040 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3041 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
3045 void OP_F600 (insn
, extension
)
3046 unsigned long insn
, extension
;
3048 unsigned long long temp
;
3051 temp
= ((signed long)State
.regs
[REG_D0
+ REG0 (insn
)]
3052 * (signed long)State
.regs
[REG_D0
+ REG1 (insn
)]);
3053 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
3054 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3055 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
3056 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
3057 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3058 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3062 void OP_F90000 (insn
, extension
)
3063 unsigned long insn
, extension
;
3065 unsigned long long temp
;
3068 temp
= ((signed long)State
.regs
[REG_D0
+ REG0_8 (insn
)]
3069 * (signed long)SEXT8 (insn
& 0xff));
3070 State
.regs
[REG_D0
+ REG0_8 (insn
)] = temp
& 0xffffffff;
3071 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3072 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
3073 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
3074 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3075 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3079 void OP_FB000000 (insn
, extension
)
3080 unsigned long insn
, extension
;
3082 unsigned long long temp
;
3085 temp
= ((signed long)State
.regs
[REG_D0
+ REG0_16 (insn
)]
3086 * (signed long)SEXT16 (insn
& 0xffff));
3087 State
.regs
[REG_D0
+ REG0_16 (insn
)] = temp
& 0xffffffff;
3088 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3089 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
3090 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
3091 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3092 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3096 void OP_FD000000 (insn
, extension
)
3097 unsigned long insn
, extension
;
3099 unsigned long long temp
;
3102 temp
= ((signed long)State
.regs
[REG_D0
+ REG0_16 (insn
)]
3103 * (signed long)(((insn
& 0xffff) << 16) + extension
));
3104 State
.regs
[REG_D0
+ REG0_16 (insn
)] = temp
& 0xffffffff;
3105 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3106 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
3107 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
3108 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3109 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3113 void OP_F610 (insn
, extension
)
3114 unsigned long insn
, extension
;
3116 unsigned long long temp
;
3119 temp
= (State
.regs
[REG_D0
+ REG0 (insn
)] * State
.regs
[REG_D0
+ REG1 (insn
)]);
3120 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
3121 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3122 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
3123 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
3124 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3125 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3129 void OP_F91400 (insn
, extension
)
3130 unsigned long insn
, extension
;
3132 unsigned long long temp
;
3135 temp
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] * SEXT8 (insn
& 0xff));
3136 State
.regs
[REG_D0
+ REG0_8 (insn
)] = temp
& 0xffffffff;
3137 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3138 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
3139 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
3140 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3141 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3144 /* mulqu imm16,dn */
3145 void OP_FB140000 (insn
, extension
)
3146 unsigned long insn
, extension
;
3148 unsigned long long temp
;
3151 temp
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] * SEXT16 (insn
& 0xffff));
3152 State
.regs
[REG_D0
+ REG0_16 (insn
)] = temp
& 0xffffffff;
3153 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3154 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
3155 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
3156 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3157 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3160 /* mulqu imm32,dn */
3161 void OP_FD140000 (insn
, extension
)
3162 unsigned long insn
, extension
;
3164 unsigned long long temp
;
3167 temp
= (State
.regs
[REG_D0
+ REG0_16 (insn
)]
3168 * (((insn
& 0xffff) << 16) + extension
));
3169 State
.regs
[REG_D0
+ REG0_16 (insn
)] = temp
& 0xffffffff;
3170 State
.regs
[REG_MDRQ
] = (temp
& 0xffffffff00000000LL
) >> 32;;
3171 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
3172 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
3173 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
3174 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
3178 void OP_F640 (insn
, extension
)
3179 unsigned long insn
, extension
;
3183 temp
= State
.regs
[REG_D0
+ REG1 (insn
)];
3184 temp
= (temp
> 0x7fff ? 0x7fff : temp
);
3185 temp
= (temp
< -0x8000 ? -0x8000 : temp
);
3186 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
;
3190 void OP_F650 (insn
, extension
)
3191 unsigned long insn
, extension
;
3195 temp
= State
.regs
[REG_D0
+ REG1 (insn
)];
3196 temp
= (temp
> 0x7fffff ? 0x7fffff : temp
);
3197 temp
= (temp
< -0x800000 ? -0x800000 : temp
);
3198 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
;
3202 void OP_F670 (insn
, extension
)
3203 unsigned long insn
, extension
;
3207 temp
= State
.regs
[REG_D0
+ REG1 (insn
)];
3208 temp
<<= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x1f);
3209 c
= (temp
!= 0 ? 1 : 0);
3211 PSW
|= (c
? PSW_C
: 0);
3216 OP_FF (insn
, extension
)
3217 unsigned long insn
, extension
;
3219 State
.exception
= SIGTRAP
;
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