sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov imm8, dn */
  66 void OP_8000 ()
  67 {
  68   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
  69 }
  70
  71 /* mov dm, dn */
  72 void OP_80 ()
  73 {
  74   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
  75 }
  76
  77 /* mov dm, an */
  78 void OP_F1E0 ()
  79 {
  80   State.regs[REG_A0 + ((insn & 0xc) >> 2)] = State.regs[REG_D0 + (insn & 0x3)];
  81 }
  82
  83 /* mov am, dn */
  84 void OP_F1D0 ()
  85 {
  86   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  87 }
  88
  89 /* mov imm8, an */
  90 void OP_9000 ()
  91 {
  92   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
  93 }
  94
  95 /* mov am, an */
  96 void OP_90 ()
  97 {
  98   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  99 }
 100
 101 /* mov sp, an */
 102 void OP_3C ()
 103 {
 104   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
 105 }
 106
 107 /* mov am, sp */
 108 void OP_F2F0 ()
 109 {
 110   State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 111 }
 112
 113 /* mov psw, dn */
 114 void OP_F2E4 ()
 115 {
 116   State.regs[REG_D0 + (insn & 0x3)] = PSW;
 117 }
 118
 119 /* mov dm, psw */
 120 void OP_F2F3 ()
 121 {
 122   PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 123 }
 124
 125 /* mov mdr, dn */
 126 void OP_F2E0 ()
 127 {
 128   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
 129 }
 130
 131 /* mov dm, mdr */
 132 void OP_F2F2 ()
 133 {
 134   State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 135 }
 136
 137 /* mov */
 138 void OP_70 ()
 139 {
 140   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 141     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 142 }
 143
 144 /* mov */
 145 void OP_F80000 ()
 146 {
 147 }
 148
 149 /* mov */
 150 void OP_FA000000 ()
 151 {
 152 }
 153
 154 /* mov */
 155 void OP_FC000000 ()
 156 {
 157 }
 158
 159 /* mov (d8,sp), dn */
 160 void OP_5800 ()
 161 {
 162   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 163     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 164 }
 165
 166 /* mov */
 167 void OP_FAB40000 ()
 168 {
 169 }
 170
 171 /* mov */
 172 void OP_FCB40000 ()
 173 {
 174 }
 175
 176 /* mov (di,am), dn */
 177 void OP_F300 ()
 178 {
 179   State.regs[REG_D0 + ((insn & 0x30) >> 8)]
 180     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 181                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 182 }
 183
 184 /* mov (abs16), dn */
 185 void OP_300000 ()
 186 {
 187   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 4);
 188 }
 189
 190 /* mov */
 191 void OP_FCA40000 ()
 192 {
 193 }
 194
 195 /* mov (am), an */
 196 void OP_F000 ()
 197 {
 198   State.regs[REG_A0 + ((insn & 0xc) >> 2)]
 199     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 200 }
 201
 202 /* mov */
 203 void OP_F82000 ()
 204 {
 205 }
 206
 207 /* mov */
 208 void OP_FA200000 ()
 209 {
 210 }
 211
 212 /* mov */
 213 void OP_FC200000 ()
 214 {
 215 }
 216
 217 /* mov (d8,sp), an */
 218 void OP_5C00 ()
 219 {
 220   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 221     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 222 }
 223
 224 /* mov */
 225 void OP_FAB00000 ()
 226 {
 227 }
 228
 229 /* mov */
 230 void OP_FCB00000 ()
 231 {
 232 }
 233
 234 /* mov (di,am), an*/
 235 void OP_F380 ()
 236 {
 237   State.regs[REG_A0 + ((insn & 0x30) >> 8)]
 238     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 239                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 240 }
 241
 242 /* mov */
 243 void OP_FAA00000 ()
 244 {
 245 }
 246
 247 /* mov */
 248 void OP_FCA00000 ()
 249 {
 250 }
 251
 252 /* mov */
 253 void OP_F8F000 ()
 254 {
 255 }
 256
 257 /* mov dm, (an) */
 258 void OP_60 ()
 259 {
 260   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 261              State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
 262 }
 263
 264 /* mov */
 265 void OP_F81000 ()
 266 {
 267 }
 268
 269 /* mov */
 270 void OP_FA100000 ()
 271 {
 272 }
 273
 274 /* mov */
 275 void OP_FC100000 ()
 276 {
 277 }
 278
 279 /* mov dm, (d8,sp) */
 280 void OP_4200 ()
 281 {
 282   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 283              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 284 }
 285
 286 /* mov */
 287 void OP_FA910000 ()
 288 {
 289 }
 290
 291 /* mov */
 292 void OP_FC910000 ()
 293 {
 294 }
 295
 296 /* mov dm, (di,an) */
 297 void OP_F340 ()
 298 {
 299   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 300               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 301              State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
 302 }
 303
 304 /* mov dm, (abs16) */
 305 void OP_10000 ()
 306 {
 307   store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 308 }
 309
 310 /* mov */
 311 void OP_FC810000 ()
 312 {
 313 }
 314
 315 /* mov am, (an) */
 316 void OP_F010 ()
 317 {
 318   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 319              State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
 320 }
 321
 322 /* mov */
 323 void OP_F83000 ()
 324 {
 325 }
 326
 327 /* mov */
 328 void OP_FA300000 ()
 329 {
 330 }
 331
 332 /* mov */
 333 void OP_FC300000 ()
 334 {
 335 }
 336
 337 /* mov am, (d8,sp) */
 338 void OP_4300 ()
 339 {
 340   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 341              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 342 }
 343
 344 /* mov */
 345 void OP_FA900000 ()
 346 {
 347 }
 348
 349 /* mov */
 350 void OP_FC900000 ()
 351 {
 352 }
 353
 354 /* mov am, (di,an) */
 355 void OP_F3C0 ()
 356 {
 357   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 358               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 359              State.regs[REG_A0 + ((insn & 0x30) >> 8)]);
 360 }
 361
 362 /* mov */
 363 void OP_FA800000 ()
 364 {
 365 }
 366
 367 /* mov */
 368 void OP_FC800000 ()
 369 {
 370 }
 371
 372 /* mov */
 373 void OP_F8F400 ()
 374 {
 375 }
 376
 377 /* mov imm16, dn */
 378 void OP_2C0000 ()
 379 {
 380   unsigned long value;
 381
 382   value = SEXT16 (insn & 0xffff);
 383   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 384 }
 385
 386 /* mov */
 387 void OP_FCCC0000 ()
 388 {
 389 }
 390
 391 /* mov imm16, an */
 392 void OP_240000 ()
 393 {
 394   unsigned long value;
 395
 396   value = insn & 0xffff;
 397   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 398 }
 399
 400 /* mov imm32, an*/
 401 void OP_FCDC0000 ()
 402 {
 403   unsigned long value;
 404
 405   value = (insn & 0xffff) << 16 | extension;
 406   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 407 }
 408
 409 /* movbu (am), dn */
 410 void OP_F040 ()
 411 {
 412   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 413     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
 414 }
 415
 416 /* movbu */
 417 void OP_F84000 ()
 418 {
 419 }
 420
 421 /* movbu */
 422 void OP_FA400000 ()
 423 {
 424 }
 425
 426 /* movbu */
 427 void OP_FC400000 ()
 428 {
 429 }
 430
 431 /* movbu */
 432 void OP_F8B800 ()
 433 {
 434 }
 435
 436 /* movbu */
 437 void OP_FAB80000 ()
 438 {
 439 }
 440
 441 /* movbu */
 442 void OP_FCB80000 ()
 443 {
 444 }
 445
 446 /* movbu (di,am), dn */
 447 void OP_F400 ()
 448 {
 449   State.regs[REG_D0 + ((insn & 0x30) >> 8)]
 450     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 451                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
 452 }
 453
 454 /* movbu (abs16), dn */
 455 void OP_340000 ()
 456 {
 457   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 1);
 458 }
 459
 460 /* movbu */
 461 void OP_FCA80000 ()
 462 {
 463 }
 464
 465 /* movbu dm, (an) */
 466 void OP_F050 ()
 467 {
 468   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 469              State.regs[REG_D0 + (insn & 0x3)]);
 470 }
 471
 472 /* movbu */
 473 void OP_F85000 ()
 474 {
 475 }
 476
 477 /* movbu */
 478 void OP_FA500000 ()
 479 {
 480 }
 481
 482 /* movbu */
 483 void OP_FC500000 ()
 484 {
 485 }
 486
 487 /* movbu */
 488 void OP_F89200 ()
 489 {
 490 }
 491
 492 /* movbu */
 493 void OP_FA920000 ()
 494 {
 495 }
 496
 497 /* movbu */
 498 void OP_FC920000 ()
 499 {
 500 }
 501
 502 /* movbu dm, (di,an) */
 503 void OP_F440 ()
 504 {
 505   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 506               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
 507              State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
 508 }
 509
 510 /* movbu dm, (abs16) */
 511 void OP_20000 ()
 512 {
 513   store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 514 }
 515
 516 /* movbu */
 517 void OP_FC820000 ()
 518 {
 519 }
 520
 521 /* movhu (am), dn */
 522 void OP_F060 ()
 523 {
 524   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 525     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
 526 }
 527
 528 /* movhu */
 529 void OP_F86000 ()
 530 {
 531 }
 532
 533 /* movhu */
 534 void OP_FA600000 ()
 535 {
 536 }
 537
 538 /* movhu */
 539 void OP_FC600000 ()
 540 {
 541 }
 542
 543 /* movhu */
 544 void OP_F8BC00 ()
 545 {
 546 }
 547
 548 /* movhu */
 549 void OP_FABC0000 ()
 550 {
 551 }
 552
 553 /* movhu */
 554 void OP_FCBC0000 ()
 555 {
 556 }
 557
 558 /* movhu (di,am), dn */
 559 void OP_F480 ()
 560 {
 561   State.regs[REG_D0 + ((insn & 0x30) >> 8)]
 562     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 563                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
 564 }
 565
 566 /* movhu (abs16), dn */
 567 void OP_380000 ()
 568 {
 569   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 2);
 570 }
 571
 572 /* movhu */
 573 void OP_FCAC0000 ()
 574 {
 575 }
 576
 577 /* movhu dm, (an) */
 578 void OP_F070 ()
 579 {
 580   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 2,
 581              State.regs[REG_D0 + (insn & 0x3)]);
 582 }
 583
 584 /* movhu */
 585 void OP_F87000 ()
 586 {
 587 }
 588
 589 /* movhu */
 590 void OP_FA700000 ()
 591 {
 592 }
 593
 594 /* movhu */
 595 void OP_FC700000 ()
 596 {
 597 }
 598
 599 /* movhu */
 600 void OP_F89300 ()
 601 {
 602 }
 603
 604 /* movhu */
 605 void OP_FA930000 ()
 606 {
 607 }
 608
 609 /* movhu */
 610 void OP_FC930000 ()
 611 {
 612 }
 613
 614 /* movhu dm, (di,an) */
 615 void OP_F4C0 ()
 616 {
 617   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 618               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
 619              State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
 620 }
 621
 622 /* movhu dm, (abs16) */
 623 void OP_30000 ()
 624 {
 625   store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 626 }
 627
 628 /* movhu */
 629 void OP_FC830000 ()
 630 {
 631 }
 632
 633 /* ext dn */
 634 void OP_F2D0 ()
 635 {
 636   if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
 637     State.regs[REG_MDR] = -1;
 638   else
 639     State.regs[REG_MDR] = 0;
 640 }
 641
 642 /* extb dn */
 643 void OP_10 ()
 644 {
 645   State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
 646 }
 647
 648 /* extbu dn */
 649 void OP_14 ()
 650 {
 651   State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
 652 }
 653
 654 /* exth dn */
 655 void OP_18 ()
 656 {
 657   State.regs[REG_D0 + (insn & 0x3)]
 658     = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
 659 }
 660
 661 /* exthu dn */
 662 void OP_1C ()
 663 {
 664   State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
 665 }
 666
 667 /* movm (sp), reg_list */
 668 void OP_CE00 ()
 669 {
 670   unsigned long sp = State.regs[REG_SP];
 671   unsigned long mask;
 672
 673   mask = insn & 0xff;
 674
 675   if (mask & 0x8)
 676     {
 677       sp += 4;
 678       State.regs[REG_LAR] = load_mem (sp, 4);
 679       sp += 4;
 680       State.regs[REG_LIR] = load_mem (sp, 4);
 681       sp += 4;
 682       State.regs[REG_MDR] = load_mem (sp, 4);
 683       sp += 4;
 684       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 685       sp += 4;
 686       State.regs[REG_A0] = load_mem (sp, 4);
 687       sp += 4;
 688       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 689       sp += 4;
 690       State.regs[REG_D0] = load_mem (sp, 4);
 691       sp += 4;
 692     }
 693
 694   if (mask & 0x10)
 695     {
 696       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 697       sp += 4;
 698     }
 699
 700   if (mask & 0x20)
 701     {
 702       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 703       sp += 4;
 704     }
 705
 706   if (mask & 0x40)
 707     {
 708       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 709       sp += 4;
 710     }
 711
 712   if (mask & 0x80)
 713     {
 714       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 715       sp += 4;
 716     }
 717
 718   /* And make sure to update the stack pointer.  */
 719   State.regs[REG_SP] = sp;
 720 }
 721
 722 /* movm reg_list, (sp) */
 723 void OP_CF00 ()
 724 {
 725   unsigned long sp = State.regs[REG_SP];
 726   unsigned long mask;
 727
 728   mask = insn & 0xff;
 729
 730   if (mask & 0x80)
 731     {
 732       sp -= 4;
 733       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 734     }
 735
 736   if (mask & 0x40)
 737     {
 738       sp -= 4;
 739       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 740     }
 741
 742   if (mask & 0x20)
 743     {
 744       sp -= 4;
 745       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 746     }
 747
 748   if (mask & 0x10)
 749     {
 750       sp -= 4;
 751       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 752     }
 753
 754   if (mask & 0x8)
 755     {
 756       sp -= 4;
 757       State.regs[REG_D0] = load_mem (sp, 4);
 758       sp -= 4;
 759       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 760       sp -= 4;
 761       State.regs[REG_A0] = load_mem (sp, 4);
 762       sp -= 4;
 763       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 764       sp -= 4;
 765       State.regs[REG_MDR] = load_mem (sp, 4);
 766       sp -= 4;
 767       State.regs[REG_LIR] = load_mem (sp, 4);
 768       sp -= 4;
 769       State.regs[REG_LAR] = load_mem (sp, 4);
 770       sp -= 4;
 771     }
 772
 773   /* And make sure to update the stack pointer.  */
 774   State.regs[REG_SP] = sp;
 775 }
 776
 777 /* clr dn */
 778 void OP_0 ()
 779 {
 780   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 781
 782   PSW |= PSW_Z;
 783   PSW &= ~(PSW_V | PSW_C | PSW_N);
 784 }
 785
 786 /* add dm,dn*/
 787 void OP_E0 ()
 788 {
 789   int z, c, n, v;
 790   unsigned long reg1, reg2, value;
 791
 792   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 793   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 794   value = reg1 + reg2;
 795   State.regs[REG_D0 + (insn & 0x3)] = value;
 796
 797   z = (value == 0);
 798   n = (value & 0x80000000);
 799   c = (reg1 < reg2);
 800   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 801        && (reg2 & 0x8000000) != (value & 0x80000000));
 802
 803   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 804   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 805           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 806 }
 807
 808 /* add dm, an */
 809 void OP_F160 ()
 810 {
 811   int z, c, n, v;
 812   unsigned long reg1, reg2, value;
 813
 814   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 815   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 816   value = reg1 + reg2;
 817   State.regs[REG_A0 + (insn & 0x3)] = value;
 818
 819   z = (value == 0);
 820   n = (value & 0x80000000);
 821   c = (reg1 < reg2);
 822   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 823        && (reg2 & 0x8000000) != (value & 0x80000000));
 824
 825   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 826   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 827           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 828 }
 829
 830 /* add am, dn*/
 831 void OP_F150 ()
 832 {
 833   int z, c, n, v;
 834   unsigned long reg1, reg2, value;
 835
 836   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 837   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 838   value = reg1 + reg2;
 839   State.regs[REG_D0 + (insn & 0x3)] = value;
 840
 841   z = (value == 0);
 842   n = (value & 0x80000000);
 843   c = (reg1 < reg2);
 844   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 845        && (reg2 & 0x8000000) != (value & 0x80000000));
 846
 847   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 848   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 849           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 850 }
 851
 852 /* add am,an */
 853 void OP_F170 ()
 854 {
 855   int z, c, n, v;
 856   unsigned long reg1, reg2, value;
 857
 858   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 859   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 860   value = reg1 + reg2;
 861   State.regs[REG_A0 + (insn & 0x3)] = value;
 862
 863   z = (value == 0);
 864   n = (value & 0x80000000);
 865   c = (reg1 < reg2);
 866   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 867        && (reg2 & 0x8000000) != (value & 0x80000000));
 868
 869   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 870   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 871           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 872 }
 873
 874 /* add imm8, dn */
 875 void OP_2800 ()
 876 {
 877   int z, c, n, v;
 878   unsigned long reg1, imm, value;
 879
 880   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 881   imm = SEXT8 (insn & 0xff);
 882   value = reg1 + imm;
 883   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 884
 885   z = (value == 0);
 886   n = (value & 0x80000000);
 887   c = (reg1 < imm);
 888   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 889        && (imm & 0x8000000) != (value & 0x80000000));
 890
 891   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 892   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 893           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 894 }
 895
 896 /* add imm16, dn */
 897 void OP_FAC00000 ()
 898 {
 899   int z, c, n, v;
 900   unsigned long reg1, imm, value;
 901
 902   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 903   imm = SEXT16 (insn & 0xffff);
 904   value = reg1 + imm;
 905   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 906
 907   z = (value == 0);
 908   n = (value & 0x80000000);
 909   c = (reg1 < imm);
 910   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 911        && (imm & 0x8000000) != (value & 0x80000000));
 912
 913   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 914   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 915           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 916 }
 917
 918 /* add imm32,dn */
 919 void OP_FCC00000 ()
 920 {
 921   int z, c, n, v;
 922   unsigned long reg1, imm, value;
 923
 924   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 925   imm = ((insn & 0xffff) << 16) | extension;
 926   value = reg1 + imm;
 927   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 928
 929   z = (value == 0);
 930   n = (value & 0x80000000);
 931   c = (reg1 < imm);
 932   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 933        && (imm & 0x8000000) != (value & 0x80000000));
 934
 935   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 936   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 937           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 938 }
 939
 940 /* add imm8, an */
 941 void OP_2000 ()
 942 {
 943   int z, c, n, v;
 944   unsigned long reg1, imm, value;
 945
 946   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
 947   imm = insn & 0xff;
 948   value = reg1 + imm;
 949   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
 950
 951   z = (value == 0);
 952   n = (value & 0x80000000);
 953   c = (reg1 < imm);
 954   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 955        && (imm & 0x8000000) != (value & 0x80000000));
 956
 957   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 958   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 959           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 960 }
 961
 962 /* add imm16, an */
 963 void OP_FAD00000 ()
 964 {
 965   int z, c, n, v;
 966   unsigned long reg1, imm, value;
 967
 968   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 969   imm = 0xffff;
 970   value = reg1 + imm;
 971   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 972
 973   z = (value == 0);
 974   n = (value & 0x80000000);
 975   c = (reg1 < imm);
 976   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 977        && (imm & 0x8000000) != (value & 0x80000000));
 978
 979   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 980   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 981           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 982 }
 983
 984 /* add imm32, an */
 985 void OP_FCD00000 ()
 986 {
 987   int z, c, n, v;
 988   unsigned long reg1, imm, value;
 989
 990   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 991   imm = ((insn & 0xffff) << 16) | extension;
 992   value = reg1 + imm;
 993   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 994
 995   z = (value == 0);
 996   n = (value & 0x80000000);
 997   c = (reg1 < imm);
 998   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 999        && (imm & 0x8000000) != (value & 0x80000000));
1000
1001   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1002   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1003           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1004 }
1005
1006 /* add imm8, sp*/
1007 void OP_F8FE00 ()
1008 {
1009   int z, c, n, v;
1010   unsigned long reg1, imm, value;
1011
1012   reg1 = State.regs[REG_SP];
1013   imm = SEXT8 (insn & 0xff);
1014   value = reg1 + imm;
1015   State.regs[REG_SP] = value;
1016
1017   z = (value == 0);
1018   n = (value & 0x80000000);
1019   c = (reg1 < imm);
1020   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1021        && (imm & 0x8000000) != (value & 0x80000000));
1022
1023   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1024   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1025           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1026 }
1027
1028 /* add imm16,sp */
1029 void OP_FAFE0000 ()
1030 {
1031   int z, c, n, v;
1032   unsigned long reg1, imm, value;
1033
1034   reg1 = State.regs[REG_SP];
1035   imm = SEXT16 (insn & 0xffff);
1036   value = reg1 + imm;
1037   State.regs[REG_SP] = value;
1038
1039   z = (value == 0);
1040   n = (value & 0x80000000);
1041   c = (reg1 < imm);
1042   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1043        && (imm & 0x8000000) != (value & 0x80000000));
1044
1045   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1046   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1047           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1048 }
1049
1050 /* add */
1051 void OP_FCFE0000 ()
1052 {
1053   int z, c, n, v;
1054   unsigned long reg1, imm, value;
1055
1056   reg1 = State.regs[REG_SP];
1057   imm = ((insn & 0xffff) << 16) | extension;
1058   value = reg1 + imm;
1059   State.regs[REG_SP] = value;
1060
1061   z = (value == 0);
1062   n = (value & 0x80000000);
1063   c = (reg1 < imm);
1064   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1065        && (imm & 0x8000000) != (value & 0x80000000));
1066
1067   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1068   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1069           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1070 }
1071
1072 /* addc */
1073 void OP_F140 ()
1074 {
1075   int z, c, n, v;
1076   unsigned long reg1, reg2, value;
1077
1078   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1079   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1080   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1081   State.regs[REG_D0 + (insn & 0x3)] = value;
1082
1083   z = (value == 0);
1084   n = (value & 0x80000000);
1085   c = (reg1 < reg2);
1086   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1087        && (reg2 & 0x8000000) != (value & 0x80000000));
1088
1089   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1090   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1091           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1092 }
1093
1094 /* sub dm, dn */
1095 void OP_F100 ()
1096 {
1097   int z, c, n, v;
1098   unsigned long reg1, reg2, value;
1099
1100   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1101   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1102   value = reg2 - reg1;
1103
1104   z = (value == 0);
1105   n = (value & 0x80000000);
1106   c = (reg1 < reg2);
1107   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1108        && (reg2 & 0x8000000) != (value & 0x80000000));
1109
1110   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1111   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1112           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1113   State.regs[REG_D0 + (insn & 0x3)] = value;
1114 }
1115
1116 /* sub dm, an */
1117 void OP_F120 ()
1118 {
1119   int z, c, n, v;
1120   unsigned long reg1, reg2, value;
1121
1122   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1123   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1124   value = reg2 - reg1;
1125
1126   z = (value == 0);
1127   n = (value & 0x80000000);
1128   c = (reg1 < reg2);
1129   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1130        && (reg2 & 0x8000000) != (value & 0x80000000));
1131
1132   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1133   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1134           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1135   State.regs[REG_A0 + (insn & 0x3)] = value;
1136 }
1137
1138 /* sub am, dn */
1139 void OP_F110 ()
1140 {
1141   int z, c, n, v;
1142   unsigned long reg1, reg2, value;
1143
1144   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1145   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1146   value = reg2 - reg1;
1147
1148   z = (value == 0);
1149   n = (value & 0x80000000);
1150   c = (reg1 < reg2);
1151   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1152        && (reg2 & 0x8000000) != (value & 0x80000000));
1153
1154   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1155   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1156           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1157   State.regs[REG_D0 + (insn & 0x3)] = value;
1158 }
1159
1160 /* sub am, an */
1161 void OP_F130 ()
1162 {
1163   int z, c, n, v;
1164   unsigned long reg1, reg2, value;
1165
1166   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1167   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1168   value = reg2 - reg1;
1169
1170   z = (value == 0);
1171   n = (value & 0x80000000);
1172   c = (reg1 < reg2);
1173   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1174        && (reg2 & 0x8000000) != (value & 0x80000000));
1175
1176   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1177   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1178           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1179   State.regs[REG_A0 + (insn & 0x3)] = value;
1180 }
1181
1182 /* sub */
1183 void OP_FCC40000 ()
1184 {
1185   int z, c, n, v;
1186   unsigned long reg1, imm, value;
1187
1188   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1189   imm = ((insn & 0xffff) << 16) | extension;
1190   value = reg1 - imm;
1191
1192   z = (value == 0);
1193   n = (value & 0x80000000);
1194   c = (reg1 < imm);
1195   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1196        && (imm & 0x8000000) != (value & 0x80000000));
1197
1198   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1199   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1200           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1201   State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
1202 }
1203
1204 /* sub */
1205 void OP_FCD40000 ()
1206 {
1207   int z, c, n, v;
1208   unsigned long reg1, imm, value;
1209
1210   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1211   imm = ((insn & 0xffff) << 16) | extension;
1212   value = reg1 - imm;
1213
1214   z = (value == 0);
1215   n = (value & 0x80000000);
1216   c = (reg1 < imm);
1217   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1218        && (imm & 0x8000000) != (value & 0x80000000));
1219
1220   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1221   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1222           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1223   State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
1224 }
1225
1226 /* subc */
1227 void OP_F180 ()
1228 {
1229   int z, c, n, v;
1230   unsigned long reg1, reg2, value;
1231
1232   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1233   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1234   value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1235
1236   z = (value == 0);
1237   n = (value & 0x80000000);
1238   c = (reg1 < reg2);
1239   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1240        && (reg2 & 0x8000000) != (value & 0x80000000));
1241
1242   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1243   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1244           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1245   State.regs[REG_D0 + (insn & 0x3)] = value;
1246 }
1247
1248 /* mul */
1249 void OP_F240 ()
1250 {
1251   unsigned long long temp;
1252   int n, z;
1253
1254   temp = (State.regs[REG_D0 + (insn & 0x3)]
1255           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1256   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1257   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1258   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1259   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1260   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1261   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1262 }
1263
1264 /* mulu */
1265 void OP_F250 ()
1266 {
1267   unsigned long long temp;
1268   int n, z;
1269
1270   temp = (State.regs[REG_D0 + (insn & 0x3)]
1271           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1272   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1273   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1274   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1275   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1276   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1277   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1278 }
1279
1280 /* div */
1281 void OP_F260 ()
1282 {
1283   long long temp;
1284   int n, z;
1285
1286   temp = State.regs[REG_MDR];
1287   temp <<= 32;
1288   temp |= State.regs[REG_D0 + (insn & 0x3)];
1289   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1290   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1291   temp = (State.regs[REG_D0 + (insn & 0x3)]
1292           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1293   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1294   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1295   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1296   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1297   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1298   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1299 }
1300
1301 /* divu */
1302 void OP_F270 ()
1303 {
1304   unsigned long long temp;
1305   int n, z;
1306
1307   temp = State.regs[REG_MDR];
1308   temp <<= 32;
1309   temp |= State.regs[REG_D0 + (insn & 0x3)];
1310   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1311   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1312   temp = (State.regs[REG_D0 + (insn & 0x3)]
1313           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1314   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1315   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1316   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1317   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1318   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1319   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1320 }
1321
1322 /* inc dn */
1323 void OP_40 ()
1324 {
1325   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
1326 }
1327
1328 /* inc an */
1329 void OP_41 ()
1330 {
1331   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1332 }
1333
1334 /* inc4 an */
1335 void OP_50 ()
1336 {
1337   State.regs[REG_A0 + (insn & 0x3)] += 4;
1338 }
1339
1340 /* cmp imm8, dn */
1341 void OP_A000 ()
1342 {
1343   int z, c, n, v;
1344   unsigned long reg1, imm, value;
1345
1346   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1347   imm = SEXT8 (insn & 0xff);
1348   value = reg1 - imm;
1349
1350   z = (value == 0);
1351   n = (value & 0x80000000);
1352   c = (reg1 < imm);
1353   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1354        && (imm & 0x8000000) != (value & 0x80000000));
1355
1356   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1357   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1358           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1359 }
1360
1361 /* cmp dm, dn */
1362 void OP_A0 ()
1363 {
1364   int z, c, n, v;
1365   unsigned long reg1, reg2, value;
1366
1367   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1368   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1369   value = reg2 - reg1;
1370
1371   z = (value == 0);
1372   n = (value & 0x80000000);
1373   c = (reg1 < reg2);
1374   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1375        && (reg2 & 0x8000000) != (value & 0x80000000));
1376
1377   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1378   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1379           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1380 }
1381
1382 /* cmp dm, an */
1383 void OP_F1A0 ()
1384 {
1385   int z, c, n, v;
1386   unsigned long reg1, reg2, value;
1387
1388   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1389   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1390   value = reg2 - reg1;
1391
1392   z = (value == 0);
1393   n = (value & 0x80000000);
1394   c = (reg1 < reg2);
1395   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1396        && (reg2 & 0x8000000) != (value & 0x80000000));
1397
1398   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1399   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1400           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1401 }
1402
1403 /* cmp am, dn */
1404 void OP_F190 ()
1405 {
1406   int z, c, n, v;
1407   unsigned long reg1, reg2, value;
1408
1409   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1410   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1411   value = reg2 - reg1;
1412
1413   z = (value == 0);
1414   n = (value & 0x80000000);
1415   c = (reg1 < reg2);
1416   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1417        && (reg2 & 0x8000000) != (value & 0x80000000));
1418
1419   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1420   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1421           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1422 }
1423
1424 /* cmp imm8, an */
1425 void OP_B000 ()
1426 {
1427   int z, c, n, v;
1428   unsigned long reg1, imm, value;
1429
1430   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1431   imm = insn & 0xff;
1432   value = reg1 - imm;
1433
1434   z = (value == 0);
1435   n = (value & 0x80000000);
1436   c = (reg1 < imm);
1437   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1438        && (imm & 0x8000000) != (value & 0x80000000));
1439
1440   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1441   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1442           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1443 }
1444
1445 /* cmp am, an */
1446 void OP_B0 ()
1447 {
1448   int z, c, n, v;
1449   unsigned long reg1, reg2, value;
1450
1451   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1452   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1453   value = reg2 - reg1;
1454
1455   z = (value == 0);
1456   n = (value & 0x80000000);
1457   c = (reg1 < reg2);
1458   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1459        && (reg2 & 0x8000000) != (value & 0x80000000));
1460
1461   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1462   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1463           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1464 }
1465
1466 /* cmp imm16, dn */
1467 void OP_FAC80000 ()
1468 {
1469   int z, c, n, v;
1470   unsigned long reg1, imm, value;
1471
1472   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1473   imm = SEXT16 (insn & 0xffff);
1474   value = reg1 - imm;
1475
1476   z = (value == 0);
1477   n = (value & 0x80000000);
1478   c = (reg1 < imm);
1479   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1480        && (imm & 0x8000000) != (value & 0x80000000));
1481
1482   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1483   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1484           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1485 }
1486
1487 /* cmp imm32, dn */
1488 void OP_FCC80000 ()
1489 {
1490   int z, c, n, v;
1491   unsigned long reg1, imm, value;
1492
1493   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1494   imm = ((insn & 0xffff) << 16) | extension;
1495   value = reg1 - imm;
1496
1497   z = (value == 0);
1498   n = (value & 0x80000000);
1499   c = (reg1 < imm);
1500   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1501        && (imm & 0x8000000) != (value & 0x80000000));
1502
1503   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1504   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1505           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1506 }
1507
1508 /* cmp imm16, an */
1509 void OP_FAD80000 ()
1510 {
1511   int z, c, n, v;
1512   unsigned long reg1, imm, value;
1513
1514   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1515   imm = insn & 0xffff;
1516   value = reg1 - imm;
1517
1518   z = (value == 0);
1519   n = (value & 0x80000000);
1520   c = (reg1 < imm);
1521   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1522        && (imm & 0x8000000) != (value & 0x80000000));
1523
1524   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1525   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1526           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1527 }
1528
1529 /* cmp imm32, an */
1530 void OP_FCD80000 ()
1531 {
1532   int z, c, n, v;
1533   unsigned long reg1, imm, value;
1534
1535   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1536   imm = ((insn & 0xffff) << 16) | extension;
1537   value = reg1 - imm;
1538
1539   z = (value == 0);
1540   n = (value & 0x80000000);
1541   c = (reg1 < imm);
1542   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1543        && (imm & 0x8000000) != (value & 0x80000000));
1544
1545   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1546   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1547           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1548 }
1549
1550 /* and dm, dn */
1551 void OP_F200 ()
1552 {
1553   int n, z;
1554
1555   State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1556   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1557   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1558   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1559   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1560 }
1561
1562 /* and */
1563 void OP_F8E000 ()
1564 {
1565 }
1566
1567 /* and */
1568 void OP_FAE00000 ()
1569 {
1570 }
1571
1572 /* and */
1573 void OP_FCE00000 ()
1574 {
1575 }
1576
1577 /* and */
1578 void OP_FAFC0000 ()
1579 {
1580 }
1581
1582 /* or dm, dn*/
1583 void OP_F210 ()
1584 {
1585   int n, z;
1586
1587   State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1588   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1589   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1590   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1591   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1592 }
1593
1594 /* or */
1595 void OP_F8E400 ()
1596 {
1597 }
1598
1599 /* or */
1600 void OP_FAE40000 ()
1601 {
1602 }
1603
1604 /* or */
1605 void OP_FCE40000 ()
1606 {
1607 }
1608
1609 /* or */
1610 void OP_FAFD0000 ()
1611 {
1612 }
1613
1614 /* xor dm, dn*/
1615 void OP_F220 ()
1616 {
1617   int n, z;
1618
1619   State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1620   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1621   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1622   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1623   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1624 }
1625
1626 /* xor */
1627 void OP_FAE80000 ()
1628 {
1629 }
1630
1631 /* xor */
1632 void OP_FCE80000 ()
1633 {
1634 }
1635
1636 /* not */
1637 void OP_F230 ()
1638 {
1639   int n, z;
1640
1641   State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1642   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1643   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1644   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1645   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1646 }
1647
1648 /* btst */
1649 void OP_F8EC00 ()
1650 {
1651 }
1652
1653 /* btst */
1654 void OP_FAEC0000 ()
1655 {
1656 }
1657
1658 /* btst */
1659 void OP_FCEC0000 ()
1660 {
1661 }
1662
1663 /* btst */
1664 void OP_FE020000 ()
1665 {
1666 }
1667
1668 /* btst */
1669 void OP_FAF80000 ()
1670 {
1671 }
1672
1673 /* bset dm, (an) */
1674 void OP_F080 ()
1675 {
1676   unsigned long temp;
1677   int z;
1678
1679   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1680   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1681   temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1682   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1683   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1684   PSW |= (z ? PSW_Z : 0);
1685 }
1686
1687 /* bset */
1688 void OP_FE000000 ()
1689 {
1690 }
1691
1692 /* bset */
1693 void OP_FAF00000 ()
1694 {
1695 }
1696
1697 /* bclr dm, (an) */
1698 void OP_F090 ()
1699 {
1700   unsigned long temp;
1701   int z;
1702
1703   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1704   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1705   temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1706   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1707   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1708   PSW |= (z ? PSW_Z : 0);
1709 }
1710
1711 /* bclr */
1712 void OP_FE010000 ()
1713 {
1714 }
1715
1716 /* bclr */
1717 void OP_FAF40000 ()
1718 {
1719 }
1720
1721 /* asr */
1722 void OP_F2B0 ()
1723 {
1724   long temp;
1725   int z, n, c;
1726
1727   temp = State.regs[REG_D0 + (insn & 0x3)];
1728   c = temp & 1;
1729   temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1730   State.regs[REG_D0 + (insn & 0x3)] = temp;
1731   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1732   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1733   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1734   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1735 }
1736
1737 /* asr */
1738 void OP_F8C800 ()
1739 {
1740 }
1741
1742 /* lsr */
1743 void OP_F2A0 ()
1744 {
1745   int z, n, c;
1746
1747   c = State.regs[REG_D0 + (insn & 0x3)] & 1;
1748   State.regs[REG_D0 + (insn & 0x3)]
1749     >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1750   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1751   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1752   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1753   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1754 }
1755
1756 /* lsr */
1757 void OP_F8C400 ()
1758 {
1759 }
1760
1761 /* asl */
1762 void OP_F290 ()
1763 {
1764   int n, z;
1765
1766   State.regs[REG_D0 + (insn & 0x3)]
1767     <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1768   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1769   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1770   PSW &= ~(PSW_Z | PSW_N);
1771   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1772 }
1773
1774 /* asl */
1775 void OP_F8C000 ()
1776 {
1777 }
1778
1779 /* asl2 dn */
1780 void OP_54 ()
1781 {
1782   int n, z;
1783
1784   State.regs[REG_D0 + (insn & 0x3)] <<= 2;
1785   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1786   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1787   PSW &= ~(PSW_Z | PSW_N);
1788   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1789 }
1790
1791 /* ror dn */
1792 void OP_F284 ()
1793 {
1794   unsigned long value;
1795   int c,n,z;
1796
1797   value = State.regs[REG_D0 + (insn & 0x3)];
1798   if (value & 0x1)
1799     c = 1;
1800
1801   value >>= 1;
1802   value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1803   State.regs[REG_D0 + (insn & 0x3)] = value;
1804   z = (value == 0);
1805   n = (value & 0x8000000) != 0;
1806   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1807   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1808 }
1809
1810 /* rol dn */
1811 void OP_F280 ()
1812 {
1813   unsigned long value;
1814   int c,n,z;
1815
1816   value = State.regs[REG_D0 + (insn & 0x3)];
1817   if (value & 0x80000000)
1818     c = 1;
1819
1820   value <<= 1;
1821   value |= ((PSW & PSW_C) != 0);
1822   State.regs[REG_D0 + (insn & 0x3)] = value;
1823   z = (value == 0);
1824   n = (value & 0x8000000) != 0;
1825   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1826   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1827 }
1828
1829 /* beq label:8 */
1830 void OP_C800 ()
1831 {
1832   /* The dispatching code will add 2 after we return, so
1833      we subtract two here to make things right.  */
1834   if (PSW & PSW_Z)
1835     State.pc += SEXT8 (insn & 0xff) - 2;
1836 }
1837
1838 /* bne label:8 */
1839 void OP_C900 ()
1840 {
1841   /* The dispatching code will add 2 after we return, so
1842      we subtract two here to make things right.  */
1843   if (!(PSW & PSW_Z))
1844     State.pc += SEXT8 (insn & 0xff) - 2;
1845 }
1846
1847 /* bgt label:8 */
1848 void OP_C100 ()
1849 {
1850   /* The dispatching code will add 2 after we return, so
1851      we subtract two here to make things right.  */
1852   if (!((PSW & PSW_Z)
1853         || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
1854     State.pc += SEXT8 (insn & 0xff) - 2;
1855 }
1856
1857 /* bge label:8 */
1858 void OP_C200 ()
1859 {
1860   /* The dispatching code will add 2 after we return, so
1861      we subtract two here to make things right.  */
1862   if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
1863     State.pc += SEXT8 (insn & 0xff) - 2;
1864 }
1865
1866 /* ble label:8 */
1867 void OP_C300 ()
1868 {
1869   /* The dispatching code will add 2 after we return, so
1870      we subtract two here to make things right.  */
1871   if ((PSW & PSW_Z)
1872        || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
1873     State.pc += SEXT8 (insn & 0xff) - 2;
1874 }
1875
1876 /* blt label:8 */
1877 void OP_C000 ()
1878 {
1879   /* The dispatching code will add 2 after we return, so
1880      we subtract two here to make things right.  */
1881   if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
1882     State.pc += SEXT8 (insn & 0xff) - 2;
1883 }
1884
1885 /* bhi label:8 */
1886 void OP_C500 ()
1887 {
1888   /* The dispatching code will add 2 after we return, so
1889      we subtract two here to make things right.  */
1890   if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
1891     State.pc += SEXT8 (insn & 0xff) - 2;
1892 }
1893
1894 /* bcc label:8 */
1895 void OP_C600 ()
1896 {
1897   /* The dispatching code will add 2 after we return, so
1898      we subtract two here to make things right.  */
1899   if (!(PSW & PSW_C))
1900     State.pc += SEXT8 (insn & 0xff) - 2;
1901 }
1902
1903 /* bls label:8 */
1904 void OP_C700 ()
1905 {
1906   /* The dispatching code will add 2 after we return, so
1907      we subtract two here to make things right.  */
1908   if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
1909     State.pc += SEXT8 (insn & 0xff) - 2;
1910 }
1911
1912 /* bcs label:8 */
1913 void OP_C400 ()
1914 {
1915   /* The dispatching code will add 2 after we return, so
1916      we subtract two here to make things right.  */
1917   if (PSW & PSW_C)
1918     State.pc += SEXT8 (insn & 0xff) - 2;
1919 }
1920
1921 /* bvc label:8 */
1922 void OP_F8E800 ()
1923 {
1924   /* The dispatching code will add 3 after we return, so
1925      we subtract two here to make things right.  */
1926   if (!(PSW & PSW_V))
1927     State.pc += SEXT8 (insn & 0xff) - 3;
1928 }
1929
1930 /* bvs label:8 */
1931 void OP_F8E900 ()
1932 {
1933   /* The dispatching code will add 3 after we return, so
1934      we subtract two here to make things right.  */
1935   if (PSW & PSW_V)
1936     State.pc += SEXT8 (insn & 0xff) - 3;
1937 }
1938
1939 /* bnc label:8 */
1940 void OP_F8EA00 ()
1941 {
1942   /* The dispatching code will add 3 after we return, so
1943      we subtract two here to make things right.  */
1944   if (!(PSW & PSW_N))
1945     State.pc += SEXT8 (insn & 0xff) - 3;
1946 }
1947
1948 /* bns label:8 */
1949 void OP_F8EB00 ()
1950 {
1951   /* The dispatching code will add 3 after we return, so
1952      we subtract two here to make things right.  */
1953   if (PSW & PSW_N)
1954     State.pc += SEXT8 (insn & 0xff) - 3;
1955 }
1956
1957 /* bra label:8 */
1958 void OP_CA00 ()
1959 {
1960   /* The dispatching code will add 2 after we return, so
1961      we subtract two here to make things right.  */
1962   State.pc += SEXT8 (insn & 0xff) - 2;
1963 }
1964
1965 /* leq */
1966 void OP_D8 ()
1967 {
1968  abort ();
1969 }
1970
1971 /* lne */
1972 void OP_D9 ()
1973 {
1974  abort ();
1975 }
1976
1977 /* lgt */
1978 void OP_D1 ()
1979 {
1980  abort ();
1981 }
1982
1983 /* lge */
1984 void OP_D2 ()
1985 {
1986  abort ();
1987 }
1988
1989 /* lle */
1990 void OP_D3 ()
1991 {
1992  abort ();
1993 }
1994
1995 /* llt */
1996 void OP_D0 ()
1997 {
1998  abort ();
1999 }
2000
2001 /* lhi */
2002 void OP_D5 ()
2003 {
2004  abort ();
2005 }
2006
2007 /* lcc */
2008 void OP_D6 ()
2009 {
2010  abort ();
2011 }
2012
2013 /* lls */
2014 void OP_D7 ()
2015 {
2016  abort ();
2017 }
2018
2019 /* lcs */
2020 void OP_D4 ()
2021 {
2022  abort ();
2023 }
2024
2025 /* lra */
2026 void OP_DA ()
2027 {
2028  abort ();
2029 }
2030
2031 /* setlb */
2032 void OP_DB ()
2033 {
2034  abort ();
2035 }
2036
2037 /* jmp (an) */
2038 void OP_F0F4 ()
2039 {
2040   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2041 }
2042
2043 /* jmp label:16 */
2044 void OP_CC0000 ()
2045 {
2046   State.pc += SEXT16 (insn & 0xffff) - 3;
2047 }
2048
2049 /* jmp label:32 */
2050 void OP_DC000000 ()
2051 {
2052   State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2053 }
2054
2055 /* call label:16,reg_list,imm8 */
2056 void OP_CD000000 ()
2057 {
2058   unsigned int next_pc, sp, adjust;
2059   unsigned long mask;
2060
2061   sp = State.regs[REG_SP];
2062   next_pc = State.pc + 2;
2063   State.mem[sp] = next_pc & 0xff;
2064   State.mem[sp+1] = next_pc & 0xff00;
2065   State.mem[sp+2] = next_pc & 0xff0000;
2066   State.mem[sp+3] = next_pc & 0xff000000;
2067
2068   mask = insn & 0xff;
2069
2070   adjust = 0;
2071   if (mask & 0x80)
2072     {
2073       adjust -= 4;
2074       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2075     }
2076
2077   if (mask & 0x40)
2078     {
2079       adjust -= 4;
2080       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2081     }
2082
2083   if (mask & 0x20)
2084     {
2085       adjust -= 4;
2086       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2087     }
2088
2089   if (mask & 0x10)
2090     {
2091       adjust -= 4;
2092       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2093     }
2094
2095   if (mask & 0x8)
2096     {
2097       adjust -= 4;
2098       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2099       adjust -= 4;
2100       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2101       adjust -= 4;
2102       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2103       adjust -= 4;
2104       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2105       adjust -= 4;
2106       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2107       adjust -= 4;
2108       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2109       adjust -= 4;
2110       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2111       adjust -= 4;
2112     }
2113
2114   /* And make sure to update the stack pointer.  */
2115   State.regs[REG_SP] -= extension;
2116   State.regs[REG_MDR] = next_pc;
2117   State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2118 }
2119
2120 /* call label:32,reg_list,imm8*/
2121 void OP_DD000000 ()
2122 {
2123   unsigned int next_pc, sp, adjust;
2124   unsigned long mask;
2125
2126   sp = State.regs[REG_SP];
2127   next_pc = State.pc + 2;
2128   State.mem[sp] = next_pc & 0xff;
2129   State.mem[sp+1] = next_pc & 0xff00;
2130   State.mem[sp+2] = next_pc & 0xff0000;
2131   State.mem[sp+3] = next_pc & 0xff000000;
2132
2133   mask = (extension & 0xff00) >> 8;
2134
2135   adjust = 0;
2136   if (mask & 0x80)
2137     {
2138       adjust -= 4;
2139       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2140     }
2141
2142   if (mask & 0x40)
2143     {
2144       adjust -= 4;
2145       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2146     }
2147
2148   if (mask & 0x20)
2149     {
2150       adjust -= 4;
2151       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2152     }
2153
2154   if (mask & 0x10)
2155     {
2156       adjust -= 4;
2157       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2158     }
2159
2160   if (mask & 0x8)
2161     {
2162       adjust -= 4;
2163       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2164       adjust -= 4;
2165       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2166       adjust -= 4;
2167       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2168       adjust -= 4;
2169       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2170       adjust -= 4;
2171       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2172       adjust -= 4;
2173       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2174       adjust -= 4;
2175       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2176       adjust -= 4;
2177     }
2178
2179   /* And make sure to update the stack pointer.  */
2180   State.regs[REG_SP] -= (extension & 0xff);
2181   State.regs[REG_MDR] = next_pc;
2182   State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2183 }
2184
2185 /* calls (an) */
2186 void OP_F0F0 ()
2187 {
2188   unsigned int next_pc, sp;
2189
2190   sp = State.regs[REG_SP];
2191   next_pc = State.pc + 2;
2192   State.mem[sp] = next_pc & 0xff;
2193   State.mem[sp+1] = next_pc & 0xff00;
2194   State.mem[sp+2] = next_pc & 0xff0000;
2195   State.mem[sp+3] = next_pc & 0xff000000;
2196   State.regs[REG_MDR] = next_pc;
2197   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2198 }
2199
2200 /* calls label:16 */
2201 void OP_FAFF0000 ()
2202 {
2203   unsigned int next_pc, sp;
2204
2205   sp = State.regs[REG_SP];
2206   next_pc = State.pc + 4;
2207   State.mem[sp] = next_pc & 0xff;
2208   State.mem[sp+1] = next_pc & 0xff00;
2209   State.mem[sp+2] = next_pc & 0xff0000;
2210   State.mem[sp+3] = next_pc & 0xff000000;
2211   State.regs[REG_MDR] = next_pc;
2212   State.pc += SEXT16 (insn & 0xffff) - 4;
2213 }
2214
2215 /* calls label:32 */
2216 void OP_FCFF0000 ()
2217 {
2218   unsigned int next_pc, sp;
2219
2220   sp = State.regs[REG_SP];
2221   next_pc = State.pc + 6;
2222   State.mem[sp] = next_pc & 0xff;
2223   State.mem[sp+1] = next_pc & 0xff00;
2224   State.mem[sp+2] = next_pc & 0xff0000;
2225   State.mem[sp+3] = next_pc & 0xff000000;
2226   State.regs[REG_MDR] = next_pc;
2227   State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2228 }
2229
2230 /* ret */
2231 void OP_DF0000 ()
2232 {
2233   unsigned int sp;
2234   unsigned long mask;
2235
2236   State.regs[REG_SP] += insn & 0xff;
2237   State.pc = State.regs[REG_MDR] - 3;
2238   sp = State.regs[REG_SP];
2239
2240   mask = (insn & 0xff00) >> 8;
2241
2242   if (mask & 0x8)
2243     {
2244       sp += 4;
2245       State.regs[REG_LAR] = load_mem (sp, 4);
2246       sp += 4;
2247       State.regs[REG_LIR] = load_mem (sp, 4);
2248       sp += 4;
2249       State.regs[REG_MDR] = load_mem (sp, 4);
2250       sp += 4;
2251       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2252       sp += 4;
2253       State.regs[REG_A0] = load_mem (sp, 4);
2254       sp += 4;
2255       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2256       sp += 4;
2257       State.regs[REG_D0] = load_mem (sp, 4);
2258       sp += 4;
2259     }
2260
2261   if (mask & 0x10)
2262     {
2263       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2264       sp += 4;
2265     }
2266
2267   if (mask & 0x20)
2268     {
2269       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2270       sp += 4;
2271     }
2272
2273   if (mask & 0x40)
2274     {
2275       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2276       sp += 4;
2277     }
2278
2279   if (mask & 0x80)
2280     {
2281       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2282       sp += 4;
2283     }
2284 }
2285
2286 /* retf reg_list,imm8 */
2287 void OP_DE0000 ()
2288 {
2289   unsigned int sp;
2290   unsigned long mask;
2291
2292   State.regs[REG_SP] += insn & 0xff;
2293   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2294               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2295   State.pc -= 3;
2296
2297   sp = State.regs[REG_SP];
2298
2299   mask = (insn & 0xff00) >> 8;
2300
2301   if (mask & 0x8)
2302     {
2303       sp += 4;
2304       State.regs[REG_LAR] = load_mem (sp, 4);
2305       sp += 4;
2306       State.regs[REG_LIR] = load_mem (sp, 4);
2307       sp += 4;
2308       State.regs[REG_MDR] = load_mem (sp, 4);
2309       sp += 4;
2310       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2311       sp += 4;
2312       State.regs[REG_A0] = load_mem (sp, 4);
2313       sp += 4;
2314       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2315       sp += 4;
2316       State.regs[REG_D0] = load_mem (sp, 4);
2317       sp += 4;
2318     }
2319
2320   if (mask & 0x10)
2321     {
2322       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2323       sp += 4;
2324     }
2325
2326   if (mask & 0x20)
2327     {
2328       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2329       sp += 4;
2330     }
2331
2332   if (mask & 0x40)
2333     {
2334       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2335       sp += 4;
2336     }
2337
2338   if (mask & 0x80)
2339     {
2340       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2341       sp += 4;
2342     }
2343 }
2344
2345 /* rets */
2346 void OP_F0FC ()
2347 {
2348   unsigned int sp;
2349
2350   sp = State.regs[REG_SP];
2351   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2352               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2353   State.pc -= 2;
2354 }
2355
2356 /* rti */
2357 void OP_F0FD ()
2358 {
2359   abort ();
2360 }
2361
2362 /* trap */
2363 void OP_F0FE ()
2364 {
2365  abort ();
2366 }
2367
2368 /* rtm */
2369 void OP_F0FF ()
2370 {
2371  abort ();
2372 }
2373
2374 /* nop */
2375 void OP_CB ()
2376 {
2377 }
2378
2379 /* putx */
2380 void OP_F500 ()
2381 {
2382 }
2383
2384 /* getx */
2385 void OP_F6F0 ()
2386 {
2387 }
2388
2389 /* mulq */
2390 void OP_F600 ()
2391 {
2392 }
2393
2394 /* mulq */
2395 void OP_F90000 ()
2396 {
2397 }
2398
2399 /* mulq */
2400 void OP_FB000000 ()
2401 {
2402 }
2403
2404 /* mulq */
2405 void OP_FD000000 ()
2406 {
2407 }
2408
2409 /* mulqu */
2410 void OP_F610 ()
2411 {
2412 }
2413
2414 /* mulqu */
2415 void OP_F91400 ()
2416 {
2417 }
2418
2419 /* mulqu */
2420 void OP_FB140000 ()
2421 {
2422 }
2423
2424 /* mulqu */
2425 void OP_FD140000 ()
2426 {
2427 }
2428
2429 /* sat16 */
2430 void OP_F640 ()
2431 {
2432 }
2433
2434 /* sat24 */
2435 void OP_F650 ()
2436 {
2437 }
2438
2439 /* bsch */
2440 void OP_F670 ()
2441 {
2442 }