1 /* Simulator for TI MSP430 and MSP430X
3 Copyright (C) 2013-2014 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "opcode/msp430-decode.h"
32 #include "targ-vals.h"
35 loader_write_mem (SIM_DESC sd
,
37 const unsigned char *buf
,
40 SIM_CPU
*cpu
= MSP430_CPU (sd
);
41 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
45 msp430_pc_fetch (SIM_CPU
*cpu
)
47 return cpu
->state
.regs
[0];
51 msp430_pc_store (SIM_CPU
*cpu
, sim_cia newpc
)
53 cpu
->state
.regs
[0] = newpc
;
57 lookup_symbol (SIM_DESC sd
, const char *name
)
59 struct bfd
*abfd
= STATE_PROG_BFD (sd
);
60 asymbol
**symbol_table
= STATE_SYMBOL_TABLE (sd
);
61 long number_of_symbols
= STATE_NUM_SYMBOLS (sd
);
64 if (symbol_table
== NULL
)
68 storage_needed
= bfd_get_symtab_upper_bound (abfd
);
69 if (storage_needed
<= 0)
72 STATE_SYMBOL_TABLE (sd
) = symbol_table
= xmalloc (storage_needed
);
73 STATE_NUM_SYMBOLS (sd
) = number_of_symbols
=
74 bfd_canonicalize_symtab (abfd
, symbol_table
);
77 for (i
= 0; i
< number_of_symbols
; i
++)
78 if (strcmp (symbol_table
[i
]->name
, name
) == 0)
80 long val
= symbol_table
[i
]->section
->vma
+ symbol_table
[i
]->value
;
87 msp430_reg_fetch (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
89 if (0 <= regno
&& regno
< 16)
93 int val
= cpu
->state
.regs
[regno
];
95 buf
[1] = (val
>> 8) & 0xff;
100 int val
= cpu
->state
.regs
[regno
];
102 buf
[1] = (val
>> 8) & 0xff;
103 buf
[2] = (val
>> 16) & 0x0f; /* Registers are only 20 bits wide. */
115 msp430_reg_store (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
117 if (0 <= regno
&& regno
< 16)
121 cpu
->state
.regs
[regno
] = (buf
[1] << 8) | buf
[0];
127 cpu
->state
.regs
[regno
] = ((buf
[2] << 16) & 0xf0000)
128 | (buf
[1] << 8) | buf
[0];
137 msp430_initialize_cpu (SIM_DESC sd
, SIM_CPU
*cpu
)
139 memset (&cpu
->state
, 0, sizeof (cpu
->state
));
143 sim_open (SIM_OPEN_KIND kind
,
144 struct host_callback_struct
*callback
,
148 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
150 struct bfd
*prog_bfd
;
152 /* Initialise the simulator. */
154 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
160 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
166 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
172 CPU_PC_FETCH (MSP430_CPU (sd
)) = msp430_pc_fetch
;
173 CPU_PC_STORE (MSP430_CPU (sd
)) = msp430_pc_store
;
174 CPU_REG_FETCH (MSP430_CPU (sd
)) = msp430_reg_fetch
;
175 CPU_REG_STORE (MSP430_CPU (sd
)) = msp430_reg_store
;
177 /* Allocate memory if none specified by user. */
178 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x130, 1) == 0)
179 sim_do_commandf (sd
, "memory-region 0,0x20");
180 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x200, 1) == 0)
181 sim_do_commandf (sd
, "memory-region 0x200,0xffe00");
182 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0xfffe, 1) == 0)
183 sim_do_commandf (sd
, "memory-region 0xfffe,2");
184 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x10000, 1) == 0)
185 sim_do_commandf (sd
, "memory-region 0x10000,0x100000");
187 /* Check for/establish the a reference program image. */
188 if (sim_analyze_program (sd
,
189 (STATE_PROG_ARGV (sd
) != NULL
190 ? *STATE_PROG_ARGV (sd
)
191 : NULL
), abfd
) != SIM_RC_OK
)
197 prog_bfd
= sim_load_file (sd
, argv
[0], callback
,
201 1 /* use LMA instead of VMA */,
203 if (prog_bfd
== NULL
)
209 /* Establish any remaining configuration options. */
210 if (sim_config (sd
) != SIM_RC_OK
)
216 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
222 /* CPU specific initialization. */
223 assert (MAX_NR_PROCESSORS
== 1);
224 msp430_initialize_cpu (sd
, MSP430_CPU (sd
));
226 msp430_trace_init (STATE_PROG_BFD (sd
));
228 MSP430_CPU (sd
)->state
.cio_breakpoint
= lookup_symbol (sd
, "C$$IO$$");
229 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "__CIOBUF__");
230 if (MSP430_CPU (sd
)->state
.cio_buffer
== -1)
231 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "_CIOBUF_");
237 sim_close (SIM_DESC sd
,
240 free (STATE_SYMBOL_TABLE (sd
));
245 sim_create_inferior (SIM_DESC sd
,
250 unsigned char resetv
[2];
254 /* Set the PC to the default reset vector if available. */
255 c
= sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, resetv
, 0xfffe, 2);
256 new_pc
= resetv
[0] + 256 * resetv
[1];
258 /* If the reset vector isn't initialized, then use the ELF entry. */
259 if (abfd
!= NULL
&& !new_pc
)
260 new_pc
= bfd_get_start_address (abfd
);
262 sim_pc_set (MSP430_CPU (sd
), new_pc
);
263 msp430_pc_store (MSP430_CPU (sd
), new_pc
);
272 } Get_Byte_Local_Data
;
275 msp430_getbyte (void *vld
)
277 Get_Byte_Local_Data
*ld
= (Get_Byte_Local_Data
*)vld
;
279 SIM_DESC sd
= ld
->sd
;
281 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, ld
->gb_addr
, 1);
286 #define REG(N) MSP430_CPU (sd)->state.regs[(N)]
287 #define PC REG(MSR_PC)
288 #define SP REG(MSR_SP)
289 #define SR REG(MSR_SR)
294 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
295 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
299 trace_reg_put (SIM_DESC sd
, int n
, unsigned int v
)
301 if (TRACE_VPU_P (MSP430_CPU (sd
)))
302 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
303 "PUT: %#x -> %s", v
, register_names
[n
]);
308 trace_reg_get (SIM_DESC sd
, int n
)
310 if (TRACE_VPU_P (MSP430_CPU (sd
)))
311 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
312 "GET: %s -> %#x", register_names
[n
], REG (n
));
316 #define REG_PUT(N,V) trace_reg_put (sd, N, V)
317 #define REG_GET(N) trace_reg_get (sd, N)
319 /* Hardware multiply (and accumulate) support. */
320 static enum { UNSIGN_32
, SIGN_32
, UNSIGN_MAC_32
, SIGN_MAC_32
} hwmult_type
;
321 static unsigned32 hwmult_op1
;
322 static unsigned32 hwmult_op2
;
323 static unsigned32 hwmult_result
;
324 static signed32 hwmult_signed_result
;
325 static unsigned32 hwmult_accumulator
;
326 static signed32 hwmult_signed_accumulator
;
328 static enum { UNSIGN_64
, SIGN_64
} hw32mult_type
;
329 static unsigned64 hw32mult_op1
;
330 static unsigned64 hw32mult_op2
;
331 static unsigned64 hw32mult_result
;
334 zero_ext (unsigned int v
, unsigned int bits
)
336 v
&= ((1 << bits
) - 1);
341 sign_ext (signed int v
, unsigned int bits
)
343 int sb
= 1 << (bits
-1); /* Sign bit. */
344 int mb
= (1 << (bits
-1)) - 1; /* Mantissa bits. */
354 get_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
)
356 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
359 unsigned char buf
[4];
364 case MSP430_Operand_Immediate
:
367 case MSP430_Operand_Register
:
368 rv
= REG_GET (op
->reg
);
370 case MSP430_Operand_Indirect
:
371 case MSP430_Operand_Indirect_Postinc
:
373 if (op
->reg
!= MSR_None
)
376 /* Index values are signed, but the sum is limited to 16
377 bits if the register < 64k, for MSP430 compatibility in
381 reg
= REG_GET (op
->reg
);
383 if (reg
< 0x10000 && ! opc
->ofs_430x
)
390 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 1);
394 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 2);
395 rv
= buf
[0] | (buf
[1] << 8);
399 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 4);
400 rv
= buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
403 assert (! opc
->size
);
407 /* Hack - MSP430X5438 serial port status register. */
411 if (addr
>= 0x130 && addr
<= 0x15B)
416 rv
= zero_ext (hwmult_result
, 16);
423 rv
= zero_ext (hwmult_result
>> 16, 16);
427 rv
= sign_ext (hwmult_signed_result
>> 16, 16);
439 rv
= hwmult_signed_result
< 0 ? -1 : 0;
442 rv
= 0; /* FIXME: Should be carry of last accumulate. */
445 rv
= hwmult_signed_accumulator
< 0 ? -1 : 0;
451 rv
= zero_ext (hw32mult_result
, 16);
455 rv
= zero_ext (hw32mult_result
>> 16, 16);
459 rv
= zero_ext (hw32mult_result
>> 32, 16);
463 switch (hw32mult_type
)
465 case UNSIGN_64
: rv
= zero_ext (hw32mult_result
>> 48, 16); break;
466 case SIGN_64
: rv
= sign_ext (hw32mult_result
>> 48, 16); break;
471 fprintf (stderr
, "unimplemented HW MULT read!\n");
476 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
477 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
478 "GET: [%#x].%d -> %#x", addr
, opc
->size
, rv
);
481 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
505 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
506 REG_PUT (op
->reg
, REG_GET (op
->reg
) + incval
);
512 put_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
, int val
)
514 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
517 unsigned char buf
[4];
538 case MSP430_Operand_Register
:
540 REG_PUT (op
->reg
, val
);
542 case MSP430_Operand_Indirect
:
543 case MSP430_Operand_Indirect_Postinc
:
545 if (op
->reg
!= MSR_None
)
548 /* Index values are signed, but the sum is limited to 16
549 bits if the register < 64k, for MSP430 compatibility in
553 reg
= REG_GET (op
->reg
);
560 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
561 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
562 "PUT: [%#x].%d <- %#x", addr
, opc
->size
, val
);
564 /* Hack - MSP430X5438 serial port transmit register. */
568 if (addr
>= 0x130 && addr
<= 0x15B)
572 /* Hardware Multiply emulation. */
573 assert (opc
->size
== 16);
577 case 0x130: hwmult_op1
= val
; hwmult_type
= UNSIGN_32
; break;
578 case 0x132: hwmult_op1
= val
; hwmult_type
= SIGN_32
; break;
579 case 0x134: hwmult_op1
= val
; hwmult_type
= UNSIGN_MAC_32
; break;
580 case 0x136: hwmult_op1
= val
; hwmult_type
= SIGN_MAC_32
; break;
582 case 0x138: hwmult_op2
= val
;
586 hwmult_result
= hwmult_op1
* hwmult_op2
;
587 hwmult_signed_result
= (signed) hwmult_result
;
588 hwmult_accumulator
= hwmult_signed_accumulator
= 0;
592 a
= sign_ext (hwmult_op1
, 16);
593 b
= sign_ext (hwmult_op2
, 16);
594 hwmult_signed_result
= a
* b
;
595 hwmult_result
= (unsigned) hwmult_signed_result
;
596 hwmult_accumulator
= hwmult_signed_accumulator
= 0;
600 hwmult_accumulator
+= hwmult_op1
* hwmult_op2
;
601 hwmult_signed_accumulator
+= hwmult_op1
* hwmult_op2
;
602 hwmult_result
= hwmult_signed_result
= 0;
606 a
= sign_ext (hwmult_op1
, 16);
607 b
= sign_ext (hwmult_op2
, 16);
608 hwmult_accumulator
+= a
* b
;
609 hwmult_signed_accumulator
+= a
* b
;
610 hwmult_result
= hwmult_signed_result
= 0;
615 case 0x140: hw32mult_op1
= val
; hw32mult_type
= UNSIGN_64
; break;
616 case 0x142: hw32mult_op1
= (hw32mult_op1
& 0xFFFF) | (val
<< 16); break;
617 case 0x144: hw32mult_op1
= val
; hw32mult_type
= SIGN_64
; break;
618 case 0x146: hw32mult_op1
= (hw32mult_op1
& 0xFFFF) | (val
<< 16); break;
619 case 0x150: hw32mult_op2
= val
; break;
621 case 0x152: hw32mult_op2
= (hw32mult_op2
& 0xFFFF) | (val
<< 16);
622 switch (hw32mult_type
)
625 hw32mult_result
= hw32mult_op1
* hw32mult_op2
;
628 hw32mult_result
= sign_ext (hw32mult_op1
, 32) * sign_ext (hw32mult_op2
, 32);
634 fprintf (stderr
, "unimplemented HW MULT write to %x!\n", addr
);
643 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 1);
648 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 2);
656 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 4);
659 assert (! opc
->size
);
664 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
688 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
690 int new_val
= REG_GET (op
->reg
) + incval
;
691 /* SP is always word-aligned. */
692 if (op
->reg
== MSR_SP
&& (new_val
& 1))
694 REG_PUT (op
->reg
, new_val
);
701 mem_put_val (SIM_DESC sd
, int addr
, int val
, int bits
)
703 MSP430_Opcode_Decoded opc
;
706 opc
.op
[0].type
= MSP430_Operand_Indirect
;
707 opc
.op
[0].addend
= addr
;
708 opc
.op
[0].reg
= MSR_None
;
709 put_op (sd
, &opc
, 0, val
);
713 mem_get_val (SIM_DESC sd
, int addr
, int bits
)
715 MSP430_Opcode_Decoded opc
;
718 opc
.op
[0].type
= MSP430_Operand_Indirect
;
719 opc
.op
[0].addend
= addr
;
720 opc
.op
[0].reg
= MSR_None
;
721 return get_op (sd
, &opc
, 0);
724 #define CIO_OPEN (0xF0)
725 #define CIO_CLOSE (0xF1)
726 #define CIO_READ (0xF2)
727 #define CIO_WRITE (0xF3)
728 #define CIO_LSEEK (0xF4)
729 #define CIO_UNLINK (0xF5)
730 #define CIO_GETENV (0xF6)
731 #define CIO_RENAME (0xF7)
732 #define CIO_GETTIME (0xF8)
733 #define CIO_GETCLK (0xF9)
734 #define CIO_SYNC (0xFF)
736 #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
737 #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
738 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
741 msp430_cio (SIM_DESC sd
)
743 /* A block of data at __CIOBUF__ describes the I/O operation to
746 unsigned char raw_parms
[13];
747 unsigned char parms
[8];
750 unsigned char buffer
[512];
752 long fd
, addr
, len
, rv
;
754 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
755 MSP430_CPU (sd
)->state
.cio_buffer
, 5);
759 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
760 MSP430_CPU (sd
)->state
.cio_buffer
+ 3, 8);
762 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
763 MSP430_CPU (sd
)->state
.cio_buffer
+ 11, length
);
771 rv
= write (fd
, buffer
, len
);
772 parms
[0] = rv
& 0xff;
778 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
779 MSP430_CPU (sd
)->state
.cio_buffer
+ 4, 8);
781 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
782 MSP430_CPU (sd
)->state
.cio_buffer
+ 12, ret_buflen
);
785 #define SRC get_op (sd, opcode, 1)
786 #define DSRC get_op (sd, opcode, 0)
787 #define DEST(V) put_op (sd, opcode, 0, (V))
790 msp430_dis_read (bfd_vma memaddr
,
793 struct disassemble_info
*dinfo
)
795 SIM_DESC sd
= dinfo
->private_data
;
796 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, myaddr
, memaddr
, length
);
800 #define DO_ALU(OP,SOP,MORE) \
804 int result = s1 OP s2 MORE; \
805 if (TRACE_ALU_P (MSP430_CPU (sd))) \
806 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \
807 "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \
811 #define SIGN (1 << (opcode->size - 1))
812 #define POS(x) (((x) & SIGN) ? 0 : 1)
813 #define NEG(x) (((x) & SIGN) ? 1 : 0)
815 #define SX(v) sign_ext (v, opcode->size)
816 #define ZX(v) zero_ext (v, opcode->size)
821 static char buf
[2][6];
827 bp
[0] = f
& MSP430_FLAG_V
? 'V' : '-';
828 bp
[1] = f
& MSP430_FLAG_N
? 'N' : '-';
829 bp
[2] = f
& MSP430_FLAG_Z
? 'Z' : '-';
830 bp
[3] = f
& MSP430_FLAG_C
? 'C' : '-';
835 /* Random number that won't show up in our usual logic. */
836 #define MAGIC_OVERFLOW 0x55000F
839 do_flags (SIM_DESC sd
,
840 MSP430_Opcode_Decoded
*opcode
,
841 int vnz_val
, /* Signed result. */
847 int signbit
= 1 << (opcode
->size
- 1);
849 f
&= ~opcode
->flags_0
;
850 f
&= ~opcode
->flags_set
;
851 f
|= opcode
->flags_1
;
853 if (vnz_val
& signbit
)
854 new_f
|= MSP430_FLAG_N
;
855 if (! (vnz_val
& ((signbit
<< 1) - 1)))
856 new_f
|= MSP430_FLAG_Z
;
857 if (overflow
== MAGIC_OVERFLOW
)
859 if (vnz_val
!= SX (vnz_val
))
860 new_f
|= MSP430_FLAG_V
;
864 new_f
|= MSP430_FLAG_V
;
866 new_f
|= MSP430_FLAG_C
;
868 new_f
= f
| (new_f
& opcode
->flags_set
);
869 if (TRACE_ALU_P (MSP430_CPU (sd
)))
872 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
873 "FLAGS: %s -> %s", flags2string (SR
),
874 flags2string (new_f
));
876 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
877 "FLAGS: %s", flags2string (new_f
));
882 #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
883 #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
885 /* These two assume unsigned 16-bit (four digit) words.
886 Mask off unwanted bits for byte operations. */
889 bcd_to_binary (int v
)
891 int r
= ( ((v
>> 0) & 0xf) * 1
892 + ((v
>> 4) & 0xf) * 10
893 + ((v
>> 8) & 0xf) * 100
894 + ((v
>> 12) & 0xf) * 1000);
899 binary_to_bcd (int v
)
901 int r
= ( ((v
/ 1) % 10) << 0
902 | ((v
/ 10) % 10) << 4
903 | ((v
/ 100) % 10) << 8
904 | ((v
/ 1000) % 10) << 12);
909 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
910 unsigned long taddr
, char *buf
, int bytes
)
912 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
913 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
915 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
919 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
920 unsigned long taddr
, const char *buf
, int bytes
)
922 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
923 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
925 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
929 cond_string (int cond
)
954 /* Checks a CALL to address CALL_ADDR. If this is a special
955 syscall address then the call is simulated and non-zero is
956 returned. Otherwise 0 is returned. */
959 maybe_perform_syscall (SIM_DESC sd
, int call_addr
)
961 if (call_addr
== 0x00160)
965 for (i
= 0; i
< 16; i
++)
968 fprintf (stderr
, "\t");
969 fprintf (stderr
, "R%-2d %05x ", i
, MSP430_CPU (sd
)->state
.regs
[i
]);
972 int sp
= SP
+ (3 - (i
/ 4)) * 2;
973 unsigned char buf
[2];
975 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, sp
, 2);
977 fprintf (stderr
, "\tSP%+d: %04x", sp
- SP
,
978 buf
[0] + buf
[1] * 256);
984 fprintf (stderr
, flags
& 0x100 ? " V" : " -");
985 fprintf (stderr
, flags
& 0x004 ? "N" : "-");
986 fprintf (stderr
, flags
& 0x002 ? "Z" : "-");
987 fprintf (stderr
, flags
& 0x001 ? "C" : "-");
990 fprintf (stderr
, "\n");
996 if ((call_addr
& ~0x3f) == 0x00180)
999 int syscall_num
= call_addr
& 0x3f;
1000 host_callback
*cb
= STATE_CALLBACK (sd
);
1003 CB_SYSCALL_INIT (&sc
);
1005 sc
.func
= syscall_num
;
1006 sc
.arg1
= MSP430_CPU (sd
)->state
.regs
[12];
1007 sc
.arg2
= MSP430_CPU (sd
)->state
.regs
[13];
1008 sc
.arg3
= MSP430_CPU (sd
)->state
.regs
[14];
1009 sc
.arg4
= MSP430_CPU (sd
)->state
.regs
[15];
1011 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
1013 const char *syscall_name
= "*unknown*";
1015 switch (syscall_num
)
1017 case TARGET_SYS_exit
:
1018 syscall_name
= "exit(%d)";
1020 case TARGET_SYS_open
:
1021 syscall_name
= "open(%#x,%#x)";
1023 case TARGET_SYS_close
:
1024 syscall_name
= "close(%d)";
1026 case TARGET_SYS_read
:
1027 syscall_name
= "read(%d,%#x,%d)";
1029 case TARGET_SYS_write
:
1030 syscall_name
= "write(%d,%#x,%d)";
1033 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
1034 syscall_name
, sc
.arg1
, sc
.arg2
, sc
.arg3
, sc
.arg4
);
1037 /* Handle SYS_exit here. */
1038 if (syscall_num
== 1)
1040 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1041 MSP430_CPU (sd
)->state
.regs
[0],
1042 sim_exited
, sc
.arg1
);
1047 sc
.p2
= MSP430_CPU (sd
);
1048 sc
.read_mem
= syscall_read_mem
;
1049 sc
.write_mem
= syscall_write_mem
;
1051 cb_syscall (cb
, &sc
);
1053 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
1054 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
1055 "returns %ld", sc
.result
);
1057 MSP430_CPU (sd
)->state
.regs
[12] = sc
.result
;
1065 msp430_step_once (SIM_DESC sd
)
1067 Get_Byte_Local_Data ld
;
1068 unsigned char buf
[100];
1071 unsigned int opcode_pc
;
1072 MSP430_Opcode_Decoded opcode_buf
;
1073 MSP430_Opcode_Decoded
*opcode
= &opcode_buf
;
1075 int u1
, u2
, uresult
;
1081 int op_bytes
, op_bits
;
1086 if (opcode_pc
< 0x10)
1088 fprintf (stderr
, "Fault: PC(%#x) is less than 0x10\n", opcode_pc
);
1089 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1090 MSP430_CPU (sd
)->state
.regs
[0],
1095 if (PC
== MSP430_CPU (sd
)->state
.cio_breakpoint
1096 && STATE_OPEN_KIND (sd
) != SIM_OPEN_DEBUG
)
1101 opsize
= msp430_decode_opcode (MSP430_CPU (sd
)->state
.regs
[0],
1102 opcode
, msp430_getbyte
, &ld
);
1106 fprintf (stderr
, "Fault: undecodable opcode at %#x\n", opcode_pc
);
1107 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1108 MSP430_CPU (sd
)->state
.regs
[0],
1113 if (opcode
->repeat_reg
)
1114 n_repeats
= (MSP430_CPU (sd
)->state
.regs
[opcode
->repeats
] & 0x000f) + 1;
1116 n_repeats
= opcode
->repeats
+ 1;
1118 op_bits
= opcode
->size
;
1133 if (TRACE_INSN_P (MSP430_CPU (sd
)))
1135 disassemble_info info
;
1136 unsigned char b
[10];
1138 msp430_trace_one (opcode_pc
);
1140 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, b
, opcode_pc
, opsize
);
1142 init_disassemble_info (&info
, stderr
, (fprintf_ftype
) fprintf
);
1143 info
.private_data
= sd
;
1144 info
.read_memory_func
= msp430_dis_read
;
1145 fprintf (stderr
, "%#8x ", opcode_pc
);
1146 for (i
= 0; i
< opsize
; i
+= 2)
1147 fprintf (stderr
, " %02x%02x", b
[i
+1], b
[i
]);
1148 for (; i
< 6; i
+= 2)
1149 fprintf (stderr
, " ");
1150 fprintf (stderr
, " ");
1151 print_insn_msp430 (opcode_pc
, &info
);
1152 fprintf (stderr
, "\n");
1156 if (TRACE_ANY_P (MSP430_CPU (sd
)))
1157 trace_prefix (sd
, MSP430_CPU (sd
), NULL_CIA
, opcode_pc
,
1158 TRACE_LINENUM_P (MSP430_CPU (sd
)), NULL
, 0, "");
1166 /* Double-operand instructions. */
1168 if (opcode
->n_bytes
== 2
1169 && opcode
->op
[0].type
== MSP430_Operand_Register
1170 && opcode
->op
[0].reg
== MSR_CG
1171 && opcode
->op
[1].type
== MSP430_Operand_Immediate
1172 && opcode
->op
[1].addend
== 0
1173 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1174 && opcode
->size
== 8)
1176 /* This is the designated software breakpoint instruction. */
1178 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1179 MSP430_CPU (sd
)->state
.regs
[0],
1180 sim_stopped
, SIM_SIGTRAP
);
1185 /* Otherwise, do the move. */
1186 for (rept
= 0; rept
< n_repeats
; rept
++)
1194 for (rept
= 0; rept
< n_repeats
; rept
++)
1196 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1201 uresult
= u1
+ u2
+ carry_to_use
;
1202 result
= s1
+ s2
+ carry_to_use
;
1203 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1204 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1205 "ADDC: %#x + %#x + %d = %#x",
1206 u1
, u2
, carry_to_use
, uresult
);
1208 FLAGS (result
, uresult
!= ZX (uresult
));
1213 for (rept
= 0; rept
< n_repeats
; rept
++)
1221 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1222 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1223 "ADD: %#x + %#x = %#x",
1226 FLAGS (result
, uresult
!= ZX (uresult
));
1231 for (rept
= 0; rept
< n_repeats
; rept
++)
1233 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1238 uresult
= ZX (~u2
) + u1
+ carry_to_use
;
1239 result
= s1
- s2
+ (carry_to_use
- 1);
1240 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1241 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1242 "SUBC: %#x - %#x + %d = %#x",
1243 u1
, u2
, carry_to_use
, uresult
);
1245 FLAGS (result
, uresult
!= ZX (uresult
));
1250 for (rept
= 0; rept
< n_repeats
; rept
++)
1256 uresult
= ZX (~u2
) + u1
+ 1;
1257 result
= SX (uresult
);
1258 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1259 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1260 "SUB: %#x - %#x = %#x",
1263 FLAGS (result
, uresult
!= ZX (uresult
));
1268 for (rept
= 0; rept
< n_repeats
; rept
++)
1274 uresult
= ZX (~u2
) + u1
+ 1;
1276 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1277 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1278 "CMP: %#x - %#x = %x",
1280 FLAGS (result
, uresult
!= ZX (uresult
));
1285 for (rept
= 0; rept
< n_repeats
; rept
++)
1287 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1290 uresult
= bcd_to_binary (u1
) + bcd_to_binary (u2
) + carry_to_use
;
1291 result
= binary_to_bcd (uresult
);
1292 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1293 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1294 "DADD: %#x + %#x + %d = %#x",
1295 u1
, u2
, carry_to_use
, result
);
1297 FLAGS (result
, uresult
> ((opcode
->size
== 8) ? 99 : 9999));
1302 for (rept
= 0; rept
< n_repeats
; rept
++)
1307 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1308 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1309 "AND: %#x & %#x = %#x",
1312 FLAGS (uresult
, uresult
!= 0);
1317 for (rept
= 0; rept
< n_repeats
; rept
++)
1322 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1323 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1324 "BIT: %#x & %#x -> %#x",
1326 FLAGS (uresult
, uresult
!= 0);
1331 for (rept
= 0; rept
< n_repeats
; rept
++)
1335 uresult
= u1
& ~ u2
;
1336 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1337 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1338 "BIC: %#x & ~ %#x = %#x",
1345 for (rept
= 0; rept
< n_repeats
; rept
++)
1350 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1351 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1352 "BIS: %#x | %#x = %#x",
1359 for (rept
= 0; rept
< n_repeats
; rept
++)
1361 s1
= 1 << (opcode
->size
- 1);
1365 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1366 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1367 "XOR: %#x & %#x = %#x",
1370 FLAGSV (uresult
, uresult
!= 0, (u1
& s1
) && (u2
& s1
));
1374 /* Single-operand instructions. Note: the decoder puts the same
1375 operand in SRC as in DEST, for our convenience. */
1378 for (rept
= 0; rept
< n_repeats
; rept
++)
1381 carry_to_use
= u1
& 1;
1383 if (SR
& MSP430_FLAG_C
)
1384 uresult
|= (1 << (opcode
->size
- 1));
1385 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1386 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1390 FLAGS (uresult
, carry_to_use
);
1395 for (rept
= 0; rept
< n_repeats
; rept
++)
1398 uresult
= ((u1
>> 8) & 0x00ff) | ((u1
<< 8) & 0xff00);
1399 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1400 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1408 for (rept
= 0; rept
< n_repeats
; rept
++)
1412 s1
= 1 << (opcode
->size
- 1);
1413 uresult
= (u1
>> 1) | (u1
& s1
);
1414 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1415 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1424 for (rept
= 0; rept
< n_repeats
; rept
++)
1428 uresult
= (u1
>> 1);
1429 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1430 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1439 for (rept
= 0; rept
< n_repeats
; rept
++)
1443 uresult
= u1
| 0xfff00;
1445 uresult
= u1
& 0x000ff;
1446 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1447 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1456 for (rept
= 0; rept
< n_repeats
; rept
++)
1460 new_sp
= REG_GET (MSR_SP
) - op_bytes
;
1461 /* SP is always word-aligned. */
1464 REG_PUT (MSR_SP
, new_sp
);
1466 mem_put_val (sd
, SP
, u1
, op_bits
);
1467 if (opcode
->op
[1].type
== MSP430_Operand_Register
)
1468 opcode
->op
[1].reg
--;
1473 for (rept
= 0; rept
< n_repeats
; rept
++)
1477 u1
= mem_get_val (sd
, SP
, op_bits
);
1479 if (opcode
->op
[0].type
== MSP430_Operand_Register
)
1480 opcode
->op
[0].reg
++;
1481 new_sp
= REG_GET (MSR_SP
) + op_bytes
;
1482 /* SP is always word-aligned. */
1485 REG_PUT (MSR_SP
, new_sp
);
1492 if (maybe_perform_syscall (sd
, u1
))
1495 REG_PUT (MSR_SP
, REG_GET (MSR_SP
) - op_bytes
);
1496 mem_put_val (sd
, SP
, PC
, op_bits
);
1497 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1498 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1499 "CALL: func %#x ret %#x, sp %#x",
1501 REG_PUT (MSR_PC
, u1
);
1505 u1
= mem_get_val (sd
, SP
, 16);
1508 PC
= mem_get_val (sd
, SP
, 16);
1510 /* Emulate the RETI action of the 20-bit CPUX architecure.
1511 This is safe for 16-bit CPU architectures as well, since the top
1512 8-bits of SR will have been written to the stack here, and will
1513 have been read as 0. */
1514 PC
|= (u1
& 0xF000) << 4;
1515 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1516 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1517 "RETI: pc %#x sr %#x",
1525 switch (opcode
->cond
)
1528 u1
= (SR
& MSP430_FLAG_Z
) ? 0 : 1;
1531 u1
= (SR
& MSP430_FLAG_Z
) ? 1 : 0;
1534 u1
= (SR
& MSP430_FLAG_C
) ? 0 : 1;
1537 u1
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1540 u1
= (SR
& MSP430_FLAG_N
) ? 1 : 0;
1543 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 1 : 0;
1546 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 0 : 1;
1555 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1556 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1557 "J%s: pc %#x -> %#x sr %#x, taken",
1558 cond_string (opcode
->cond
), PC
, i
, SR
);
1560 if (PC
== opcode_pc
)
1564 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1565 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1566 "J%s: pc %#x to %#x sr %#x, not taken",
1567 cond_string (opcode
->cond
), PC
, i
, SR
);
1571 fprintf (stderr
, "error: unexpected opcode id %d\n", opcode
->id
);
1577 sim_engine_run (SIM_DESC sd
,
1584 msp430_step_once (sd
);
1585 if (sim_events_tick (sd
))
1586 sim_events_process (sd
);