1 /* Simulator for TI MSP430 and MSP430X
3 Copyright (C) 2013-2015 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "opcode/msp430-decode.h"
32 #include "targ-vals.h"
35 loader_write_mem (SIM_DESC sd
,
37 const unsigned char *buf
,
40 SIM_CPU
*cpu
= MSP430_CPU (sd
);
41 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
45 msp430_pc_fetch (SIM_CPU
*cpu
)
47 return cpu
->state
.regs
[0];
51 msp430_pc_store (SIM_CPU
*cpu
, sim_cia newpc
)
53 cpu
->state
.regs
[0] = newpc
;
57 lookup_symbol (SIM_DESC sd
, const char *name
)
59 struct bfd
*abfd
= STATE_PROG_BFD (sd
);
60 asymbol
**symbol_table
= STATE_SYMBOL_TABLE (sd
);
61 long number_of_symbols
= STATE_NUM_SYMBOLS (sd
);
64 if (symbol_table
== NULL
)
68 storage_needed
= bfd_get_symtab_upper_bound (abfd
);
69 if (storage_needed
<= 0)
72 STATE_SYMBOL_TABLE (sd
) = symbol_table
= xmalloc (storage_needed
);
73 STATE_NUM_SYMBOLS (sd
) = number_of_symbols
=
74 bfd_canonicalize_symtab (abfd
, symbol_table
);
77 for (i
= 0; i
< number_of_symbols
; i
++)
78 if (strcmp (symbol_table
[i
]->name
, name
) == 0)
80 long val
= symbol_table
[i
]->section
->vma
+ symbol_table
[i
]->value
;
87 msp430_reg_fetch (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
89 if (0 <= regno
&& regno
< 16)
93 int val
= cpu
->state
.regs
[regno
];
95 buf
[1] = (val
>> 8) & 0xff;
100 int val
= cpu
->state
.regs
[regno
];
102 buf
[1] = (val
>> 8) & 0xff;
103 buf
[2] = (val
>> 16) & 0x0f; /* Registers are only 20 bits wide. */
115 msp430_reg_store (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
117 if (0 <= regno
&& regno
< 16)
121 cpu
->state
.regs
[regno
] = (buf
[1] << 8) | buf
[0];
127 cpu
->state
.regs
[regno
] = ((buf
[2] << 16) & 0xf0000)
128 | (buf
[1] << 8) | buf
[0];
137 msp430_initialize_cpu (SIM_DESC sd
, SIM_CPU
*cpu
)
139 memset (&cpu
->state
, 0, sizeof (cpu
->state
));
143 sim_open (SIM_OPEN_KIND kind
,
144 struct host_callback_struct
*callback
,
148 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
150 struct bfd
*prog_bfd
;
152 /* Initialise the simulator. */
154 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
160 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
166 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
172 CPU_PC_FETCH (MSP430_CPU (sd
)) = msp430_pc_fetch
;
173 CPU_PC_STORE (MSP430_CPU (sd
)) = msp430_pc_store
;
174 CPU_REG_FETCH (MSP430_CPU (sd
)) = msp430_reg_fetch
;
175 CPU_REG_STORE (MSP430_CPU (sd
)) = msp430_reg_store
;
177 /* Allocate memory if none specified by user. */
178 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x130, 1) == 0)
179 sim_do_commandf (sd
, "memory-region 0,0x20");
180 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x200, 1) == 0)
181 sim_do_commandf (sd
, "memory-region 0x200,0xffe00");
182 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0xfffe, 1) == 0)
183 sim_do_commandf (sd
, "memory-region 0xfffe,2");
184 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x10000, 1) == 0)
185 sim_do_commandf (sd
, "memory-region 0x10000,0x100000");
187 /* Check for/establish the a reference program image. */
188 if (sim_analyze_program (sd
,
189 (STATE_PROG_ARGV (sd
) != NULL
190 ? *STATE_PROG_ARGV (sd
)
191 : NULL
), abfd
) != SIM_RC_OK
)
197 prog_bfd
= sim_load_file (sd
, argv
[0], callback
,
201 1 /* use LMA instead of VMA */,
203 if (prog_bfd
== NULL
)
209 /* Establish any remaining configuration options. */
210 if (sim_config (sd
) != SIM_RC_OK
)
216 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
222 /* CPU specific initialization. */
223 assert (MAX_NR_PROCESSORS
== 1);
224 msp430_initialize_cpu (sd
, MSP430_CPU (sd
));
226 msp430_trace_init (STATE_PROG_BFD (sd
));
228 MSP430_CPU (sd
)->state
.cio_breakpoint
= lookup_symbol (sd
, "C$$IO$$");
229 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "__CIOBUF__");
230 if (MSP430_CPU (sd
)->state
.cio_buffer
== -1)
231 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "_CIOBUF_");
237 sim_close (SIM_DESC sd
,
240 free (STATE_SYMBOL_TABLE (sd
));
245 sim_create_inferior (SIM_DESC sd
,
250 unsigned char resetv
[2];
254 /* Set the PC to the default reset vector if available. */
255 c
= sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, resetv
, 0xfffe, 2);
256 new_pc
= resetv
[0] + 256 * resetv
[1];
258 /* If the reset vector isn't initialized, then use the ELF entry. */
259 if (abfd
!= NULL
&& !new_pc
)
260 new_pc
= bfd_get_start_address (abfd
);
262 sim_pc_set (MSP430_CPU (sd
), new_pc
);
263 msp430_pc_store (MSP430_CPU (sd
), new_pc
);
272 } Get_Byte_Local_Data
;
275 msp430_getbyte (void *vld
)
277 Get_Byte_Local_Data
*ld
= (Get_Byte_Local_Data
*)vld
;
279 SIM_DESC sd
= ld
->sd
;
281 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, ld
->gb_addr
, 1);
286 #define REG(N) MSP430_CPU (sd)->state.regs[(N)]
287 #define PC REG(MSR_PC)
288 #define SP REG(MSR_SP)
289 #define SR REG(MSR_SR)
294 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
295 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
299 trace_reg_put (SIM_DESC sd
, int n
, unsigned int v
)
301 if (TRACE_VPU_P (MSP430_CPU (sd
)))
302 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
303 "PUT: %#x -> %s", v
, register_names
[n
]);
308 trace_reg_get (SIM_DESC sd
, int n
)
310 if (TRACE_VPU_P (MSP430_CPU (sd
)))
311 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
312 "GET: %s -> %#x", register_names
[n
], REG (n
));
316 #define REG_PUT(N,V) trace_reg_put (sd, N, V)
317 #define REG_GET(N) trace_reg_get (sd, N)
319 /* Hardware multiply (and accumulate) support. */
322 zero_ext (unsigned int v
, unsigned int bits
)
324 v
&= ((1 << bits
) - 1);
328 static signed long long
329 sign_ext (signed long long v
, unsigned int bits
)
331 signed long long sb
= 1LL << (bits
-1); /* Sign bit. */
332 signed long long mb
= (1LL << (bits
-1)) - 1LL; /* Mantissa bits. */
342 get_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
)
344 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
347 unsigned char buf
[4];
352 case MSP430_Operand_Immediate
:
355 case MSP430_Operand_Register
:
356 rv
= REG_GET (op
->reg
);
358 case MSP430_Operand_Indirect
:
359 case MSP430_Operand_Indirect_Postinc
:
361 if (op
->reg
!= MSR_None
)
364 /* Index values are signed, but the sum is limited to 16
365 bits if the register < 64k, for MSP430 compatibility in
369 reg
= REG_GET (op
->reg
);
371 if (reg
< 0x10000 && ! opc
->ofs_430x
)
378 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 1);
382 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 2);
383 rv
= buf
[0] | (buf
[1] << 8);
387 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 4);
388 rv
= buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
391 assert (! opc
->size
);
395 /* Hack - MSP430X5438 serial port status register. */
399 if (addr
>= 0x130 && addr
<= 0x15B)
404 switch (HWMULT (sd
, hwmult_type
))
408 rv
= zero_ext (HWMULT (sd
, hwmult_result
), 16);
412 rv
= sign_ext (HWMULT (sd
, hwmult_signed_result
), 16);
418 switch (HWMULT (sd
, hwmult_type
))
422 rv
= zero_ext (HWMULT (sd
, hwmult_result
) >> 16, 16);
427 rv
= sign_ext (HWMULT (sd
, hwmult_signed_result
) >> 16, 16);
433 switch (HWMULT (sd
, hwmult_type
))
439 rv
= HWMULT (sd
, hwmult_signed_result
) < 0 ? -1 : 0;
442 rv
= 0; /* FIXME: Should be carry of last accumulate. */
445 rv
= HWMULT (sd
, hwmult_signed_accumulator
) < 0 ? -1 : 0;
451 rv
= zero_ext (HWMULT (sd
, hw32mult_result
), 16);
455 rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 16, 16);
459 rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 32, 16);
463 switch (HWMULT (sd
, hw32mult_type
))
465 case UNSIGN_64
: rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 48, 16); break;
466 case SIGN_64
: rv
= sign_ext (HWMULT (sd
, hw32mult_result
) >> 48, 16); break;
471 fprintf (stderr
, "unimplemented HW MULT read!\n");
476 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
477 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
478 "GET: [%#x].%d -> %#x", addr
, opc
->size
, rv
);
481 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
505 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
506 REG_PUT (op
->reg
, REG_GET (op
->reg
) + incval
);
512 put_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
, int val
)
514 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
517 unsigned char buf
[4];
538 case MSP430_Operand_Register
:
540 REG_PUT (op
->reg
, val
);
542 case MSP430_Operand_Indirect
:
543 case MSP430_Operand_Indirect_Postinc
:
545 if (op
->reg
!= MSR_None
)
548 /* Index values are signed, but the sum is limited to 16
549 bits if the register < 64k, for MSP430 compatibility in
553 reg
= REG_GET (op
->reg
);
560 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
561 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
562 "PUT: [%#x].%d <- %#x", addr
, opc
->size
, val
);
564 /* Hack - MSP430X5438 serial port transmit register. */
568 if (addr
>= 0x130 && addr
<= 0x15B)
572 /* Hardware Multiply emulation. */
573 assert (opc
->size
== 16);
577 case 0x130: HWMULT (sd
, hwmult_op1
) = val
; HWMULT (sd
, hwmult_type
) = UNSIGN_32
; break;
578 case 0x132: HWMULT (sd
, hwmult_op1
) = val
; HWMULT (sd
, hwmult_type
) = SIGN_32
; break;
579 case 0x134: HWMULT (sd
, hwmult_op1
) = val
; HWMULT (sd
, hwmult_type
) = UNSIGN_MAC_32
; break;
580 case 0x136: HWMULT (sd
, hwmult_op1
) = val
; HWMULT (sd
, hwmult_type
) = SIGN_MAC_32
; break;
582 case 0x138: HWMULT (sd
, hwmult_op2
) = val
;
583 switch (HWMULT (sd
, hwmult_type
))
586 HWMULT (sd
, hwmult_result
) = HWMULT (sd
, hwmult_op1
) * HWMULT (sd
, hwmult_op2
);
587 HWMULT (sd
, hwmult_signed_result
) = (signed) HWMULT (sd
, hwmult_result
);
588 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_signed_accumulator
) = 0;
592 a
= sign_ext (HWMULT (sd
, hwmult_op1
), 16);
593 b
= sign_ext (HWMULT (sd
, hwmult_op2
), 16);
594 HWMULT (sd
, hwmult_signed_result
) = a
* b
;
595 HWMULT (sd
, hwmult_result
) = (unsigned) HWMULT (sd
, hwmult_signed_result
);
596 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_signed_accumulator
) = 0;
600 HWMULT (sd
, hwmult_accumulator
) += HWMULT (sd
, hwmult_op1
) * HWMULT (sd
, hwmult_op2
);
601 HWMULT (sd
, hwmult_signed_accumulator
) += HWMULT (sd
, hwmult_op1
) * HWMULT (sd
, hwmult_op2
);
602 HWMULT (sd
, hwmult_result
) = HWMULT (sd
, hwmult_accumulator
);
603 HWMULT (sd
, hwmult_signed_result
) = HWMULT (sd
, hwmult_signed_accumulator
);
607 a
= sign_ext (HWMULT (sd
, hwmult_op1
), 16);
608 b
= sign_ext (HWMULT (sd
, hwmult_op2
), 16);
609 HWMULT (sd
, hwmult_accumulator
) += a
* b
;
610 HWMULT (sd
, hwmult_signed_accumulator
) += a
* b
;
611 HWMULT (sd
, hwmult_result
) = HWMULT (sd
, hwmult_accumulator
);
612 HWMULT (sd
, hwmult_signed_result
) = HWMULT (sd
, hwmult_signed_accumulator
);
618 /* Copy into LOW result... */
619 switch (HWMULT (sd
, hwmult_type
))
623 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_result
) = zero_ext (val
, 16);
624 HWMULT (sd
, hwmult_signed_accumulator
) = sign_ext (val
, 16);
628 HWMULT (sd
, hwmult_signed_accumulator
) = HWMULT (sd
, hwmult_result
) = sign_ext (val
, 16);
629 HWMULT (sd
, hwmult_accumulator
) = zero_ext (val
, 16);
635 HWMULT (sd
, hw32mult_op1
) = val
;
636 HWMULT (sd
, hw32mult_type
) = UNSIGN_64
;
639 HWMULT (sd
, hw32mult_op1
) = (HWMULT (sd
, hw32mult_op1
) & 0xFFFF) | (val
<< 16);
642 HWMULT (sd
, hw32mult_op1
) = val
;
643 HWMULT (sd
, hw32mult_type
) = SIGN_64
;
646 HWMULT (sd
, hw32mult_op1
) = (HWMULT (sd
, hw32mult_op1
) & 0xFFFF) | (val
<< 16);
649 HWMULT (sd
, hw32mult_op2
) = val
;
653 HWMULT (sd
, hw32mult_op2
) = (HWMULT (sd
, hw32mult_op2
) & 0xFFFF) | (val
<< 16);
654 switch (HWMULT (sd
, hw32mult_type
))
657 HWMULT (sd
, hw32mult_result
) = HWMULT (sd
, hw32mult_op1
) * HWMULT (sd
, hw32mult_op2
);
660 HWMULT (sd
, hw32mult_result
) = sign_ext (HWMULT (sd
, hw32mult_op1
), 32)
661 * sign_ext (HWMULT (sd
, hw32mult_op2
), 32);
667 fprintf (stderr
, "unimplemented HW MULT write to %x!\n", addr
);
676 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 1);
681 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 2);
689 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 4);
692 assert (! opc
->size
);
697 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
721 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
723 int new_val
= REG_GET (op
->reg
) + incval
;
724 /* SP is always word-aligned. */
725 if (op
->reg
== MSR_SP
&& (new_val
& 1))
727 REG_PUT (op
->reg
, new_val
);
734 mem_put_val (SIM_DESC sd
, int addr
, int val
, int bits
)
736 MSP430_Opcode_Decoded opc
;
739 opc
.op
[0].type
= MSP430_Operand_Indirect
;
740 opc
.op
[0].addend
= addr
;
741 opc
.op
[0].reg
= MSR_None
;
742 put_op (sd
, &opc
, 0, val
);
746 mem_get_val (SIM_DESC sd
, int addr
, int bits
)
748 MSP430_Opcode_Decoded opc
;
751 opc
.op
[0].type
= MSP430_Operand_Indirect
;
752 opc
.op
[0].addend
= addr
;
753 opc
.op
[0].reg
= MSR_None
;
754 return get_op (sd
, &opc
, 0);
757 #define CIO_OPEN (0xF0)
758 #define CIO_CLOSE (0xF1)
759 #define CIO_READ (0xF2)
760 #define CIO_WRITE (0xF3)
761 #define CIO_LSEEK (0xF4)
762 #define CIO_UNLINK (0xF5)
763 #define CIO_GETENV (0xF6)
764 #define CIO_RENAME (0xF7)
765 #define CIO_GETTIME (0xF8)
766 #define CIO_GETCLK (0xF9)
767 #define CIO_SYNC (0xFF)
769 #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
770 #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
771 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
774 msp430_cio (SIM_DESC sd
)
776 /* A block of data at __CIOBUF__ describes the I/O operation to
779 unsigned char raw_parms
[13];
780 unsigned char parms
[8];
783 unsigned char buffer
[512];
785 long fd
, addr
, len
, rv
;
787 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
788 MSP430_CPU (sd
)->state
.cio_buffer
, 5);
792 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
793 MSP430_CPU (sd
)->state
.cio_buffer
+ 3, 8);
795 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
796 MSP430_CPU (sd
)->state
.cio_buffer
+ 11, length
);
804 rv
= write (fd
, buffer
, len
);
805 parms
[0] = rv
& 0xff;
811 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
812 MSP430_CPU (sd
)->state
.cio_buffer
+ 4, 8);
814 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
815 MSP430_CPU (sd
)->state
.cio_buffer
+ 12, ret_buflen
);
818 #define SRC get_op (sd, opcode, 1)
819 #define DSRC get_op (sd, opcode, 0)
820 #define DEST(V) put_op (sd, opcode, 0, (V))
823 msp430_dis_read (bfd_vma memaddr
,
826 struct disassemble_info
*dinfo
)
828 SIM_DESC sd
= dinfo
->private_data
;
829 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, myaddr
, memaddr
, length
);
833 #define DO_ALU(OP,SOP,MORE) \
837 int result = s1 OP s2 MORE; \
838 if (TRACE_ALU_P (MSP430_CPU (sd))) \
839 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \
840 "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \
844 #define SIGN (1 << (opcode->size - 1))
845 #define POS(x) (((x) & SIGN) ? 0 : 1)
846 #define NEG(x) (((x) & SIGN) ? 1 : 0)
848 #define SX(v) sign_ext (v, opcode->size)
849 #define ZX(v) zero_ext (v, opcode->size)
854 static char buf
[2][6];
860 bp
[0] = f
& MSP430_FLAG_V
? 'V' : '-';
861 bp
[1] = f
& MSP430_FLAG_N
? 'N' : '-';
862 bp
[2] = f
& MSP430_FLAG_Z
? 'Z' : '-';
863 bp
[3] = f
& MSP430_FLAG_C
? 'C' : '-';
868 /* Random number that won't show up in our usual logic. */
869 #define MAGIC_OVERFLOW 0x55000F
872 do_flags (SIM_DESC sd
,
873 MSP430_Opcode_Decoded
*opcode
,
874 int vnz_val
, /* Signed result. */
880 int signbit
= 1 << (opcode
->size
- 1);
882 f
&= ~opcode
->flags_0
;
883 f
&= ~opcode
->flags_set
;
884 f
|= opcode
->flags_1
;
886 if (vnz_val
& signbit
)
887 new_f
|= MSP430_FLAG_N
;
888 if (! (vnz_val
& ((signbit
<< 1) - 1)))
889 new_f
|= MSP430_FLAG_Z
;
890 if (overflow
== MAGIC_OVERFLOW
)
892 if (vnz_val
!= SX (vnz_val
))
893 new_f
|= MSP430_FLAG_V
;
897 new_f
|= MSP430_FLAG_V
;
899 new_f
|= MSP430_FLAG_C
;
901 new_f
= f
| (new_f
& opcode
->flags_set
);
902 if (TRACE_ALU_P (MSP430_CPU (sd
)))
905 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
906 "FLAGS: %s -> %s", flags2string (SR
),
907 flags2string (new_f
));
909 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
910 "FLAGS: %s", flags2string (new_f
));
915 #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
916 #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
918 /* These two assume unsigned 16-bit (four digit) words.
919 Mask off unwanted bits for byte operations. */
922 bcd_to_binary (int v
)
924 int r
= ( ((v
>> 0) & 0xf) * 1
925 + ((v
>> 4) & 0xf) * 10
926 + ((v
>> 8) & 0xf) * 100
927 + ((v
>> 12) & 0xf) * 1000);
932 binary_to_bcd (int v
)
934 int r
= ( ((v
/ 1) % 10) << 0
935 | ((v
/ 10) % 10) << 4
936 | ((v
/ 100) % 10) << 8
937 | ((v
/ 1000) % 10) << 12);
942 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
943 unsigned long taddr
, char *buf
, int bytes
)
945 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
946 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
948 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
952 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
953 unsigned long taddr
, const char *buf
, int bytes
)
955 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
956 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
958 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
962 cond_string (int cond
)
987 /* Checks a CALL to address CALL_ADDR. If this is a special
988 syscall address then the call is simulated and non-zero is
989 returned. Otherwise 0 is returned. */
992 maybe_perform_syscall (SIM_DESC sd
, int call_addr
)
994 if (call_addr
== 0x00160)
998 for (i
= 0; i
< 16; i
++)
1001 fprintf (stderr
, "\t");
1002 fprintf (stderr
, "R%-2d %05x ", i
, MSP430_CPU (sd
)->state
.regs
[i
]);
1005 int sp
= SP
+ (3 - (i
/ 4)) * 2;
1006 unsigned char buf
[2];
1008 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, sp
, 2);
1010 fprintf (stderr
, "\tSP%+d: %04x", sp
- SP
,
1011 buf
[0] + buf
[1] * 256);
1017 fprintf (stderr
, flags
& 0x100 ? " V" : " -");
1018 fprintf (stderr
, flags
& 0x004 ? "N" : "-");
1019 fprintf (stderr
, flags
& 0x002 ? "Z" : "-");
1020 fprintf (stderr
, flags
& 0x001 ? "C" : "-");
1023 fprintf (stderr
, "\n");
1029 if ((call_addr
& ~0x3f) == 0x00180)
1032 int syscall_num
= call_addr
& 0x3f;
1033 host_callback
*cb
= STATE_CALLBACK (sd
);
1036 CB_SYSCALL_INIT (&sc
);
1038 sc
.func
= syscall_num
;
1039 sc
.arg1
= MSP430_CPU (sd
)->state
.regs
[12];
1040 sc
.arg2
= MSP430_CPU (sd
)->state
.regs
[13];
1041 sc
.arg3
= MSP430_CPU (sd
)->state
.regs
[14];
1042 sc
.arg4
= MSP430_CPU (sd
)->state
.regs
[15];
1044 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
1046 const char *syscall_name
= "*unknown*";
1048 switch (syscall_num
)
1050 case TARGET_SYS_exit
:
1051 syscall_name
= "exit(%d)";
1053 case TARGET_SYS_open
:
1054 syscall_name
= "open(%#x,%#x)";
1056 case TARGET_SYS_close
:
1057 syscall_name
= "close(%d)";
1059 case TARGET_SYS_read
:
1060 syscall_name
= "read(%d,%#x,%d)";
1062 case TARGET_SYS_write
:
1063 syscall_name
= "write(%d,%#x,%d)";
1066 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
1067 syscall_name
, sc
.arg1
, sc
.arg2
, sc
.arg3
, sc
.arg4
);
1070 /* Handle SYS_exit here. */
1071 if (syscall_num
== 1)
1073 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1074 MSP430_CPU (sd
)->state
.regs
[0],
1075 sim_exited
, sc
.arg1
);
1080 sc
.p2
= MSP430_CPU (sd
);
1081 sc
.read_mem
= syscall_read_mem
;
1082 sc
.write_mem
= syscall_write_mem
;
1084 cb_syscall (cb
, &sc
);
1086 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
1087 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
1088 "returns %ld", sc
.result
);
1090 MSP430_CPU (sd
)->state
.regs
[12] = sc
.result
;
1098 msp430_step_once (SIM_DESC sd
)
1100 Get_Byte_Local_Data ld
;
1101 unsigned char buf
[100];
1104 unsigned int opcode_pc
;
1105 MSP430_Opcode_Decoded opcode_buf
;
1106 MSP430_Opcode_Decoded
*opcode
= &opcode_buf
;
1108 int u1
, u2
, uresult
;
1114 int op_bytes
, op_bits
;
1119 if (opcode_pc
< 0x10)
1121 fprintf (stderr
, "Fault: PC(%#x) is less than 0x10\n", opcode_pc
);
1122 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1123 MSP430_CPU (sd
)->state
.regs
[0],
1128 if (PC
== MSP430_CPU (sd
)->state
.cio_breakpoint
1129 && STATE_OPEN_KIND (sd
) != SIM_OPEN_DEBUG
)
1134 opsize
= msp430_decode_opcode (MSP430_CPU (sd
)->state
.regs
[0],
1135 opcode
, msp430_getbyte
, &ld
);
1139 fprintf (stderr
, "Fault: undecodable opcode at %#x\n", opcode_pc
);
1140 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1141 MSP430_CPU (sd
)->state
.regs
[0],
1146 if (opcode
->repeat_reg
)
1147 n_repeats
= (MSP430_CPU (sd
)->state
.regs
[opcode
->repeats
] & 0x000f) + 1;
1149 n_repeats
= opcode
->repeats
+ 1;
1151 op_bits
= opcode
->size
;
1166 if (TRACE_INSN_P (MSP430_CPU (sd
)))
1168 disassemble_info info
;
1169 unsigned char b
[10];
1171 msp430_trace_one (opcode_pc
);
1173 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, b
, opcode_pc
, opsize
);
1175 init_disassemble_info (&info
, stderr
, (fprintf_ftype
) fprintf
);
1176 info
.private_data
= sd
;
1177 info
.read_memory_func
= msp430_dis_read
;
1178 fprintf (stderr
, "%#8x ", opcode_pc
);
1179 for (i
= 0; i
< opsize
; i
+= 2)
1180 fprintf (stderr
, " %02x%02x", b
[i
+1], b
[i
]);
1181 for (; i
< 6; i
+= 2)
1182 fprintf (stderr
, " ");
1183 fprintf (stderr
, " ");
1184 print_insn_msp430 (opcode_pc
, &info
);
1185 fprintf (stderr
, "\n");
1189 if (TRACE_ANY_P (MSP430_CPU (sd
)))
1190 trace_prefix (sd
, MSP430_CPU (sd
), NULL_CIA
, opcode_pc
,
1191 TRACE_LINENUM_P (MSP430_CPU (sd
)), NULL
, 0, "");
1199 /* Double-operand instructions. */
1201 if (opcode
->n_bytes
== 2
1202 && opcode
->op
[0].type
== MSP430_Operand_Register
1203 && opcode
->op
[0].reg
== MSR_CG
1204 && opcode
->op
[1].type
== MSP430_Operand_Immediate
1205 && opcode
->op
[1].addend
== 0
1206 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1207 && opcode
->size
== 8)
1209 /* This is the designated software breakpoint instruction. */
1211 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1212 MSP430_CPU (sd
)->state
.regs
[0],
1213 sim_stopped
, SIM_SIGTRAP
);
1218 /* Otherwise, do the move. */
1219 for (rept
= 0; rept
< n_repeats
; rept
++)
1227 for (rept
= 0; rept
< n_repeats
; rept
++)
1229 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1234 uresult
= u1
+ u2
+ carry_to_use
;
1235 result
= s1
+ s2
+ carry_to_use
;
1236 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1237 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1238 "ADDC: %#x + %#x + %d = %#x",
1239 u1
, u2
, carry_to_use
, uresult
);
1241 FLAGS (result
, uresult
!= ZX (uresult
));
1246 for (rept
= 0; rept
< n_repeats
; rept
++)
1254 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1255 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1256 "ADD: %#x + %#x = %#x",
1259 FLAGS (result
, uresult
!= ZX (uresult
));
1264 for (rept
= 0; rept
< n_repeats
; rept
++)
1266 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1271 uresult
= ZX (~u2
) + u1
+ carry_to_use
;
1272 result
= s1
- s2
+ (carry_to_use
- 1);
1273 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1274 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1275 "SUBC: %#x - %#x + %d = %#x",
1276 u1
, u2
, carry_to_use
, uresult
);
1278 FLAGS (result
, uresult
!= ZX (uresult
));
1283 for (rept
= 0; rept
< n_repeats
; rept
++)
1289 uresult
= ZX (~u2
) + u1
+ 1;
1290 result
= SX (uresult
);
1291 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1292 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1293 "SUB: %#x - %#x = %#x",
1296 FLAGS (result
, uresult
!= ZX (uresult
));
1301 for (rept
= 0; rept
< n_repeats
; rept
++)
1307 uresult
= ZX (~u2
) + u1
+ 1;
1309 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1310 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1311 "CMP: %#x - %#x = %x",
1313 FLAGS (result
, uresult
!= ZX (uresult
));
1318 for (rept
= 0; rept
< n_repeats
; rept
++)
1320 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1323 uresult
= bcd_to_binary (u1
) + bcd_to_binary (u2
) + carry_to_use
;
1324 result
= binary_to_bcd (uresult
);
1325 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1326 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1327 "DADD: %#x + %#x + %d = %#x",
1328 u1
, u2
, carry_to_use
, result
);
1330 FLAGS (result
, uresult
> ((opcode
->size
== 8) ? 99 : 9999));
1335 for (rept
= 0; rept
< n_repeats
; rept
++)
1340 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1341 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1342 "AND: %#x & %#x = %#x",
1345 FLAGS (uresult
, uresult
!= 0);
1350 for (rept
= 0; rept
< n_repeats
; rept
++)
1355 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1356 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1357 "BIT: %#x & %#x -> %#x",
1359 FLAGS (uresult
, uresult
!= 0);
1364 for (rept
= 0; rept
< n_repeats
; rept
++)
1368 uresult
= u1
& ~ u2
;
1369 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1370 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1371 "BIC: %#x & ~ %#x = %#x",
1378 for (rept
= 0; rept
< n_repeats
; rept
++)
1383 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1384 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1385 "BIS: %#x | %#x = %#x",
1392 for (rept
= 0; rept
< n_repeats
; rept
++)
1394 s1
= 1 << (opcode
->size
- 1);
1398 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1399 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1400 "XOR: %#x & %#x = %#x",
1403 FLAGSV (uresult
, uresult
!= 0, (u1
& s1
) && (u2
& s1
));
1407 /* Single-operand instructions. Note: the decoder puts the same
1408 operand in SRC as in DEST, for our convenience. */
1411 for (rept
= 0; rept
< n_repeats
; rept
++)
1414 carry_to_use
= u1
& 1;
1416 if (SR
& MSP430_FLAG_C
)
1417 uresult
|= (1 << (opcode
->size
- 1));
1418 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1419 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1423 FLAGS (uresult
, carry_to_use
);
1428 for (rept
= 0; rept
< n_repeats
; rept
++)
1431 uresult
= ((u1
>> 8) & 0x00ff) | ((u1
<< 8) & 0xff00);
1432 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1433 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1441 for (rept
= 0; rept
< n_repeats
; rept
++)
1445 s1
= 1 << (opcode
->size
- 1);
1446 uresult
= (u1
>> 1) | (u1
& s1
);
1447 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1448 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1457 for (rept
= 0; rept
< n_repeats
; rept
++)
1461 uresult
= (u1
>> 1);
1462 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1463 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1472 for (rept
= 0; rept
< n_repeats
; rept
++)
1476 uresult
= u1
| 0xfff00;
1478 uresult
= u1
& 0x000ff;
1479 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1480 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1489 for (rept
= 0; rept
< n_repeats
; rept
++)
1493 new_sp
= REG_GET (MSR_SP
) - op_bytes
;
1494 /* SP is always word-aligned. */
1497 REG_PUT (MSR_SP
, new_sp
);
1499 mem_put_val (sd
, SP
, u1
, op_bits
);
1500 if (opcode
->op
[1].type
== MSP430_Operand_Register
)
1501 opcode
->op
[1].reg
--;
1506 for (rept
= 0; rept
< n_repeats
; rept
++)
1510 u1
= mem_get_val (sd
, SP
, op_bits
);
1512 if (opcode
->op
[0].type
== MSP430_Operand_Register
)
1513 opcode
->op
[0].reg
++;
1514 new_sp
= REG_GET (MSR_SP
) + op_bytes
;
1515 /* SP is always word-aligned. */
1518 REG_PUT (MSR_SP
, new_sp
);
1525 if (maybe_perform_syscall (sd
, u1
))
1528 REG_PUT (MSR_SP
, REG_GET (MSR_SP
) - op_bytes
);
1529 mem_put_val (sd
, SP
, PC
, op_bits
);
1530 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1531 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1532 "CALL: func %#x ret %#x, sp %#x",
1534 REG_PUT (MSR_PC
, u1
);
1538 u1
= mem_get_val (sd
, SP
, 16);
1541 PC
= mem_get_val (sd
, SP
, 16);
1543 /* Emulate the RETI action of the 20-bit CPUX architecure.
1544 This is safe for 16-bit CPU architectures as well, since the top
1545 8-bits of SR will have been written to the stack here, and will
1546 have been read as 0. */
1547 PC
|= (u1
& 0xF000) << 4;
1548 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1549 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1550 "RETI: pc %#x sr %#x",
1558 switch (opcode
->cond
)
1561 u1
= (SR
& MSP430_FLAG_Z
) ? 0 : 1;
1564 u1
= (SR
& MSP430_FLAG_Z
) ? 1 : 0;
1567 u1
= (SR
& MSP430_FLAG_C
) ? 0 : 1;
1570 u1
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1573 u1
= (SR
& MSP430_FLAG_N
) ? 1 : 0;
1576 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 1 : 0;
1579 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 0 : 1;
1588 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1589 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1590 "J%s: pc %#x -> %#x sr %#x, taken",
1591 cond_string (opcode
->cond
), PC
, i
, SR
);
1593 if (PC
== opcode_pc
)
1597 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1598 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1599 "J%s: pc %#x to %#x sr %#x, not taken",
1600 cond_string (opcode
->cond
), PC
, i
, SR
);
1604 fprintf (stderr
, "error: unexpected opcode id %d\n", opcode
->id
);
1610 sim_engine_run (SIM_DESC sd
,
1617 msp430_step_once (sd
);
1618 if (sim_events_tick (sd
))
1619 sim_events_process (sd
);