sim/or1k/sem-switch.c

   1 /* Simulator instruction semantics for or1k32bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2018 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { OR1K32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { OR1K32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { OR1K32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { OR1K32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J },
  42     { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL },
  43     { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR },
  44     { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR },
  45     { OR1K32BF_INSN_L_BNF, && case_sem_INSN_L_BNF },
  46     { OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF },
  47     { OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP },
  48     { OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS },
  49     { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC },
  50     { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC },
  51     { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC },
  52     { OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE },
  53     { OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM },
  54     { OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI },
  55     { OR1K32BF_INSN_L_MACRC, && case_sem_INSN_L_MACRC },
  56     { OR1K32BF_INSN_L_MFSPR, && case_sem_INSN_L_MFSPR },
  57     { OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR },
  58     { OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ },
  59     { OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS },
  60     { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA },
  61     { OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ },
  62     { OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS },
  63     { OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ },
  64     { OR1K32BF_INSN_L_LHS, && case_sem_INSN_L_LHS },
  65     { OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW },
  66     { OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB },
  67     { OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH },
  68     { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA },
  69     { OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL },
  70     { OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI },
  71     { OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL },
  72     { OR1K32BF_INSN_L_SRLI, && case_sem_INSN_L_SRLI },
  73     { OR1K32BF_INSN_L_SRA, && case_sem_INSN_L_SRA },
  74     { OR1K32BF_INSN_L_SRAI, && case_sem_INSN_L_SRAI },
  75     { OR1K32BF_INSN_L_ROR, && case_sem_INSN_L_ROR },
  76     { OR1K32BF_INSN_L_RORI, && case_sem_INSN_L_RORI },
  77     { OR1K32BF_INSN_L_AND, && case_sem_INSN_L_AND },
  78     { OR1K32BF_INSN_L_OR, && case_sem_INSN_L_OR },
  79     { OR1K32BF_INSN_L_XOR, && case_sem_INSN_L_XOR },
  80     { OR1K32BF_INSN_L_ADD, && case_sem_INSN_L_ADD },
  81     { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB },
  82     { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC },
  83     { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL },
  84     { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU },
  85     { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV },
  86     { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU },
  87     { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 },
  88     { OR1K32BF_INSN_L_FL1, && case_sem_INSN_L_FL1 },
  89     { OR1K32BF_INSN_L_ANDI, && case_sem_INSN_L_ANDI },
  90     { OR1K32BF_INSN_L_ORI, && case_sem_INSN_L_ORI },
  91     { OR1K32BF_INSN_L_XORI, && case_sem_INSN_L_XORI },
  92     { OR1K32BF_INSN_L_ADDI, && case_sem_INSN_L_ADDI },
  93     { OR1K32BF_INSN_L_ADDIC, && case_sem_INSN_L_ADDIC },
  94     { OR1K32BF_INSN_L_MULI, && case_sem_INSN_L_MULI },
  95     { OR1K32BF_INSN_L_EXTHS, && case_sem_INSN_L_EXTHS },
  96     { OR1K32BF_INSN_L_EXTBS, && case_sem_INSN_L_EXTBS },
  97     { OR1K32BF_INSN_L_EXTHZ, && case_sem_INSN_L_EXTHZ },
  98     { OR1K32BF_INSN_L_EXTBZ, && case_sem_INSN_L_EXTBZ },
  99     { OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS },
 100     { OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ },
 101     { OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV },
 102     { OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS },
 103     { OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI },
 104     { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
 105     { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
 106     { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
 107     { OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI },
 108     { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
 109     { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
 110     { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
 111     { OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI },
 112     { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
 113     { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
 114     { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
 115     { OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI },
 116     { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
 117     { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
 118     { OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ },
 119     { OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI },
 120     { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
 121     { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI },
 122     { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC },
 123     { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB },
 124     { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI },
 125     { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 },
 126     { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 },
 127     { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 },
 128     { OR1K32BF_INSN_L_CUST4, && case_sem_INSN_L_CUST4 },
 129     { OR1K32BF_INSN_L_CUST5, && case_sem_INSN_L_CUST5 },
 130     { OR1K32BF_INSN_L_CUST6, && case_sem_INSN_L_CUST6 },
 131     { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
 132     { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
 133     { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
 134     { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
 135     { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
 136     { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
 137     { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
 138     { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
 139     { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
 140     { OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S },
 141     { OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S },
 142     { OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S },
 143     { OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S },
 144     { OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S },
 145     { OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S },
 146     { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
 147     { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
 148     { 0, 0 }
 149   };
 150   int i;
 151
 152   for (i = 0; labels[i].label != 0; ++i)
 153     {
 154 #if FAST_P
 155       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 156 #else
 157       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 158 #endif
 159     }
 160
 161 #undef DEFINE_LABELS
 162 #endif /* DEFINE_LABELS */
 163
 164 #ifdef DEFINE_SWITCH
 165
 166 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 167    off frills like tracing and profiling.  */
 168 /* FIXME: A better way would be to have TRACE_RESULT check for something
 169    that can cause it to be optimized out.  Another way would be to emit
 170    special handlers into the instruction "stream".  */
 171
 172 #if FAST_P
 173 #undef CGEN_TRACE_RESULT
 174 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
 175 #endif
 176
 177 #undef GET_ATTR
 178 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 179
 180 {
 181
 182 #if WITH_SCACHE_PBB
 183
 184 /* Branch to next handler without going around main loop.  */
 185 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 186 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 187
 188 #else /* ! WITH_SCACHE_PBB */
 189
 190 #define NEXT(vpc) BREAK (sem)
 191 #ifdef __GNUC__
 192 #if FAST_P
 193   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 194 #else
 195   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 196 #endif
 197 #else
 198   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 199 #endif
 200
 201 #endif /* ! WITH_SCACHE_PBB */
 202
 203     {
 204
 205   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 206 {
 207   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 208   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 209 #define FLD(f) abuf->fields.sfmt_empty.f
 210   int UNUSED written = 0;
 211   IADDR UNUSED pc = abuf->addr;
 212   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 213
 214   {
 215     /* Update the recorded pc in the cpu state struct.
 216        Only necessary for WITH_SCACHE case, but to avoid the
 217        conditional compilation ....  */
 218     SET_H_PC (pc);
 219     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 220        using the default-insn-bitsize spec.  When executing insns in parallel
 221        we may want to queue the fault and continue execution.  */
 222     vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 223     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 224   }
 225
 226 #undef FLD
 227 }
 228   NEXT (vpc);
 229
 230   CASE (sem, INSN_X_AFTER) : /* --after-- */
 231 {
 232   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 233   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 234 #define FLD(f) abuf->fields.sfmt_empty.f
 235   int UNUSED written = 0;
 236   IADDR UNUSED pc = abuf->addr;
 237   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 238
 239   {
 240 #if WITH_SCACHE_PBB_OR1K32BF
 241     or1k32bf_pbb_after (current_cpu, sem_arg);
 242 #endif
 243   }
 244
 245 #undef FLD
 246 }
 247   NEXT (vpc);
 248
 249   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 250 {
 251   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 252   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 253 #define FLD(f) abuf->fields.sfmt_empty.f
 254   int UNUSED written = 0;
 255   IADDR UNUSED pc = abuf->addr;
 256   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 257
 258   {
 259 #if WITH_SCACHE_PBB_OR1K32BF
 260     or1k32bf_pbb_before (current_cpu, sem_arg);
 261 #endif
 262   }
 263
 264 #undef FLD
 265 }
 266   NEXT (vpc);
 267
 268   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 269 {
 270   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 271   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 272 #define FLD(f) abuf->fields.sfmt_empty.f
 273   int UNUSED written = 0;
 274   IADDR UNUSED pc = abuf->addr;
 275   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 276
 277   {
 278 #if WITH_SCACHE_PBB_OR1K32BF
 279 #ifdef DEFINE_SWITCH
 280     vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
 281                                pbb_br_type, pbb_br_npc);
 282     BREAK (sem);
 283 #else
 284     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 285     vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
 286                                CPU_PBB_BR_TYPE (current_cpu),
 287                                CPU_PBB_BR_NPC (current_cpu));
 288 #endif
 289 #endif
 290   }
 291
 292 #undef FLD
 293 }
 294   NEXT (vpc);
 295
 296   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 297 {
 298   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 299   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 300 #define FLD(f) abuf->fields.sfmt_empty.f
 301   int UNUSED written = 0;
 302   IADDR UNUSED pc = abuf->addr;
 303   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 304
 305   {
 306 #if WITH_SCACHE_PBB_OR1K32BF
 307     vpc = or1k32bf_pbb_chain (current_cpu, sem_arg);
 308 #ifdef DEFINE_SWITCH
 309     BREAK (sem);
 310 #endif
 311 #endif
 312   }
 313
 314 #undef FLD
 315 }
 316   NEXT (vpc);
 317
 318   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 319 {
 320   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 321   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 322 #define FLD(f) abuf->fields.sfmt_empty.f
 323   int UNUSED written = 0;
 324   IADDR UNUSED pc = abuf->addr;
 325   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 326
 327   {
 328 #if WITH_SCACHE_PBB_OR1K32BF
 329 #if defined DEFINE_SWITCH || defined FAST_P
 330     /* In the switch case FAST_P is a constant, allowing several optimizations
 331        in any called inline functions.  */
 332     vpc = or1k32bf_pbb_begin (current_cpu, FAST_P);
 333 #else
 334 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 335     vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 336 #else
 337     vpc = or1k32bf_pbb_begin (current_cpu, 0);
 338 #endif
 339 #endif
 340 #endif
 341   }
 342
 343 #undef FLD
 344 }
 345   NEXT (vpc);
 346
 347   CASE (sem, INSN_L_J) : /* l.j ${disp26} */
 348 {
 349   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 350   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 351 #define FLD(f) abuf->fields.sfmt_l_j.f
 352   int UNUSED written = 0;
 353   IADDR UNUSED pc = abuf->addr;
 354   SEM_BRANCH_INIT
 355   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 356
 357 {
 358 {
 359   {
 360     USI opval = FLD (i_disp26);
 361     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 362     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 363   }
 364 }
 365 if (GET_H_SYS_CPUCFGR_ND ()) {
 366 if (1)
 367   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 368 }
 369 }
 370
 371   SEM_BRANCH_FINI (vpc);
 372 #undef FLD
 373 }
 374   NEXT (vpc);
 375
 376   CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */
 377 {
 378   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 379   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 380 #define FLD(f) abuf->fields.sfmt_l_j.f
 381   int UNUSED written = 0;
 382   IADDR UNUSED pc = abuf->addr;
 383   SEM_BRANCH_INIT
 384   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 385
 386 {
 387   {
 388     USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
 389     SET_H_GPR (((UINT) 9), opval);
 390     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 391   }
 392 {
 393 {
 394   {
 395     USI opval = FLD (i_disp26);
 396     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 397     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 398   }
 399 }
 400 if (GET_H_SYS_CPUCFGR_ND ()) {
 401 if (1)
 402   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 403 }
 404 }
 405 }
 406
 407   SEM_BRANCH_FINI (vpc);
 408 #undef FLD
 409 }
 410   NEXT (vpc);
 411
 412   CASE (sem, INSN_L_JR) : /* l.jr $rB */
 413 {
 414   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 415   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 416 #define FLD(f) abuf->fields.sfmt_l_sll.f
 417   int UNUSED written = 0;
 418   IADDR UNUSED pc = abuf->addr;
 419   SEM_BRANCH_INIT
 420   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 421
 422 {
 423 {
 424   {
 425     USI opval = GET_H_GPR (FLD (f_r3));
 426     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
 427     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 428   }
 429 }
 430 if (GET_H_SYS_CPUCFGR_ND ()) {
 431 if (1)
 432   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 433 }
 434 }
 435
 436   SEM_BRANCH_FINI (vpc);
 437 #undef FLD
 438 }
 439   NEXT (vpc);
 440
 441   CASE (sem, INSN_L_JALR) : /* l.jalr $rB */
 442 {
 443   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 444   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 445 #define FLD(f) abuf->fields.sfmt_l_sll.f
 446   int UNUSED written = 0;
 447   IADDR UNUSED pc = abuf->addr;
 448   SEM_BRANCH_INIT
 449   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 450
 451 {
 452   {
 453     USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
 454     SET_H_GPR (((UINT) 9), opval);
 455     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 456   }
 457 {
 458 {
 459   {
 460     USI opval = GET_H_GPR (FLD (f_r3));
 461     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
 462     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 463   }
 464 }
 465 if (GET_H_SYS_CPUCFGR_ND ()) {
 466 if (1)
 467   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 468 }
 469 }
 470 }
 471
 472   SEM_BRANCH_FINI (vpc);
 473 #undef FLD
 474 }
 475   NEXT (vpc);
 476
 477   CASE (sem, INSN_L_BNF) : /* l.bnf ${disp26} */
 478 {
 479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 481 #define FLD(f) abuf->fields.sfmt_l_j.f
 482   int UNUSED written = 0;
 483   IADDR UNUSED pc = abuf->addr;
 484   SEM_BRANCH_INIT
 485   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 486
 487 {
 488 if (NOTSI (GET_H_SYS_SR_F ())) {
 489 {
 490   {
 491     USI opval = FLD (i_disp26);
 492     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 493     written |= (1 << 4);
 494     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 495   }
 496 }
 497 } else {
 498 if (GET_H_SYS_CPUCFGR_ND ()) {
 499 {
 500   {
 501     USI opval = ADDSI (pc, 4);
 502     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
 503     written |= (1 << 4);
 504     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 505   }
 506 }
 507 }
 508 }
 509 if (GET_H_SYS_CPUCFGR_ND ()) {
 510 if (1)
 511   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 512 }
 513 }
 514
 515   abuf->written = written;
 516   SEM_BRANCH_FINI (vpc);
 517 #undef FLD
 518 }
 519   NEXT (vpc);
 520
 521   CASE (sem, INSN_L_BF) : /* l.bf ${disp26} */
 522 {
 523   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 524   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 525 #define FLD(f) abuf->fields.sfmt_l_j.f
 526   int UNUSED written = 0;
 527   IADDR UNUSED pc = abuf->addr;
 528   SEM_BRANCH_INIT
 529   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 530
 531 {
 532 if (GET_H_SYS_SR_F ()) {
 533 {
 534   {
 535     USI opval = FLD (i_disp26);
 536     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 537     written |= (1 << 4);
 538     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 539   }
 540 }
 541 } else {
 542 if (GET_H_SYS_CPUCFGR_ND ()) {
 543 {
 544   {
 545     USI opval = ADDSI (pc, 4);
 546     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
 547     written |= (1 << 4);
 548     CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 549   }
 550 }
 551 }
 552 }
 553 if (GET_H_SYS_CPUCFGR_ND ()) {
 554 if (1)
 555   SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
 556 }
 557 }
 558
 559   abuf->written = written;
 560   SEM_BRANCH_FINI (vpc);
 561 #undef FLD
 562 }
 563   NEXT (vpc);
 564
 565   CASE (sem, INSN_L_TRAP) : /* l.trap ${uimm16} */
 566 {
 567   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 568   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 569 #define FLD(f) abuf->fields.sfmt_empty.f
 570   int UNUSED written = 0;
 571   IADDR UNUSED pc = abuf->addr;
 572   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 573
 574 or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP);
 575
 576 #undef FLD
 577 }
 578   NEXT (vpc);
 579
 580   CASE (sem, INSN_L_SYS) : /* l.sys ${uimm16} */
 581 {
 582   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 583   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 584 #define FLD(f) abuf->fields.sfmt_empty.f
 585   int UNUSED written = 0;
 586   IADDR UNUSED pc = abuf->addr;
 587   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 588
 589 or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
 590
 591 #undef FLD
 592 }
 593   NEXT (vpc);
 594
 595   CASE (sem, INSN_L_MSYNC) : /* l.msync */
 596 {
 597   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 598   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 599 #define FLD(f) abuf->fields.sfmt_empty.f
 600   int UNUSED written = 0;
 601   IADDR UNUSED pc = abuf->addr;
 602   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 603
 604 ((void) 0); /*nop*/
 605
 606 #undef FLD
 607 }
 608   NEXT (vpc);
 609
 610   CASE (sem, INSN_L_PSYNC) : /* l.psync */
 611 {
 612   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 613   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 614 #define FLD(f) abuf->fields.sfmt_empty.f
 615   int UNUSED written = 0;
 616   IADDR UNUSED pc = abuf->addr;
 617   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 618
 619 ((void) 0); /*nop*/
 620
 621 #undef FLD
 622 }
 623   NEXT (vpc);
 624
 625   CASE (sem, INSN_L_CSYNC) : /* l.csync */
 626 {
 627   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 628   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 629 #define FLD(f) abuf->fields.sfmt_empty.f
 630   int UNUSED written = 0;
 631   IADDR UNUSED pc = abuf->addr;
 632   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 633
 634 ((void) 0); /*nop*/
 635
 636 #undef FLD
 637 }
 638   NEXT (vpc);
 639
 640   CASE (sem, INSN_L_RFE) : /* l.rfe */
 641 {
 642   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 644 #define FLD(f) abuf->fields.sfmt_empty.f
 645   int UNUSED written = 0;
 646   IADDR UNUSED pc = abuf->addr;
 647   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 648
 649 or1k32bf_rfe (current_cpu);
 650
 651 #undef FLD
 652 }
 653   NEXT (vpc);
 654
 655   CASE (sem, INSN_L_NOP_IMM) : /* l.nop ${uimm16} */
 656 {
 657   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 658   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 659 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
 660   int UNUSED written = 0;
 661   IADDR UNUSED pc = abuf->addr;
 662   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 663
 664 or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
 665
 666 #undef FLD
 667 }
 668   NEXT (vpc);
 669
 670   CASE (sem, INSN_L_MOVHI) : /* l.movhi $rD,$uimm16 */
 671 {
 672   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 673   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 674 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
 675   int UNUSED written = 0;
 676   IADDR UNUSED pc = abuf->addr;
 677   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 678
 679   {
 680     USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
 681     SET_H_GPR (FLD (f_r1), opval);
 682     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 683   }
 684
 685 #undef FLD
 686 }
 687   NEXT (vpc);
 688
 689   CASE (sem, INSN_L_MACRC) : /* l.macrc $rD */
 690 {
 691   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 692   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 693 #define FLD(f) abuf->fields.sfmt_l_slli.f
 694   int UNUSED written = 0;
 695   IADDR UNUSED pc = abuf->addr;
 696   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 697
 698 {
 699   {
 700     USI opval = GET_H_MAC_MACLO ();
 701     SET_H_GPR (FLD (f_r1), opval);
 702     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 703   }
 704   {
 705     USI opval = 0;
 706     SET_H_MAC_MACLO (opval);
 707     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
 708   }
 709   {
 710     USI opval = 0;
 711     SET_H_MAC_MACHI (opval);
 712     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
 713   }
 714 }
 715
 716 #undef FLD
 717 }
 718   NEXT (vpc);
 719
 720   CASE (sem, INSN_L_MFSPR) : /* l.mfspr $rD,$rA,${uimm16} */
 721 {
 722   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 723   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 724 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
 725   int UNUSED written = 0;
 726   IADDR UNUSED pc = abuf->addr;
 727   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 728
 729   {
 730     USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
 731     SET_H_GPR (FLD (f_r1), opval);
 732     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 733   }
 734
 735 #undef FLD
 736 }
 737   NEXT (vpc);
 738
 739   CASE (sem, INSN_L_MTSPR) : /* l.mtspr $rA,$rB,${uimm16-split} */
 740 {
 741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 743 #define FLD(f) abuf->fields.sfmt_l_mtspr.f
 744   int UNUSED written = 0;
 745   IADDR UNUSED pc = abuf->addr;
 746   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 747
 748 or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
 749
 750 #undef FLD
 751 }
 752   NEXT (vpc);
 753
 754   CASE (sem, INSN_L_LWZ) : /* l.lwz $rD,${simm16}($rA) */
 755 {
 756   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 757   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 758 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 759   int UNUSED written = 0;
 760   IADDR UNUSED pc = abuf->addr;
 761   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 762
 763   {
 764     USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
 765     SET_H_GPR (FLD (f_r1), opval);
 766     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 767   }
 768
 769 #undef FLD
 770 }
 771   NEXT (vpc);
 772
 773   CASE (sem, INSN_L_LWS) : /* l.lws $rD,${simm16}($rA) */
 774 {
 775   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 776   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 777 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 778   int UNUSED written = 0;
 779   IADDR UNUSED pc = abuf->addr;
 780   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 781
 782   {
 783     SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
 784     SET_H_GPR (FLD (f_r1), opval);
 785     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 786   }
 787
 788 #undef FLD
 789 }
 790   NEXT (vpc);
 791
 792   CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */
 793 {
 794   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 795   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 796 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 797   int UNUSED written = 0;
 798   IADDR UNUSED pc = abuf->addr;
 799   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 800
 801 {
 802   {
 803     USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
 804     SET_H_GPR (FLD (f_r1), opval);
 805     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 806   }
 807   {
 808     BI opval = 1;
 809     CPU (h_atomic_reserve) = opval;
 810     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
 811   }
 812   {
 813     SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
 814     CPU (h_atomic_address) = opval;
 815     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
 816   }
 817 }
 818
 819 #undef FLD
 820 }
 821   NEXT (vpc);
 822
 823   CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */
 824 {
 825   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 826   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 827 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 828   int UNUSED written = 0;
 829   IADDR UNUSED pc = abuf->addr;
 830   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 831
 832   {
 833     USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
 834     SET_H_GPR (FLD (f_r1), opval);
 835     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 836   }
 837
 838 #undef FLD
 839 }
 840   NEXT (vpc);
 841
 842   CASE (sem, INSN_L_LBS) : /* l.lbs $rD,${simm16}($rA) */
 843 {
 844   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 845   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 846 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 847   int UNUSED written = 0;
 848   IADDR UNUSED pc = abuf->addr;
 849   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 850
 851   {
 852     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
 853     SET_H_GPR (FLD (f_r1), opval);
 854     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 855   }
 856
 857 #undef FLD
 858 }
 859   NEXT (vpc);
 860
 861   CASE (sem, INSN_L_LHZ) : /* l.lhz $rD,${simm16}($rA) */
 862 {
 863   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 864   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 865 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 866   int UNUSED written = 0;
 867   IADDR UNUSED pc = abuf->addr;
 868   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 869
 870   {
 871     USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
 872     SET_H_GPR (FLD (f_r1), opval);
 873     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 874   }
 875
 876 #undef FLD
 877 }
 878   NEXT (vpc);
 879
 880   CASE (sem, INSN_L_LHS) : /* l.lhs $rD,${simm16}($rA) */
 881 {
 882   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 883   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 884 #define FLD(f) abuf->fields.sfmt_l_lwz.f
 885   int UNUSED written = 0;
 886   IADDR UNUSED pc = abuf->addr;
 887   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 888
 889   {
 890     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
 891     SET_H_GPR (FLD (f_r1), opval);
 892     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
 893   }
 894
 895 #undef FLD
 896 }
 897   NEXT (vpc);
 898
 899   CASE (sem, INSN_L_SW) : /* l.sw ${simm16-split}($rA),$rB */
 900 {
 901   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 902   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 903 #define FLD(f) abuf->fields.sfmt_l_sw.f
 904   int UNUSED written = 0;
 905   IADDR UNUSED pc = abuf->addr;
 906   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 907
 908 {
 909   SI tmp_addr;
 910   tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
 911   {
 912     USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
 913     SETMEMUSI (current_cpu, pc, tmp_addr, opval);
 914     CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
 915   }
 916 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
 917   {
 918     BI opval = 0;
 919     CPU (h_atomic_reserve) = opval;
 920     written |= (1 << 4);
 921     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
 922   }
 923 }
 924 }
 925
 926   abuf->written = written;
 927 #undef FLD
 928 }
 929   NEXT (vpc);
 930
 931   CASE (sem, INSN_L_SB) : /* l.sb ${simm16-split}($rA),$rB */
 932 {
 933   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 934   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 935 #define FLD(f) abuf->fields.sfmt_l_sw.f
 936   int UNUSED written = 0;
 937   IADDR UNUSED pc = abuf->addr;
 938   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 939
 940 {
 941   SI tmp_addr;
 942   tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
 943   {
 944     UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
 945     SETMEMUQI (current_cpu, pc, tmp_addr, opval);
 946     CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
 947   }
 948 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
 949   {
 950     BI opval = 0;
 951     CPU (h_atomic_reserve) = opval;
 952     written |= (1 << 4);
 953     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
 954   }
 955 }
 956 }
 957
 958   abuf->written = written;
 959 #undef FLD
 960 }
 961   NEXT (vpc);
 962
 963   CASE (sem, INSN_L_SH) : /* l.sh ${simm16-split}($rA),$rB */
 964 {
 965   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 966   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 967 #define FLD(f) abuf->fields.sfmt_l_sw.f
 968   int UNUSED written = 0;
 969   IADDR UNUSED pc = abuf->addr;
 970   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 971
 972 {
 973   SI tmp_addr;
 974   tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
 975   {
 976     UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
 977     SETMEMUHI (current_cpu, pc, tmp_addr, opval);
 978     CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
 979   }
 980 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
 981   {
 982     BI opval = 0;
 983     CPU (h_atomic_reserve) = opval;
 984     written |= (1 << 4);
 985     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
 986   }
 987 }
 988 }
 989
 990   abuf->written = written;
 991 #undef FLD
 992 }
 993   NEXT (vpc);
 994
 995   CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */
 996 {
 997   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 998   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 999 #define FLD(f) abuf->fields.sfmt_l_sw.f
1000   int UNUSED written = 0;
1001   IADDR UNUSED pc = abuf->addr;
1002   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1003
1004 {
1005   SI tmp_addr;
1006   BI tmp_flag;
1007   tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
1008   {
1009     USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
1010     SET_H_SYS_SR_F (opval);
1011     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1012   }
1013 if (GET_H_SYS_SR_F ()) {
1014   {
1015     USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
1016     SETMEMUSI (current_cpu, pc, tmp_addr, opval);
1017     written |= (1 << 7);
1018     CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1019   }
1020 }
1021   {
1022     BI opval = 0;
1023     CPU (h_atomic_reserve) = opval;
1024     CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
1025   }
1026 }
1027
1028   abuf->written = written;
1029 #undef FLD
1030 }
1031   NEXT (vpc);
1032
1033   CASE (sem, INSN_L_SLL) : /* l.sll $rD,$rA,$rB */
1034 {
1035   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1036   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1037 #define FLD(f) abuf->fields.sfmt_l_sll.f
1038   int UNUSED written = 0;
1039   IADDR UNUSED pc = abuf->addr;
1040   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1041
1042   {
1043     USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1044     SET_H_GPR (FLD (f_r1), opval);
1045     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1046   }
1047
1048 #undef FLD
1049 }
1050   NEXT (vpc);
1051
1052   CASE (sem, INSN_L_SLLI) : /* l.slli $rD,$rA,${uimm6} */
1053 {
1054   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1055   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1056 #define FLD(f) abuf->fields.sfmt_l_slli.f
1057   int UNUSED written = 0;
1058   IADDR UNUSED pc = abuf->addr;
1059   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1060
1061   {
1062     USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1063     SET_H_GPR (FLD (f_r1), opval);
1064     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1065   }
1066
1067 #undef FLD
1068 }
1069   NEXT (vpc);
1070
1071   CASE (sem, INSN_L_SRL) : /* l.srl $rD,$rA,$rB */
1072 {
1073   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1074   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1075 #define FLD(f) abuf->fields.sfmt_l_sll.f
1076   int UNUSED written = 0;
1077   IADDR UNUSED pc = abuf->addr;
1078   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1079
1080   {
1081     USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1082     SET_H_GPR (FLD (f_r1), opval);
1083     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1084   }
1085
1086 #undef FLD
1087 }
1088   NEXT (vpc);
1089
1090   CASE (sem, INSN_L_SRLI) : /* l.srli $rD,$rA,${uimm6} */
1091 {
1092   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1093   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1094 #define FLD(f) abuf->fields.sfmt_l_slli.f
1095   int UNUSED written = 0;
1096   IADDR UNUSED pc = abuf->addr;
1097   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1098
1099   {
1100     USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1101     SET_H_GPR (FLD (f_r1), opval);
1102     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1103   }
1104
1105 #undef FLD
1106 }
1107   NEXT (vpc);
1108
1109   CASE (sem, INSN_L_SRA) : /* l.sra $rD,$rA,$rB */
1110 {
1111   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1112   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1113 #define FLD(f) abuf->fields.sfmt_l_sll.f
1114   int UNUSED written = 0;
1115   IADDR UNUSED pc = abuf->addr;
1116   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1117
1118   {
1119     USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1120     SET_H_GPR (FLD (f_r1), opval);
1121     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1122   }
1123
1124 #undef FLD
1125 }
1126   NEXT (vpc);
1127
1128   CASE (sem, INSN_L_SRAI) : /* l.srai $rD,$rA,${uimm6} */
1129 {
1130   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1131   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1132 #define FLD(f) abuf->fields.sfmt_l_slli.f
1133   int UNUSED written = 0;
1134   IADDR UNUSED pc = abuf->addr;
1135   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1136
1137   {
1138     USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1139     SET_H_GPR (FLD (f_r1), opval);
1140     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1141   }
1142
1143 #undef FLD
1144 }
1145   NEXT (vpc);
1146
1147   CASE (sem, INSN_L_ROR) : /* l.ror $rD,$rA,$rB */
1148 {
1149   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1150   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1151 #define FLD(f) abuf->fields.sfmt_l_sll.f
1152   int UNUSED written = 0;
1153   IADDR UNUSED pc = abuf->addr;
1154   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1155
1156   {
1157     USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1158     SET_H_GPR (FLD (f_r1), opval);
1159     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1160   }
1161
1162 #undef FLD
1163 }
1164   NEXT (vpc);
1165
1166   CASE (sem, INSN_L_RORI) : /* l.rori $rD,$rA,${uimm6} */
1167 {
1168   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1169   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1170 #define FLD(f) abuf->fields.sfmt_l_slli.f
1171   int UNUSED written = 0;
1172   IADDR UNUSED pc = abuf->addr;
1173   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1174
1175   {
1176     USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1177     SET_H_GPR (FLD (f_r1), opval);
1178     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1179   }
1180
1181 #undef FLD
1182 }
1183   NEXT (vpc);
1184
1185   CASE (sem, INSN_L_AND) : /* l.and $rD,$rA,$rB */
1186 {
1187   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1188   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1189 #define FLD(f) abuf->fields.sfmt_l_sll.f
1190   int UNUSED written = 0;
1191   IADDR UNUSED pc = abuf->addr;
1192   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1193
1194   {
1195     USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1196     SET_H_GPR (FLD (f_r1), opval);
1197     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1198   }
1199
1200 #undef FLD
1201 }
1202   NEXT (vpc);
1203
1204   CASE (sem, INSN_L_OR) : /* l.or $rD,$rA,$rB */
1205 {
1206   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1207   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1208 #define FLD(f) abuf->fields.sfmt_l_sll.f
1209   int UNUSED written = 0;
1210   IADDR UNUSED pc = abuf->addr;
1211   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1212
1213   {
1214     USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1215     SET_H_GPR (FLD (f_r1), opval);
1216     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1217   }
1218
1219 #undef FLD
1220 }
1221   NEXT (vpc);
1222
1223   CASE (sem, INSN_L_XOR) : /* l.xor $rD,$rA,$rB */
1224 {
1225   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1226   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1227 #define FLD(f) abuf->fields.sfmt_l_sll.f
1228   int UNUSED written = 0;
1229   IADDR UNUSED pc = abuf->addr;
1230   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1231
1232   {
1233     USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1234     SET_H_GPR (FLD (f_r1), opval);
1235     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1236   }
1237
1238 #undef FLD
1239 }
1240   NEXT (vpc);
1241
1242   CASE (sem, INSN_L_ADD) : /* l.add $rD,$rA,$rB */
1243 {
1244   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1245   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1246 #define FLD(f) abuf->fields.sfmt_l_sll.f
1247   int UNUSED written = 0;
1248   IADDR UNUSED pc = abuf->addr;
1249   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1250
1251 {
1252 {
1253   {
1254     BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1255     SET_H_SYS_SR_CY (opval);
1256     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1257   }
1258   {
1259     BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1260     SET_H_SYS_SR_OV (opval);
1261     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1262   }
1263   {
1264     USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1265     SET_H_GPR (FLD (f_r1), opval);
1266     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1267   }
1268 }
1269 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1270 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1271 }
1272 }
1273
1274 #undef FLD
1275 }
1276   NEXT (vpc);
1277
1278   CASE (sem, INSN_L_SUB) : /* l.sub $rD,$rA,$rB */
1279 {
1280   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1281   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1282 #define FLD(f) abuf->fields.sfmt_l_sll.f
1283   int UNUSED written = 0;
1284   IADDR UNUSED pc = abuf->addr;
1285   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1286
1287 {
1288 {
1289   {
1290     BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1291     SET_H_SYS_SR_CY (opval);
1292     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1293   }
1294   {
1295     BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1296     SET_H_SYS_SR_OV (opval);
1297     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1298   }
1299   {
1300     USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1301     SET_H_GPR (FLD (f_r1), opval);
1302     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1303   }
1304 }
1305 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1306 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1307 }
1308 }
1309
1310 #undef FLD
1311 }
1312   NEXT (vpc);
1313
1314   CASE (sem, INSN_L_ADDC) : /* l.addc $rD,$rA,$rB */
1315 {
1316   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1317   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1318 #define FLD(f) abuf->fields.sfmt_l_sll.f
1319   int UNUSED written = 0;
1320   IADDR UNUSED pc = abuf->addr;
1321   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1322
1323 {
1324 {
1325   BI tmp_tmp_sys_sr_cy;
1326   tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
1327   {
1328     BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1329     SET_H_SYS_SR_CY (opval);
1330     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1331   }
1332   {
1333     BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1334     SET_H_SYS_SR_OV (opval);
1335     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1336   }
1337   {
1338     USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1339     SET_H_GPR (FLD (f_r1), opval);
1340     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1341   }
1342 }
1343 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1344 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1345 }
1346 }
1347
1348 #undef FLD
1349 }
1350   NEXT (vpc);
1351
1352   CASE (sem, INSN_L_MUL) : /* l.mul $rD,$rA,$rB */
1353 {
1354   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1355   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1356 #define FLD(f) abuf->fields.sfmt_l_sll.f
1357   int UNUSED written = 0;
1358   IADDR UNUSED pc = abuf->addr;
1359   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1360
1361 {
1362 {
1363   {
1364     BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1365     SET_H_SYS_SR_OV (opval);
1366     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1367   }
1368   {
1369     BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1370     SET_H_SYS_SR_CY (opval);
1371     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1372   }
1373   {
1374     USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1375     SET_H_GPR (FLD (f_r1), opval);
1376     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1377   }
1378 }
1379 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1380 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1381 }
1382 }
1383
1384 #undef FLD
1385 }
1386   NEXT (vpc);
1387
1388   CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */
1389 {
1390   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1391   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1392 #define FLD(f) abuf->fields.sfmt_l_sll.f
1393   int UNUSED written = 0;
1394   IADDR UNUSED pc = abuf->addr;
1395   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1396
1397 {
1398 {
1399   {
1400     BI opval = 0;
1401     SET_H_SYS_SR_OV (opval);
1402     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1403   }
1404   {
1405     BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1406     SET_H_SYS_SR_CY (opval);
1407     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1408   }
1409   {
1410     USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1411     SET_H_GPR (FLD (f_r1), opval);
1412     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1413   }
1414 }
1415 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1416 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1417 }
1418 }
1419
1420 #undef FLD
1421 }
1422   NEXT (vpc);
1423
1424   CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */
1425 {
1426   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1427   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1428 #define FLD(f) abuf->fields.sfmt_l_sll.f
1429   int UNUSED written = 0;
1430   IADDR UNUSED pc = abuf->addr;
1431   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1432
1433 {
1434 if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
1435 {
1436   {
1437     BI opval = 0;
1438     SET_H_SYS_SR_CY (opval);
1439     written |= (1 << 6);
1440     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1441   }
1442   {
1443     SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1444     SET_H_GPR (FLD (f_r1), opval);
1445     written |= (1 << 5);
1446     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1447   }
1448 }
1449 } else {
1450   {
1451     BI opval = 1;
1452     SET_H_SYS_SR_CY (opval);
1453     written |= (1 << 6);
1454     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1455   }
1456 }
1457   {
1458     BI opval = 0;
1459     SET_H_SYS_SR_OV (opval);
1460     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1461   }
1462 if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
1463 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1464 }
1465 }
1466
1467   abuf->written = written;
1468 #undef FLD
1469 }
1470   NEXT (vpc);
1471
1472   CASE (sem, INSN_L_DIVU) : /* l.divu $rD,$rA,$rB */
1473 {
1474   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1475   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1476 #define FLD(f) abuf->fields.sfmt_l_sll.f
1477   int UNUSED written = 0;
1478   IADDR UNUSED pc = abuf->addr;
1479   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1480
1481 {
1482 if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
1483 {
1484   {
1485     BI opval = 0;
1486     SET_H_SYS_SR_CY (opval);
1487     written |= (1 << 6);
1488     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1489   }
1490   {
1491     USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1492     SET_H_GPR (FLD (f_r1), opval);
1493     written |= (1 << 5);
1494     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1495   }
1496 }
1497 } else {
1498   {
1499     BI opval = 1;
1500     SET_H_SYS_SR_CY (opval);
1501     written |= (1 << 6);
1502     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1503   }
1504 }
1505   {
1506     BI opval = 0;
1507     SET_H_SYS_SR_OV (opval);
1508     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1509   }
1510 if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
1511 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1512 }
1513 }
1514
1515   abuf->written = written;
1516 #undef FLD
1517 }
1518   NEXT (vpc);
1519
1520   CASE (sem, INSN_L_FF1) : /* l.ff1 $rD,$rA */
1521 {
1522   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1523   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1524 #define FLD(f) abuf->fields.sfmt_l_slli.f
1525   int UNUSED written = 0;
1526   IADDR UNUSED pc = abuf->addr;
1527   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1528
1529   {
1530     USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
1531     SET_H_GPR (FLD (f_r1), opval);
1532     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1533   }
1534
1535 #undef FLD
1536 }
1537   NEXT (vpc);
1538
1539   CASE (sem, INSN_L_FL1) : /* l.fl1 $rD,$rA */
1540 {
1541   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1542   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1543 #define FLD(f) abuf->fields.sfmt_l_slli.f
1544   int UNUSED written = 0;
1545   IADDR UNUSED pc = abuf->addr;
1546   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1547
1548   {
1549     USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
1550     SET_H_GPR (FLD (f_r1), opval);
1551     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1552   }
1553
1554 #undef FLD
1555 }
1556   NEXT (vpc);
1557
1558   CASE (sem, INSN_L_ANDI) : /* l.andi $rD,$rA,$uimm16 */
1559 {
1560   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1561   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1562 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
1563   int UNUSED written = 0;
1564   IADDR UNUSED pc = abuf->addr;
1565   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1566
1567   {
1568     USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
1569     SET_H_GPR (FLD (f_r1), opval);
1570     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1571   }
1572
1573 #undef FLD
1574 }
1575   NEXT (vpc);
1576
1577   CASE (sem, INSN_L_ORI) : /* l.ori $rD,$rA,$uimm16 */
1578 {
1579   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1580   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1581 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
1582   int UNUSED written = 0;
1583   IADDR UNUSED pc = abuf->addr;
1584   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1585
1586   {
1587     USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
1588     SET_H_GPR (FLD (f_r1), opval);
1589     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1590   }
1591
1592 #undef FLD
1593 }
1594   NEXT (vpc);
1595
1596   CASE (sem, INSN_L_XORI) : /* l.xori $rD,$rA,$simm16 */
1597 {
1598   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1599   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1600 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1601   int UNUSED written = 0;
1602   IADDR UNUSED pc = abuf->addr;
1603   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1604
1605   {
1606     USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1607     SET_H_GPR (FLD (f_r1), opval);
1608     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1609   }
1610
1611 #undef FLD
1612 }
1613   NEXT (vpc);
1614
1615   CASE (sem, INSN_L_ADDI) : /* l.addi $rD,$rA,$simm16 */
1616 {
1617   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1618   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1619 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1620   int UNUSED written = 0;
1621   IADDR UNUSED pc = abuf->addr;
1622   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1623
1624 {
1625 {
1626   {
1627     BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
1628     SET_H_SYS_SR_CY (opval);
1629     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1630   }
1631   {
1632     BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
1633     SET_H_SYS_SR_OV (opval);
1634     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1635   }
1636   {
1637     USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1638     SET_H_GPR (FLD (f_r1), opval);
1639     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1640   }
1641 }
1642 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1643 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1644 }
1645 }
1646
1647 #undef FLD
1648 }
1649   NEXT (vpc);
1650
1651   CASE (sem, INSN_L_ADDIC) : /* l.addic $rD,$rA,$simm16 */
1652 {
1653   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1654   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1655 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1656   int UNUSED written = 0;
1657   IADDR UNUSED pc = abuf->addr;
1658   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1659
1660 {
1661 {
1662   BI tmp_tmp_sys_sr_cy;
1663   tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
1664   {
1665     BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1666     SET_H_SYS_SR_CY (opval);
1667     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1668   }
1669   {
1670     BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1671     SET_H_SYS_SR_OV (opval);
1672     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1673   }
1674   {
1675     SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1676     SET_H_GPR (FLD (f_r1), opval);
1677     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1678   }
1679 }
1680 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1681 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1682 }
1683 }
1684
1685 #undef FLD
1686 }
1687   NEXT (vpc);
1688
1689   CASE (sem, INSN_L_MULI) : /* l.muli $rD,$rA,$simm16 */
1690 {
1691   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1692   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1693 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1694   int UNUSED written = 0;
1695   IADDR UNUSED pc = abuf->addr;
1696   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1697
1698 {
1699 {
1700   {
1701     USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1702     SET_H_SYS_SR_OV (opval);
1703     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1704   }
1705   {
1706     USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1707     SET_H_SYS_SR_CY (opval);
1708     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1709   }
1710   {
1711     USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1712     SET_H_GPR (FLD (f_r1), opval);
1713     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1714   }
1715 }
1716 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1717 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1718 }
1719 }
1720
1721 #undef FLD
1722 }
1723   NEXT (vpc);
1724
1725   CASE (sem, INSN_L_EXTHS) : /* l.exths $rD,$rA */
1726 {
1727   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1728   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1729 #define FLD(f) abuf->fields.sfmt_l_slli.f
1730   int UNUSED written = 0;
1731   IADDR UNUSED pc = abuf->addr;
1732   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1733
1734   {
1735     USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
1736     SET_H_GPR (FLD (f_r1), opval);
1737     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1738   }
1739
1740 #undef FLD
1741 }
1742   NEXT (vpc);
1743
1744   CASE (sem, INSN_L_EXTBS) : /* l.extbs $rD,$rA */
1745 {
1746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1748 #define FLD(f) abuf->fields.sfmt_l_slli.f
1749   int UNUSED written = 0;
1750   IADDR UNUSED pc = abuf->addr;
1751   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1752
1753   {
1754     USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
1755     SET_H_GPR (FLD (f_r1), opval);
1756     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1757   }
1758
1759 #undef FLD
1760 }
1761   NEXT (vpc);
1762
1763   CASE (sem, INSN_L_EXTHZ) : /* l.exthz $rD,$rA */
1764 {
1765   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1766   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1767 #define FLD(f) abuf->fields.sfmt_l_slli.f
1768   int UNUSED written = 0;
1769   IADDR UNUSED pc = abuf->addr;
1770   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1771
1772   {
1773     USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
1774     SET_H_GPR (FLD (f_r1), opval);
1775     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1776   }
1777
1778 #undef FLD
1779 }
1780   NEXT (vpc);
1781
1782   CASE (sem, INSN_L_EXTBZ) : /* l.extbz $rD,$rA */
1783 {
1784   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1785   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1786 #define FLD(f) abuf->fields.sfmt_l_slli.f
1787   int UNUSED written = 0;
1788   IADDR UNUSED pc = abuf->addr;
1789   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1790
1791   {
1792     USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
1793     SET_H_GPR (FLD (f_r1), opval);
1794     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1795   }
1796
1797 #undef FLD
1798 }
1799   NEXT (vpc);
1800
1801   CASE (sem, INSN_L_EXTWS) : /* l.extws $rD,$rA */
1802 {
1803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1805 #define FLD(f) abuf->fields.sfmt_l_slli.f
1806   int UNUSED written = 0;
1807   IADDR UNUSED pc = abuf->addr;
1808   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1809
1810   {
1811     USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
1812     SET_H_GPR (FLD (f_r1), opval);
1813     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1814   }
1815
1816 #undef FLD
1817 }
1818   NEXT (vpc);
1819
1820   CASE (sem, INSN_L_EXTWZ) : /* l.extwz $rD,$rA */
1821 {
1822   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1823   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1824 #define FLD(f) abuf->fields.sfmt_l_slli.f
1825   int UNUSED written = 0;
1826   IADDR UNUSED pc = abuf->addr;
1827   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1828
1829   {
1830     USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
1831     SET_H_GPR (FLD (f_r1), opval);
1832     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1833   }
1834
1835 #undef FLD
1836 }
1837   NEXT (vpc);
1838
1839   CASE (sem, INSN_L_CMOV) : /* l.cmov $rD,$rA,$rB */
1840 {
1841   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1842   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1843 #define FLD(f) abuf->fields.sfmt_l_sll.f
1844   int UNUSED written = 0;
1845   IADDR UNUSED pc = abuf->addr;
1846   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1847
1848 if (GET_H_SYS_SR_F ()) {
1849   {
1850     USI opval = GET_H_GPR (FLD (f_r2));
1851     SET_H_GPR (FLD (f_r1), opval);
1852     written |= (1 << 3);
1853     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1854   }
1855 } else {
1856   {
1857     USI opval = GET_H_GPR (FLD (f_r3));
1858     SET_H_GPR (FLD (f_r1), opval);
1859     written |= (1 << 3);
1860     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1861   }
1862 }
1863
1864   abuf->written = written;
1865 #undef FLD
1866 }
1867   NEXT (vpc);
1868
1869   CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
1870 {
1871   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1872   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1873 #define FLD(f) abuf->fields.sfmt_l_sll.f
1874   int UNUSED written = 0;
1875   IADDR UNUSED pc = abuf->addr;
1876   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1877
1878   {
1879     USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1880     SET_H_SYS_SR_F (opval);
1881     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1882   }
1883
1884 #undef FLD
1885 }
1886   NEXT (vpc);
1887
1888   CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */
1889 {
1890   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1891   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1892 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1893   int UNUSED written = 0;
1894   IADDR UNUSED pc = abuf->addr;
1895   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1896
1897   {
1898     USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1899     SET_H_SYS_SR_F (opval);
1900     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1901   }
1902
1903 #undef FLD
1904 }
1905   NEXT (vpc);
1906
1907   CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
1908 {
1909   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1910   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1911 #define FLD(f) abuf->fields.sfmt_l_sll.f
1912   int UNUSED written = 0;
1913   IADDR UNUSED pc = abuf->addr;
1914   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1915
1916   {
1917     USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1918     SET_H_SYS_SR_F (opval);
1919     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1920   }
1921
1922 #undef FLD
1923 }
1924   NEXT (vpc);
1925
1926   CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */
1927 {
1928   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1929   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1930 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1931   int UNUSED written = 0;
1932   IADDR UNUSED pc = abuf->addr;
1933   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1934
1935   {
1936     USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1937     SET_H_SYS_SR_F (opval);
1938     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1939   }
1940
1941 #undef FLD
1942 }
1943   NEXT (vpc);
1944
1945   CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
1946 {
1947   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1948   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1949 #define FLD(f) abuf->fields.sfmt_l_sll.f
1950   int UNUSED written = 0;
1951   IADDR UNUSED pc = abuf->addr;
1952   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1953
1954   {
1955     USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1956     SET_H_SYS_SR_F (opval);
1957     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1958   }
1959
1960 #undef FLD
1961 }
1962   NEXT (vpc);
1963
1964   CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */
1965 {
1966   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1967   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1968 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1969   int UNUSED written = 0;
1970   IADDR UNUSED pc = abuf->addr;
1971   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1972
1973   {
1974     USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1975     SET_H_SYS_SR_F (opval);
1976     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1977   }
1978
1979 #undef FLD
1980 }
1981   NEXT (vpc);
1982
1983   CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
1984 {
1985   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1986   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1987 #define FLD(f) abuf->fields.sfmt_l_sll.f
1988   int UNUSED written = 0;
1989   IADDR UNUSED pc = abuf->addr;
1990   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1991
1992   {
1993     USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1994     SET_H_SYS_SR_F (opval);
1995     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1996   }
1997
1998 #undef FLD
1999 }
2000   NEXT (vpc);
2001
2002   CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */
2003 {
2004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2006 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2007   int UNUSED written = 0;
2008   IADDR UNUSED pc = abuf->addr;
2009   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2010
2011   {
2012     USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2013     SET_H_SYS_SR_F (opval);
2014     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2015   }
2016
2017 #undef FLD
2018 }
2019   NEXT (vpc);
2020
2021   CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
2022 {
2023   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2024   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2025 #define FLD(f) abuf->fields.sfmt_l_sll.f
2026   int UNUSED written = 0;
2027   IADDR UNUSED pc = abuf->addr;
2028   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2029
2030   {
2031     USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2032     SET_H_SYS_SR_F (opval);
2033     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2034   }
2035
2036 #undef FLD
2037 }
2038   NEXT (vpc);
2039
2040   CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */
2041 {
2042   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2043   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2044 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2045   int UNUSED written = 0;
2046   IADDR UNUSED pc = abuf->addr;
2047   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2048
2049   {
2050     USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2051     SET_H_SYS_SR_F (opval);
2052     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2053   }
2054
2055 #undef FLD
2056 }
2057   NEXT (vpc);
2058
2059   CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
2060 {
2061   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2062   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2063 #define FLD(f) abuf->fields.sfmt_l_sll.f
2064   int UNUSED written = 0;
2065   IADDR UNUSED pc = abuf->addr;
2066   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2067
2068   {
2069     USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2070     SET_H_SYS_SR_F (opval);
2071     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2072   }
2073
2074 #undef FLD
2075 }
2076   NEXT (vpc);
2077
2078   CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */
2079 {
2080   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2081   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2082 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2083   int UNUSED written = 0;
2084   IADDR UNUSED pc = abuf->addr;
2085   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2086
2087   {
2088     USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2089     SET_H_SYS_SR_F (opval);
2090     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2091   }
2092
2093 #undef FLD
2094 }
2095   NEXT (vpc);
2096
2097   CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
2098 {
2099   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2100   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2101 #define FLD(f) abuf->fields.sfmt_l_sll.f
2102   int UNUSED written = 0;
2103   IADDR UNUSED pc = abuf->addr;
2104   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2105
2106   {
2107     USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2108     SET_H_SYS_SR_F (opval);
2109     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2110   }
2111
2112 #undef FLD
2113 }
2114   NEXT (vpc);
2115
2116   CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */
2117 {
2118   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2119   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2120 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2121   int UNUSED written = 0;
2122   IADDR UNUSED pc = abuf->addr;
2123   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2124
2125   {
2126     USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2127     SET_H_SYS_SR_F (opval);
2128     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2129   }
2130
2131 #undef FLD
2132 }
2133   NEXT (vpc);
2134
2135   CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
2136 {
2137   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2138   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2139 #define FLD(f) abuf->fields.sfmt_l_sll.f
2140   int UNUSED written = 0;
2141   IADDR UNUSED pc = abuf->addr;
2142   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2143
2144   {
2145     USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2146     SET_H_SYS_SR_F (opval);
2147     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2148   }
2149
2150 #undef FLD
2151 }
2152   NEXT (vpc);
2153
2154   CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */
2155 {
2156   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2157   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2158 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2159   int UNUSED written = 0;
2160   IADDR UNUSED pc = abuf->addr;
2161   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2162
2163   {
2164     USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2165     SET_H_SYS_SR_F (opval);
2166     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2167   }
2168
2169 #undef FLD
2170 }
2171   NEXT (vpc);
2172
2173   CASE (sem, INSN_L_SFEQ) : /* l.sfeq $rA,$rB */
2174 {
2175   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2176   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2177 #define FLD(f) abuf->fields.sfmt_l_sll.f
2178   int UNUSED written = 0;
2179   IADDR UNUSED pc = abuf->addr;
2180   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2181
2182   {
2183     USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2184     SET_H_SYS_SR_F (opval);
2185     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2186   }
2187
2188 #undef FLD
2189 }
2190   NEXT (vpc);
2191
2192   CASE (sem, INSN_L_SFEQI) : /* l.sfeqi $rA,$simm16 */
2193 {
2194   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2195   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2196 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2197   int UNUSED written = 0;
2198   IADDR UNUSED pc = abuf->addr;
2199   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2200
2201   {
2202     USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2203     SET_H_SYS_SR_F (opval);
2204     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2205   }
2206
2207 #undef FLD
2208 }
2209   NEXT (vpc);
2210
2211   CASE (sem, INSN_L_SFNE) : /* l.sfne $rA,$rB */
2212 {
2213   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2214   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2215 #define FLD(f) abuf->fields.sfmt_l_sll.f
2216   int UNUSED written = 0;
2217   IADDR UNUSED pc = abuf->addr;
2218   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2219
2220   {
2221     USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2222     SET_H_SYS_SR_F (opval);
2223     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2224   }
2225
2226 #undef FLD
2227 }
2228   NEXT (vpc);
2229
2230   CASE (sem, INSN_L_SFNEI) : /* l.sfnei $rA,$simm16 */
2231 {
2232   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2233   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2234 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2235   int UNUSED written = 0;
2236   IADDR UNUSED pc = abuf->addr;
2237   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2238
2239   {
2240     USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2241     SET_H_SYS_SR_F (opval);
2242     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2243   }
2244
2245 #undef FLD
2246 }
2247   NEXT (vpc);
2248
2249   CASE (sem, INSN_L_MAC) : /* l.mac $rA,$rB */
2250 {
2251   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2252   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2253 #define FLD(f) abuf->fields.sfmt_l_sll.f
2254   int UNUSED written = 0;
2255   IADDR UNUSED pc = abuf->addr;
2256   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2257
2258 {
2259   SI tmp_prod;
2260   DI tmp_result;
2261   tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2262   tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
2263   {
2264     SI opval = SUBWORDDISI (tmp_result, 0);
2265     SET_H_MAC_MACHI (opval);
2266     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2267   }
2268   {
2269     SI opval = SUBWORDDISI (tmp_result, 1);
2270     SET_H_MAC_MACLO (opval);
2271     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2272   }
2273 }
2274
2275 #undef FLD
2276 }
2277   NEXT (vpc);
2278
2279   CASE (sem, INSN_L_MSB) : /* l.msb $rA,$rB */
2280 {
2281   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2282   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2283 #define FLD(f) abuf->fields.sfmt_l_sll.f
2284   int UNUSED written = 0;
2285   IADDR UNUSED pc = abuf->addr;
2286   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2287
2288 {
2289   SI tmp_prod;
2290   DI tmp_result;
2291   tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2292   tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
2293   {
2294     SI opval = SUBWORDDISI (tmp_result, 0);
2295     SET_H_MAC_MACHI (opval);
2296     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2297   }
2298   {
2299     SI opval = SUBWORDDISI (tmp_result, 1);
2300     SET_H_MAC_MACLO (opval);
2301     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2302   }
2303 }
2304
2305 #undef FLD
2306 }
2307   NEXT (vpc);
2308
2309   CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
2310 {
2311   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2312   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2313 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2314   int UNUSED written = 0;
2315   IADDR UNUSED pc = abuf->addr;
2316   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2317
2318 {
2319   SI tmp_prod;
2320   DI tmp_result;
2321   tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
2322   tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
2323   {
2324     SI opval = SUBWORDDISI (tmp_result, 0);
2325     SET_H_MAC_MACHI (opval);
2326     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2327   }
2328   {
2329     SI opval = SUBWORDDISI (tmp_result, 1);
2330     SET_H_MAC_MACLO (opval);
2331     CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2332   }
2333 }
2334
2335 #undef FLD
2336 }
2337   NEXT (vpc);
2338
2339   CASE (sem, INSN_L_CUST1) : /* l.cust1 */
2340 {
2341   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2342   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2343 #define FLD(f) abuf->fields.sfmt_empty.f
2344   int UNUSED written = 0;
2345   IADDR UNUSED pc = abuf->addr;
2346   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2347
2348 ((void) 0); /*nop*/
2349
2350 #undef FLD
2351 }
2352   NEXT (vpc);
2353
2354   CASE (sem, INSN_L_CUST2) : /* l.cust2 */
2355 {
2356   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2357   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2358 #define FLD(f) abuf->fields.sfmt_empty.f
2359   int UNUSED written = 0;
2360   IADDR UNUSED pc = abuf->addr;
2361   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2362
2363 ((void) 0); /*nop*/
2364
2365 #undef FLD
2366 }
2367   NEXT (vpc);
2368
2369   CASE (sem, INSN_L_CUST3) : /* l.cust3 */
2370 {
2371   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2372   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2373 #define FLD(f) abuf->fields.sfmt_empty.f
2374   int UNUSED written = 0;
2375   IADDR UNUSED pc = abuf->addr;
2376   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2377
2378 ((void) 0); /*nop*/
2379
2380 #undef FLD
2381 }
2382   NEXT (vpc);
2383
2384   CASE (sem, INSN_L_CUST4) : /* l.cust4 */
2385 {
2386   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2387   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2388 #define FLD(f) abuf->fields.sfmt_empty.f
2389   int UNUSED written = 0;
2390   IADDR UNUSED pc = abuf->addr;
2391   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2392
2393 ((void) 0); /*nop*/
2394
2395 #undef FLD
2396 }
2397   NEXT (vpc);
2398
2399   CASE (sem, INSN_L_CUST5) : /* l.cust5 */
2400 {
2401   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2402   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2403 #define FLD(f) abuf->fields.sfmt_empty.f
2404   int UNUSED written = 0;
2405   IADDR UNUSED pc = abuf->addr;
2406   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2407
2408 ((void) 0); /*nop*/
2409
2410 #undef FLD
2411 }
2412   NEXT (vpc);
2413
2414   CASE (sem, INSN_L_CUST6) : /* l.cust6 */
2415 {
2416   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2417   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2418 #define FLD(f) abuf->fields.sfmt_empty.f
2419   int UNUSED written = 0;
2420   IADDR UNUSED pc = abuf->addr;
2421   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2422
2423 ((void) 0); /*nop*/
2424
2425 #undef FLD
2426 }
2427   NEXT (vpc);
2428
2429   CASE (sem, INSN_L_CUST7) : /* l.cust7 */
2430 {
2431   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2433 #define FLD(f) abuf->fields.sfmt_empty.f
2434   int UNUSED written = 0;
2435   IADDR UNUSED pc = abuf->addr;
2436   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2437
2438 ((void) 0); /*nop*/
2439
2440 #undef FLD
2441 }
2442   NEXT (vpc);
2443
2444   CASE (sem, INSN_L_CUST8) : /* l.cust8 */
2445 {
2446   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2447   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2448 #define FLD(f) abuf->fields.sfmt_empty.f
2449   int UNUSED written = 0;
2450   IADDR UNUSED pc = abuf->addr;
2451   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2452
2453 ((void) 0); /*nop*/
2454
2455 #undef FLD
2456 }
2457   NEXT (vpc);
2458
2459   CASE (sem, INSN_LF_ADD_S) : /* lf.add.s $rDSF,$rASF,$rBSF */
2460 {
2461   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2462   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2463 #define FLD(f) abuf->fields.sfmt_l_sll.f
2464   int UNUSED written = 0;
2465   IADDR UNUSED pc = abuf->addr;
2466   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2467
2468   {
2469     SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2470     SET_H_FSR (FLD (f_r1), opval);
2471     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2472   }
2473
2474 #undef FLD
2475 }
2476   NEXT (vpc);
2477
2478   CASE (sem, INSN_LF_SUB_S) : /* lf.sub.s $rDSF,$rASF,$rBSF */
2479 {
2480   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2481   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2482 #define FLD(f) abuf->fields.sfmt_l_sll.f
2483   int UNUSED written = 0;
2484   IADDR UNUSED pc = abuf->addr;
2485   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2486
2487   {
2488     SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2489     SET_H_FSR (FLD (f_r1), opval);
2490     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2491   }
2492
2493 #undef FLD
2494 }
2495   NEXT (vpc);
2496
2497   CASE (sem, INSN_LF_MUL_S) : /* lf.mul.s $rDSF,$rASF,$rBSF */
2498 {
2499   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2500   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2501 #define FLD(f) abuf->fields.sfmt_l_sll.f
2502   int UNUSED written = 0;
2503   IADDR UNUSED pc = abuf->addr;
2504   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2505
2506   {
2507     SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2508     SET_H_FSR (FLD (f_r1), opval);
2509     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2510   }
2511
2512 #undef FLD
2513 }
2514   NEXT (vpc);
2515
2516   CASE (sem, INSN_LF_DIV_S) : /* lf.div.s $rDSF,$rASF,$rBSF */
2517 {
2518   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2519   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2520 #define FLD(f) abuf->fields.sfmt_l_sll.f
2521   int UNUSED written = 0;
2522   IADDR UNUSED pc = abuf->addr;
2523   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2524
2525   {
2526     SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2527     SET_H_FSR (FLD (f_r1), opval);
2528     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2529   }
2530
2531 #undef FLD
2532 }
2533   NEXT (vpc);
2534
2535   CASE (sem, INSN_LF_REM_S) : /* lf.rem.s $rDSF,$rASF,$rBSF */
2536 {
2537   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2538   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2539 #define FLD(f) abuf->fields.sfmt_l_sll.f
2540   int UNUSED written = 0;
2541   IADDR UNUSED pc = abuf->addr;
2542   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2543
2544   {
2545     SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2546     SET_H_FSR (FLD (f_r1), opval);
2547     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2548   }
2549
2550 #undef FLD
2551 }
2552   NEXT (vpc);
2553
2554   CASE (sem, INSN_LF_ITOF_S) : /* lf.itof.s $rDSF,$rA */
2555 {
2556   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2557   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2558 #define FLD(f) abuf->fields.sfmt_l_slli.f
2559   int UNUSED written = 0;
2560   IADDR UNUSED pc = abuf->addr;
2561   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2562
2563   {
2564     SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
2565     SET_H_FSR (FLD (f_r1), opval);
2566     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2567   }
2568
2569 #undef FLD
2570 }
2571   NEXT (vpc);
2572
2573   CASE (sem, INSN_LF_FTOI_S) : /* lf.ftoi.s $rD,$rASF */
2574 {
2575   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2576   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2577 #define FLD(f) abuf->fields.sfmt_l_slli.f
2578   int UNUSED written = 0;
2579   IADDR UNUSED pc = abuf->addr;
2580   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2581
2582   {
2583     SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
2584     SET_H_GPR (FLD (f_r1), opval);
2585     CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
2586   }
2587
2588 #undef FLD
2589 }
2590   NEXT (vpc);
2591
2592   CASE (sem, INSN_LF_EQ_S) : /* lf.sfeq.s $rASF,$rBSF */
2593 {
2594   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2595   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2596 #define FLD(f) abuf->fields.sfmt_l_sll.f
2597   int UNUSED written = 0;
2598   IADDR UNUSED pc = abuf->addr;
2599   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2600
2601   {
2602     BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2603     SET_H_SYS_SR_F (opval);
2604     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2605   }
2606
2607 #undef FLD
2608 }
2609   NEXT (vpc);
2610
2611   CASE (sem, INSN_LF_NE_S) : /* lf.sfne.s $rASF,$rBSF */
2612 {
2613   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2614   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2615 #define FLD(f) abuf->fields.sfmt_l_sll.f
2616   int UNUSED written = 0;
2617   IADDR UNUSED pc = abuf->addr;
2618   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2619
2620   {
2621     BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2622     SET_H_SYS_SR_F (opval);
2623     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2624   }
2625
2626 #undef FLD
2627 }
2628   NEXT (vpc);
2629
2630   CASE (sem, INSN_LF_GE_S) : /* lf.sfge.s $rASF,$rBSF */
2631 {
2632   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2633   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2634 #define FLD(f) abuf->fields.sfmt_l_sll.f
2635   int UNUSED written = 0;
2636   IADDR UNUSED pc = abuf->addr;
2637   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2638
2639   {
2640     BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2641     SET_H_SYS_SR_F (opval);
2642     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2643   }
2644
2645 #undef FLD
2646 }
2647   NEXT (vpc);
2648
2649   CASE (sem, INSN_LF_GT_S) : /* lf.sfgt.s $rASF,$rBSF */
2650 {
2651   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2652   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2653 #define FLD(f) abuf->fields.sfmt_l_sll.f
2654   int UNUSED written = 0;
2655   IADDR UNUSED pc = abuf->addr;
2656   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2657
2658   {
2659     BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2660     SET_H_SYS_SR_F (opval);
2661     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2662   }
2663
2664 #undef FLD
2665 }
2666   NEXT (vpc);
2667
2668   CASE (sem, INSN_LF_LT_S) : /* lf.sflt.s $rASF,$rBSF */
2669 {
2670   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2671   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2672 #define FLD(f) abuf->fields.sfmt_l_sll.f
2673   int UNUSED written = 0;
2674   IADDR UNUSED pc = abuf->addr;
2675   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2676
2677   {
2678     BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2679     SET_H_SYS_SR_F (opval);
2680     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2681   }
2682
2683 #undef FLD
2684 }
2685   NEXT (vpc);
2686
2687   CASE (sem, INSN_LF_LE_S) : /* lf.sfle.s $rASF,$rBSF */
2688 {
2689   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2690   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2691 #define FLD(f) abuf->fields.sfmt_l_sll.f
2692   int UNUSED written = 0;
2693   IADDR UNUSED pc = abuf->addr;
2694   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2695
2696   {
2697     BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2698     SET_H_SYS_SR_F (opval);
2699     CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2700   }
2701
2702 #undef FLD
2703 }
2704   NEXT (vpc);
2705
2706   CASE (sem, INSN_LF_MADD_S) : /* lf.madd.s $rDSF,$rASF,$rBSF */
2707 {
2708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2710 #define FLD(f) abuf->fields.sfmt_l_sll.f
2711   int UNUSED written = 0;
2712   IADDR UNUSED pc = abuf->addr;
2713   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2714
2715   {
2716     SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
2717     SET_H_FSR (FLD (f_r1), opval);
2718     CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2719   }
2720
2721 #undef FLD
2722 }
2723   NEXT (vpc);
2724
2725   CASE (sem, INSN_LF_CUST1_S) : /* lf.cust1.s $rASF,$rBSF */
2726 {
2727   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2728   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2729 #define FLD(f) abuf->fields.sfmt_empty.f
2730   int UNUSED written = 0;
2731   IADDR UNUSED pc = abuf->addr;
2732   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2733
2734 ((void) 0); /*nop*/
2735
2736 #undef FLD
2737 }
2738   NEXT (vpc);
2739
2740
2741     }
2742   ENDSWITCH (sem) /* End of semantic switch.  */
2743
2744   /* At this point `vpc' contains the next insn to execute.  */
2745 }
2746
2747 #undef DEFINE_SWITCH
2748 #endif /* DEFINE_SWITCH */