1 /* Main simulator entry points specific to the OR1K.
2 Copyright (C) 2017-2021 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* This must come before any other includes. */
23 #include "sim-options.h"
24 #include "libiberty.h"
30 static void free_state (SIM_DESC
);
33 /* Cover function of sim_state_free to free the cpu buffers as well. */
36 free_state (SIM_DESC sd
)
38 if (STATE_MODULES (sd
) != NULL
)
39 sim_module_uninstall (sd
);
40 sim_cpu_free_all (sd
);
44 /* Defaults for user passed arguments. */
45 static const USI or1k_default_vr
= 0x0;
46 static const USI or1k_default_upr
= 0x0
47 | SPR_FIELD_MASK_SYS_UPR_UP
;
48 static const USI or1k_default_cpucfgr
= 0x0
49 | SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
50 | SPR_FIELD_MASK_SYS_CPUCFGR_OF32S
;
54 static UWI or1k_cpucfgr
;
60 OPTION_OR1K_CPUCFGR
= OPTION_START
,
63 /* Setup help and handlers for the user defined arguments. */
64 DECLARE_OPTION_HANDLER (or1k_option_handler
);
66 static const OPTION or1k_options
[] = {
67 {{"or1k-cpucfgr", required_argument
, NULL
, OPTION_OR1K_CPUCFGR
},
68 '\0', "INTEGER|default", "Set simulator CPUCFGR value",
70 {{"or1k-vr", required_argument
, NULL
, OPTION_OR1K_VR
},
71 '\0', "INTEGER|default", "Set simulator VR value",
73 {{"or1k-upr", required_argument
, NULL
, OPTION_OR1K_UPR
},
74 '\0', "INTEGER|default", "Set simulator UPR value",
76 {{NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
79 /* Handler for parsing user defined arguments. Currently we support
80 configuring some of the CPU implementation specific registers including
81 the Version Register (VR), the Unit Present Register (UPR) and the CPU
82 Configuration Register (CPUCFGR). */
84 or1k_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
90 if (strcmp ("default", arg
) == 0)
91 or1k_vr
= or1k_default_vr
;
97 n
= strtoull (arg
, &endptr
, 0);
98 if (*arg
!= '\0' && *endptr
== '\0')
105 case OPTION_OR1K_UPR
:
106 if (strcmp ("default", arg
) == 0)
107 or1k_upr
= or1k_default_upr
;
110 unsigned long long n
;
113 n
= strtoull (arg
, &endptr
, 0);
114 if (*arg
!= '\0' && *endptr
== '\0')
119 (sd
, "invalid argument to option --or1k-upr: `%s'\n", arg
);
125 case OPTION_OR1K_CPUCFGR
:
126 if (strcmp ("default", arg
) == 0)
127 or1k_cpucfgr
= or1k_default_cpucfgr
;
130 unsigned long long n
;
133 n
= strtoull (arg
, &endptr
, 0);
134 if (*arg
!= '\0' && *endptr
== '\0')
139 (sd
, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg
);
146 sim_io_eprintf (sd
, "Unknown or1k option %d\n", opt
);
153 extern const SIM_MACH
* const or1k_sim_machs
[];
155 /* Create an instance of the simulator. */
158 sim_open (SIM_OPEN_KIND kind
, host_callback
*callback
, struct bfd
*abfd
,
161 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
165 /* Set default options before parsing user options. */
166 STATE_MACHS (sd
) = or1k_sim_machs
;
167 STATE_MODEL_NAME (sd
) = "or1200";
168 current_target_byte_order
= BFD_ENDIAN_BIG
;
170 /* The cpu data is kept in a separately allocated chunk of memory. */
171 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
177 /* Perform initial sim setups. */
178 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
184 or1k_upr
= or1k_default_upr
;
185 or1k_vr
= or1k_default_vr
;
186 or1k_cpucfgr
= or1k_default_cpucfgr
;
187 sim_add_option_table (sd
, NULL
, or1k_options
);
189 /* Parse the user passed arguments. */
190 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
196 /* Allocate core managed memory if none specified by user.
197 Use address 4 here in case the user wanted address 0 unmapped. */
198 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
200 sim_do_commandf (sd
, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE
);
203 /* Check for/establish the reference program image. */
204 if (sim_analyze_program (sd
,
205 (STATE_PROG_ARGV (sd
) != NULL
206 ? *STATE_PROG_ARGV (sd
)
207 : NULL
), abfd
) != SIM_RC_OK
)
213 /* Establish any remaining configuration options. */
214 if (sim_config (sd
) != SIM_RC_OK
)
220 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
226 /* Make sure delay slot mode is consistent with the loaded binary. */
227 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_or1knd
)
228 or1k_cpucfgr
|= SPR_FIELD_MASK_SYS_CPUCFGR_ND
;
230 or1k_cpucfgr
&= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND
;
232 /* Open a copy of the cpu descriptor table and initialize the
233 disassembler. These initialization functions are generated by CGEN
234 using the binutils scheme cpu description files. */
237 or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd
)->printable_name
,
239 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
241 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
242 CPU_CPU_DESC (cpu
) = cd
;
243 CPU_DISASSEMBLER (cpu
) = sim_cgen_disassemble_insn
;
245 or1k_cgen_init_dis (cd
);
248 /* Do some final OpenRISC sim specific initializations. */
249 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
251 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
252 /* Only needed for profiling, but the structure member is small. */
253 memset (CPU_OR1K_MISC_PROFILE (cpu
), 0,
254 sizeof (*CPU_OR1K_MISC_PROFILE (cpu
)));
256 or1k_cpu_init (sd
, cpu
, or1k_vr
, or1k_upr
, or1k_cpucfgr
);
264 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
265 char * const *argv
, char * const *envp
)
267 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
271 addr
= bfd_get_start_address (abfd
);
274 sim_pc_set (current_cpu
, addr
);