sim/ppc/cpu.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _CPU_H_
  23 #define _CPU_H_
  24
  25 #ifndef INLINE_CPU
  26 #define INLINE_CPU
  27 #endif
  28
  29 #include "basics.h"
  30 #include "registers.h"
  31 #include "device_tree.h"
  32 #include "corefile.h"
  33 #include "vm.h"
  34 #include "events.h"
  35 #include "interrupts.h"
  36 #include "psim.h"
  37 #include "icache.h"
  38 #include "itable.h"
  39 #include "mon.h"
  40
  41
  42 /* typedef struct _cpu cpu;
  43
  44    Declared in basics.h because it is used opaquely throughout the
  45    code */
  46
  47
  48 /* Create a cpu object */
  49
  50 INLINE_CPU cpu *cpu_create
  51 (psim *system,
  52  core *memory,
  53  event_queue *events,
  54  cpu_mon *monitor,
  55  int cpu_nr);
  56
  57 INLINE_CPU void cpu_init
  58 (cpu *processor);
  59
  60 /* Find our way home */
  61
  62 INLINE_CPU psim *cpu_system
  63 (cpu *processor);
  64
  65 INLINE_CPU cpu_mon *cpu_monitor
  66 (cpu *processor);
  67
  68 INLINE_CPU int cpu_nr
  69 (cpu *processor);
  70
  71 INLINE_CPU event_queue *cpu_event_queue
  72 (cpu *processor);
  73
  74
  75 /* The processors local concept of time */
  76
  77 INLINE_CPU signed64 cpu_get_time_base
  78 (cpu *processor);
  79
  80 INLINE_CPU void cpu_set_time_base
  81 (cpu *processor,
  82  signed64 time_base);
  83
  84 INLINE_CPU signed32 cpu_get_decrementer
  85 (cpu *processor);
  86
  87 INLINE_CPU void cpu_set_decrementer
  88 (cpu *processor,
  89  signed32 decrementer);
  90
  91
  92 /* manipulate the program counter
  93
  94    The program counter is not included in the register file.  Instead
  95    it is extracted and then later restored (set, reset, halt).  This
  96    is to give the user of the cpu (and the compiler) the chance to
  97    minimize the need to load/store the cpu's PC value.  (Especially in
  98    the case of a single processor) */
  99
 100 INLINE_CPU void cpu_set_program_counter
 101 (cpu *processor,
 102  unsigned_word new_program_counter);
 103
 104 INLINE_CPU unsigned_word cpu_get_program_counter
 105 (cpu *processor);
 106
 107 INLINE_CPU void cpu_restart
 108 (cpu *processor,
 109  unsigned_word nia);
 110
 111 INLINE_CPU void cpu_halt
 112 (cpu *processor,
 113  unsigned_word nia,
 114  stop_reason reason,
 115  int signal);
 116
 117
 118 #if WITH_IDECODE_CACHE_SIZE
 119 /* Return the cache entry that matches the given CIA.  No guarentee
 120    that the cache entry actually contains the instruction for that
 121    address */
 122
 123 INLINE_CPU idecode_cache *cpu_icache_entry
 124 (cpu *processor,
 125  unsigned_word cia);
 126
 127 INLINE_CPU void cpu_flush_icache
 128 (cpu *processor);
 129 #endif
 130
 131
 132 /* reveal the processors VM:
 133
 134    At first sight it may seem better to, instead of exposing the cpu's
 135    inner vm maps, to have the cpu its self provide memory manipulation
 136    functions. (eg cpu_instruction_fetch() cpu_data_read_4())
 137
 138    Unfortunatly in addition to these functions is the need (for the
 139    debugger) to be able to read/write to memory in ways that violate
 140    the vm protection (eg store breakpoint instruction in the
 141    instruction map). */
 142
 143 INLINE_CPU vm_data_map *cpu_data_map
 144 (cpu *processor);
 145
 146 INLINE_CPU vm_instruction_map *cpu_instruction_map
 147 (cpu *processor);
 148
 149
 150 /* grant access to the reservation information */
 151 typedef struct _memory_reservation {
 152   int valid;
 153   unsigned_word addr;
 154   unsigned_word data;
 155 } memory_reservation;
 156
 157 INLINE_CPU memory_reservation *cpu_reservation
 158 (cpu *processor);
 159
 160
 161 INLINE_CPU void cpu_print_info
 162 (cpu *processor,
 163  int verbose);
 164
 165
 166 /* Registers:
 167
 168    This model exploits the PowerPC's requirement for a synchronization
 169    to occure after (or before) the update of any context controlling
 170    register.  All context sync points must call the sync function
 171    below to when ever a synchronization point is reached */
 172
 173 INLINE_CPU registers *cpu_registers
 174 (cpu *processor);
 175
 176 INLINE_CPU void cpu_synchronize_context
 177 (cpu *processor);
 178
 179 #define IS_PROBLEM_STATE(PROCESSOR) \
 180 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 181  ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \
 182  : 1)
 183
 184 #define IS_64BIT_MODE(PROCESSOR) \
 185 (WITH_TARGET_WORD_BITSIZE == 64 \
 186  ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 187     ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \
 188     : 1) \
 189  : 0)
 190
 191 #define IS_FP_AVAILABLE(PROCESSOR) \
 192 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 193  ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \
 194  : 1)
 195
 196 #endif