sim/ppc/cpu.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _CPU_H_
  23 #define _CPU_H_
  24
  25 #ifndef INLINE_CPU
  26 #define INLINE_CPU
  27 #endif
  28
  29 #include "basics.h"
  30 #include "registers.h"
  31 #include "device_tree.h"
  32 #include "corefile.h"
  33 #include "vm.h"
  34 #include "events.h"
  35 #include "interrupts.h"
  36 #include "psim.h"
  37 #include "icache.h"
  38 #include "itable.h"
  39 #include "mon.h"
  40 #include "function_unit.h"
  41
  42
  43 /* typedef struct _cpu cpu;
  44
  45    Declared in basics.h because it is used opaquely throughout the
  46    code */
  47
  48
  49 /* Create a cpu object */
  50
  51 INLINE_CPU cpu *cpu_create
  52 (psim *system,
  53  core *memory,
  54  event_queue *events,
  55  cpu_mon *monitor,
  56  int cpu_nr);
  57
  58 INLINE_CPU void cpu_init
  59 (cpu *processor);
  60
  61 /* Find our way home */
  62
  63 INLINE_CPU psim *cpu_system
  64 (cpu *processor);
  65
  66 INLINE_CPU cpu_mon *cpu_monitor
  67 (cpu *processor);
  68
  69 INLINE_CPU int cpu_nr
  70 (cpu *processor);
  71
  72 INLINE_CPU event_queue *cpu_event_queue
  73 (cpu *processor);
  74
  75
  76 /* The processors local concept of time */
  77
  78 INLINE_CPU signed64 cpu_get_time_base
  79 (cpu *processor);
  80
  81 INLINE_CPU void cpu_set_time_base
  82 (cpu *processor,
  83  signed64 time_base);
  84
  85 INLINE_CPU signed32 cpu_get_decrementer
  86 (cpu *processor);
  87
  88 INLINE_CPU void cpu_set_decrementer
  89 (cpu *processor,
  90  signed32 decrementer);
  91
  92
  93 /* manipulate the program counter
  94
  95    The program counter is not included in the register file.  Instead
  96    it is extracted and then later restored (set, reset, halt).  This
  97    is to give the user of the cpu (and the compiler) the chance to
  98    minimize the need to load/store the cpu's PC value.  (Especially in
  99    the case of a single processor) */
 100
 101 INLINE_CPU void cpu_set_program_counter
 102 (cpu *processor,
 103  unsigned_word new_program_counter);
 104
 105 INLINE_CPU unsigned_word cpu_get_program_counter
 106 (cpu *processor);
 107
 108 INLINE_CPU void cpu_restart
 109 (cpu *processor,
 110  unsigned_word nia);
 111
 112 INLINE_CPU void cpu_halt
 113 (cpu *processor,
 114  unsigned_word nia,
 115  stop_reason reason,
 116  int signal);
 117
 118
 119 #if WITH_IDECODE_CACHE_SIZE
 120 /* Return the cache entry that matches the given CIA.  No guarentee
 121    that the cache entry actually contains the instruction for that
 122    address */
 123
 124 INLINE_CPU idecode_cache *cpu_icache_entry
 125 (cpu *processor,
 126  unsigned_word cia);
 127
 128 INLINE_CPU void cpu_flush_icache
 129 (cpu *processor);
 130 #endif
 131
 132
 133 /* reveal the processors VM:
 134
 135    At first sight it may seem better to, instead of exposing the cpu's
 136    inner vm maps, to have the cpu its self provide memory manipulation
 137    functions. (eg cpu_instruction_fetch() cpu_data_read_4())
 138
 139    Unfortunatly in addition to these functions is the need (for the
 140    debugger) to be able to read/write to memory in ways that violate
 141    the vm protection (eg store breakpoint instruction in the
 142    instruction map). */
 143
 144 INLINE_CPU vm_data_map *cpu_data_map
 145 (cpu *processor);
 146
 147 INLINE_CPU vm_instruction_map *cpu_instruction_map
 148 (cpu *processor);
 149
 150
 151 /* grant access to the reservation information */
 152 typedef struct _memory_reservation {
 153   int valid;
 154   unsigned_word addr;
 155   unsigned_word data;
 156 } memory_reservation;
 157
 158 INLINE_CPU memory_reservation *cpu_reservation
 159 (cpu *processor);
 160
 161
 162 INLINE_CPU void cpu_print_info
 163 (cpu *processor,
 164  int verbose);
 165
 166
 167 /* Registers:
 168
 169    This model exploits the PowerPC's requirement for a synchronization
 170    to occure after (or before) the update of any context controlling
 171    register.  All context sync points must call the sync function
 172    below to when ever a synchronization point is reached */
 173
 174 INLINE_CPU registers *cpu_registers
 175 (cpu *processor);
 176
 177 INLINE_CPU void cpu_synchronize_context
 178 (cpu *processor);
 179
 180 INLINE_CPU function_unit *cpu_function_unit
 181 (cpu *processor);
 182
 183 #define IS_PROBLEM_STATE(PROCESSOR) \
 184 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 185  ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \
 186  : 1)
 187
 188 #define IS_64BIT_MODE(PROCESSOR) \
 189 (WITH_TARGET_WORD_BITSIZE == 64 \
 190  ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 191     ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \
 192     : 1) \
 193  : 0)
 194
 195 #define IS_FP_AVAILABLE(PROCESSOR) \
 196 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
 197  ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \
 198  : 1)
 199
 200 #endif