1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 #include "registers.h"
31 #include "device_tree.h"
35 #include "interrupts.h"
42 /* typedef struct _cpu cpu;
44 Declared in basics.h because it is used opaquely throughout the
48 /* Create a cpu object */
50 INLINE_CPU cpu
*cpu_create
57 INLINE_CPU
void cpu_init
60 /* Find our way home */
62 INLINE_CPU psim
*cpu_system
65 INLINE_CPU cpu_mon
*cpu_monitor
71 INLINE_CPU event_queue
*cpu_event_queue
75 /* The processors local concept of time */
77 INLINE_CPU signed64 cpu_get_time_base
80 INLINE_CPU
void cpu_set_time_base
84 INLINE_CPU signed32 cpu_get_decrementer
87 INLINE_CPU
void cpu_set_decrementer
89 signed32 decrementer
);
92 /* manipulate the program counter
94 The program counter is not included in the register file. Instead
95 it is extracted and then later restored (set, reset, halt). This
96 is to give the user of the cpu (and the compiler) the chance to
97 minimize the need to load/store the cpu's PC value. (Especially in
98 the case of a single processor) */
100 INLINE_CPU
void cpu_set_program_counter
102 unsigned_word new_program_counter
);
104 INLINE_CPU unsigned_word cpu_get_program_counter
107 INLINE_CPU
void cpu_restart
111 INLINE_CPU
void cpu_halt
118 #if WITH_IDECODE_CACHE_SIZE
119 /* Return the cache entry that matches the given CIA. No guarentee
120 that the cache entry actually contains the instruction for that
123 INLINE_CPU idecode_cache
*cpu_icache_entry
127 INLINE_CPU
void cpu_flush_icache
132 /* reveal the processors VM:
134 At first sight it may seem better to, instead of exposing the cpu's
135 inner vm maps, to have the cpu its self provide memory manipulation
136 functions. (eg cpu_instruction_fetch() cpu_data_read_4())
138 Unfortunatly in addition to these functions is the need (for the
139 debugger) to be able to read/write to memory in ways that violate
140 the vm protection (eg store breakpoint instruction in the
143 INLINE_CPU vm_data_map
*cpu_data_map
146 INLINE_CPU vm_instruction_map
*cpu_instruction_map
150 /* grant access to the reservation information */
151 typedef struct _memory_reservation
{
155 } memory_reservation
;
157 INLINE_CPU memory_reservation
*cpu_reservation
161 INLINE_CPU
void cpu_print_info
168 This model exploits the PowerPC's requirement for a synchronization
169 to occure after (or before) the update of any context controlling
170 register. All context sync points must call the sync function
171 below to when ever a synchronization point is reached */
173 INLINE_CPU registers
*cpu_registers
176 INLINE_CPU
void cpu_synchronize_context
179 #define IS_PROBLEM_STATE(PROCESSOR) \
180 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
181 ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \
184 #define IS_64BIT_MODE(PROCESSOR) \
185 (WITH_TARGET_WORD_BITSIZE == 64 \
186 ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
187 ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \
191 #define IS_FP_AVAILABLE(PROCESSOR) \
192 (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \
193 ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \