sim/ppc/e500_expression.h

   1 /* e500 expression macros, for PSIM, the PowerPC simulator.
   2
   3    Copyright 2003 Free Software Foundation, Inc.
   4
   5    Contributed by Red Hat Inc; developed under contract from Motorola.
   6    Written by matthew green <mrg@redhat.com>.
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330,
  23    Boston, MA 02111-1307, USA.  */
  24
  25 /* e500 register dance */
  26 #define EV_SET_REG4(sh, sl, h0, h1, h2, h3) do { \
  27         (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \
  28         (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \
  29 } while (0)
  30 #define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \
  31         (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \
  32         (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \
  33         ACC = ((unsigned64)(sh) << 32) | (sl & 0xffffffff); \
  34 } while (0)
  35
  36 #define EV_SET_REG2(sh, sl, dh, dl) do { \
  37         (sh) = (dh) & 0xffffffff; \
  38         (sl) = (dl) & 0xffffffff; \
  39 } while (0)
  40 #define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \
  41         (sh) = (dh) & 0xffffffff; \
  42         (sl) = (dl) & 0xffffffff; \
  43         ACC = ((unsigned64)(sh) << 32) | ((sl) & 0xffffffff); \
  44 } while (0)
  45
  46 #define EV_SET_REG1(sh, sl, d) do { \
  47         (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \
  48         (sl) = (d) & 0xffffffff; \
  49 } while (0)
  50 #define EV_SET_REG1_ACC(sh, sl, d) do { \
  51         (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \
  52         (sl) = (d) & 0xffffffff; \
  53         ACC = (d); \
  54 } while (0)
  55
  56 #define EV_SET_REG(s, d) do { \
  57         (s) = (d) & 0xffffffff; \
  58 } while (0)
  59
  60 /* get the low or high half word of a word */
  61 #define EV_LOHALF(x)    ((unsigned32)(x) & 0xffff)
  62 #define EV_HIHALF(x)    (((unsigned32)(x) >> 16) & 0xffff)
  63
  64 /* partially visible accumulator accessors */
  65 #define EV_SET_ACC(rh, rl) \
  66         ACC = ((unsigned64)(rh) << 32) | ((rl) & 0xffffffff)
  67
  68 #define EV_ACCLOW       (ACC & 0xffffffff)
  69 #define EV_ACCHIGH      ((ACC >> 32) & 0xffffffff)
  70
  71 /* bit manipulation macros needed for e500 SPE */
  72 #define EV_BITREVERSE16(x) \
  73                   (((x) & 0x0001) << 15) \
  74                 | (((x) & 0x0002) << 13) \
  75                 | (((x) & 0x0004) << 11) \
  76                 | (((x) & 0x0008) << 9) \
  77                 | (((x) & 0x0010) << 7) \
  78                 | (((x) & 0x0020) << 5) \
  79                 | (((x) & 0x0040) << 3) \
  80                 | (((x) & 0x0080) << 1) \
  81                 | (((x) & 0x0100) >> 1) \
  82                 | (((x) & 0x0200) >> 3) \
  83                 | (((x) & 0x0400) >> 5) \
  84                 | (((x) & 0x0800) >> 7) \
  85                 | (((x) & 0x1000) >> 9) \
  86                 | (((x) & 0x2000) >> 11) \
  87                 | (((x) & 0x4000) >> 13) \
  88                 | (((x) & 0x8000) >> 15)
  89
  90 /* saturation helpers */
  91 #define EV_MUL16_SSF(a,b)       ((signed64)((signed32)(signed16)(a) * (signed32)(signed16)(b)) << 1)
  92 /* this one loses the top sign bit; be careful */
  93 #define EV_MUL32_SSF(a,b)       (((signed64)(signed32)(a) * (signed64)(signed32)(b)) << 1)
  94 #define EV_SAT_P_S32(x)         ((((signed64)(x)) < -0x80000000LL) || (((signed64)(x)) > 0x7fffffffLL))
  95 #define EV_SAT_P_U32(x)         ((((signed64)(x)) < -0LL) || (((signed64)(x)) > 0xffffffffLL))
  96
  97 #define EV_SATURATE(flag, sat_val, val) \
  98         ((flag) ? (sat_val) : (val))
  99
 100 #define EV_SATURATE_ACC(flag, sign, negative_sat_val, positive_sat_val, val) \
 101         ((flag) ? ((((sign) >> 63) & 1) ? (negative_sat_val) : (positive_sat_val)) : (val))
 102
 103 /* SPEFSCR handling.  */
 104
 105 /* These bits must be clear.  */
 106 #define EV_SPEFSCR_MASK (BIT(40) | BIT(41) | spefscr_mode | BIT(56))
 107
 108 /* The Inexact and Divide by zero sticky bits are based on others.  */
 109 #define EV_SET_SPEFSCR(bits) do { \
 110   int finxs = (bits) & (spefscr_fgh|spefscr_fxh|spefscr_fg|spefscr_fx); \
 111   int fdbzs = (bits) & (spefscr_fdbzh|spefscr_fdbz); \
 112   SPREG(spr_spefscr) = ((bits) & ~EV_SPEFSCR_MASK) | \
 113                        (finxs ? spefscr_finxs : 0) | \
 114                        (fdbzs ? spefscr_fdbzs : 0); \
 115 } while (0)
 116
 117 #define EV_SET_SPEFSCR_BITS(s) \
 118   EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s))
 119
 120 #define EV_SET_SPEFSCR_OV(l,h) do { \
 121         unsigned32 _sPefScR = SPREG(spr_spefscr); \
 122         if (l) \
 123           _sPefScR |= spefscr_ov | spefscr_sov; \
 124         else \
 125           _sPefScR &= ~spefscr_ov; \
 126         if (h) \
 127           _sPefScR |= spefscr_ovh | spefscr_sovh; \
 128         else \
 129           _sPefScR &= ~spefscr_ovh; \
 130         EV_SET_SPEFSCR(_sPefScR); \
 131 } while (0)
 132
 133 /* SPE floating point helpers.  */
 134
 135 #define EV_PMAX 0x7f7fffff
 136 #define EV_NMAX 0xff7fffff
 137 #define EV_PMIN 0x00800001
 138 #define EV_NMIN 0x80800001
 139
 140 #define EV_IS_INFDENORMNAN(x) \
 141         (sim_fpu_is_infinity(x) || sim_fpu_is_denorm(x) || sim_fpu_is_nan(x))
 142
 143 /* These aren't used (yet?)  For now, SPU is always enabled.
 144    Would be nice if they were generated by igen for e500.  */
 145 #define SPU_BEGIN \
 146 { \
 147   if (MSR & msr_e500_spu_enable) { \
 148
 149 #define SPU_END \
 150   } else { \
 151     /* FIXME: raise SPU unavailable.  */ \
 152   } \
 153 }
 154
 155 /* These are also not yet used.  */
 156 #define SPU_FP_BEGIN \
 157 {
 158
 159 #define SPU_FP_END \
 160   { \
 161      unsigned s = SPEFSCR; \
 162      /* Check SPEFSCR; raise exceptions if any required.  */ \
 163      if (((spefscr_finxe || spefscr_finve) \
 164          && (s & (spefscr_finvh|spefscr_finv))) \
 165       || ((spefscr_finxe || spefscr_fdbze) \
 166          && (s & (spefscr_fdbzh|spefscr_fdbz))) \
 167       || ((spefscr_finxe || spefscr_funfe) \
 168          && (s & (spefscr_funfh|spefscr_funf))) \
 169       || ((spefscr_finxe || spefscr_fovfe) \
 170          && (s & (spefscr_fovfh|spefscr_fovf)))) \
 171        /* FIXME: raise exceptions.  */; \
 172    } \
 173 }