1 /* This file is part of the program psim.
3 Copyright 1994, 1995, 1996, 1997, 2003 Andrew Cagney
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, see <http://www.gnu.org/licenses/>.
20 /* Additional, and optional expressions. */
22 #include "altivec_expression.h"
25 #include "e500_expression.h"
28 /* 32bit target expressions:
30 Each calculation is performed three times using each of the
31 signed64, unsigned64 and long integer types. The macro ALU_END
32 (in _ALU_RESULT_VAL) then selects which of the three alternative
33 results will be used in the final assignment of the target
34 register. As this selection is determined at compile time by
35 fields in the instruction (OE, EA, Rc) the compiler has sufficient
36 information to firstly simplify the selection code into a single
37 case and then back anotate the equations and hence eliminate any
38 resulting dead code. That dead code being the calculations that,
39 as it turned out were not in the end needed.
41 64bit arrithemetic is used firstly because it allows the use of
42 gcc's efficient long long operators (typically efficiently output
43 inline) and secondly because the resultant answer will contain in
44 the low 32bits the answer while in the high 32bits is either carry
45 or status information. */
47 /* 64bit target expressions:
49 Unfortunatly 128bit arrithemetic isn't that common. Consequently
50 the 32/64 bit trick can not be used. Instead all calculations are
51 required to retain carry/overflow information in separate
52 variables. Even with this restriction it is still possible for the
53 trick of letting the compiler discard the calculation of unneeded
57 /* Macro's to type cast 32bit constants to 64bits */
58 #define SIGNED64(val) ((signed64)(signed32)(val))
59 #define UNSIGNED64(val) ((unsigned64)(unsigned32)(val))
62 /* Start a section of ALU code */
64 #define ALU_BEGIN(val) \
66 natural_word alu_val; \
67 unsigned64 alu_carry_val; \
68 signed64 alu_overflow_val; \
72 /* assign the result to the target register */
74 #define ALU_END(TARG,CA,OE,Rc) \
75 { /* select the result to use */ \
76 signed_word const alu_result = _ALU_RESULT_VAL(CA,OE,Rc); \
77 /* determine the overflow bit if needed */ \
79 if ((((unsigned64)(alu_overflow_val & BIT64(0))) \
81 == (alu_overflow_val & BIT64(32))) \
82 XER &= (~xer_overflow); \
84 XER |= (xer_summary_overflow | xer_overflow); \
86 /* Update the carry bit if needed */ \
88 XER = ((XER & ~xer_carry) \
89 | SHUFFLED32((alu_carry_val >> 32), 31, xer_carry_bit)); \
90 /* if (alu_carry_val & BIT64(31)) \
93 XER &= (~xer_carry); */ \
95 TRACE(trace_alu, (" Result = %ld (0x%lx), XER = %ld\n", \
96 (long)alu_result, (long)alu_result, (long)XER)); \
97 /* Update the Result Conditions if needed */ \
98 CR0_COMPARE(alu_result, 0, Rc); \
99 /* assign targ same */ \
103 /* select the result from the different options */
105 #define _ALU_RESULT_VAL(CA,OE,Rc) (WITH_TARGET_WORD_BITSIZE == 64 \
114 /* More basic alu operations */
115 #if (WITH_TARGET_WORD_BITSIZE == 64)
116 #define ALU_SET(val) \
119 alu_carry_val = ((unsigned64)alu_val) >> 32; \
120 alu_overflow_val = ((signed64)alu_val) >> 32; \
123 #if (WITH_TARGET_WORD_BITSIZE == 32)
124 #define ALU_SET(val) \
127 alu_carry_val = (unsigned32)(alu_val); \
128 alu_overflow_val = (signed32)(alu_val); \
132 #if (WITH_TARGET_WORD_BITSIZE == 64)
133 #define ALU_ADD(val) \
135 unsigned64 alu_lo = (UNSIGNED64(alu_val) \
136 + UNSIGNED64(val)); \
137 signed alu_carry = ((alu_lo & BIT(31)) != 0); \
138 alu_carry_val = (alu_carry_val \
139 + UNSIGNED64(EXTRACTED(val, 0, 31)) \
141 alu_overflow_val = (alu_overflow_val \
142 + SIGNED64(EXTRACTED(val, 0, 31)) \
144 alu_val = alu_val + val; \
147 #if (WITH_TARGET_WORD_BITSIZE == 32)
148 #define ALU_ADD(val) \
151 alu_carry_val += (unsigned32)(val); \
152 alu_overflow_val += (signed32)(val); \
157 #if (WITH_TARGET_WORD_BITSIZE == 64)
160 signed carry = MASKED32(XER, xer_carry_bit, xer_carry_bit) != 0; \
164 #if (WITH_TARGET_WORD_BITSIZE == 32)
167 signed carry = MASKED32(XER, xer_carry_bit, xer_carry_bit) != 0; \
174 #if (WITH_TARGET_WORD_BITSIZE == 64)
176 #if (WITH_TARGET_WORD_BITSIZE == 32)
177 #define ALU_SUB(val) \
180 alu_carry_val -= (unsigned32)(val); \
181 alu_overflow_val -= (signed32)(val); \
186 #if (WITH_TARGET_WORD_BITSIZE == 64)
188 #if (WITH_TARGET_WORD_BITSIZE == 32)
189 #define ALU_OR(val) \
192 alu_carry_val = (unsigned32)(alu_val); \
193 alu_overflow_val = (signed32)(alu_val); \
198 #if (WITH_TARGET_WORD_BITSIZE == 64)
200 #if (WITH_TARGET_WORD_BITSIZE == 32)
201 #define ALU_XOR(val) \
204 alu_carry_val = (unsigned32)(alu_val); \
205 alu_overflow_val = (signed32)(alu_val); \
211 #if (WITH_TARGET_WORD_BITSIZE == 64)
213 #if (WITH_TARGET_WORD_BITSIZE == 32)
216 alu_val = -alu_val; \
217 alu_carry_val = -alu_carry_val; \
218 alu_overflow_val = -alu_overflow_val; \
224 #if (WITH_TARGET_WORD_BITSIZE == 64)
226 #if (WITH_TARGET_WORD_BITSIZE == 32)
227 #define ALU_AND(val) \
230 alu_carry_val = (unsigned32)(alu_val); \
231 alu_overflow_val = (signed32)(alu_val); \
236 #if (WITH_TARGET_WORD_BITSIZE == 64)
239 signed64 new_alu_val = ~alu_val; \
240 ALU_SET(new_alu_val); \
243 #if (WITH_TARGET_WORD_BITSIZE == 32)
246 signed new_alu_val = ~alu_val; \
247 ALU_SET(new_alu_val); \
252 /* Macros for updating the condition register */
254 #define CR1_UPDATE(Rc) \
257 CR_SET(1, EXTRACTED32(FPSCR, fpscr_fx_bit, fpscr_ox_bit)); \
262 #define _DO_CR_COMPARE(LHS, RHS) \
269 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL)
270 #define CR_FIELD(REG) EXTRACTED32(CR, REG*4, REG*4+3)
271 #define CR_SET_XER_SO(REG, VAL) \
273 creg new_bits = ((XER & xer_summary_overflow) \
274 ? (cr_i_summary_overflow | VAL) \
276 CR_SET(REG, new_bits); \
279 #define CR_COMPARE(REG, LHS, RHS) \
281 creg new_bits = ((XER & xer_summary_overflow) \
282 ? (cr_i_summary_overflow | _DO_CR_COMPARE(LHS,RHS)) \
283 : _DO_CR_COMPARE(LHS,RHS)); \
284 CR_SET(REG, new_bits); \
287 #define CR0_COMPARE(LHS, RHS, Rc) \
290 CR_COMPARE(0, LHS, RHS); \
292 ("CR=0x%08lx, LHS=%ld, RHS=%ld\n", \
293 (unsigned long)CR, (long)LHS, (long)RHS)); \
299 /* Bring data in from the cold */
301 #define MEM(SIGN, EA, NR_BYTES) \
302 ((SIGN##_##NR_BYTES) vm_data_map_read_##NR_BYTES(cpu_data_map(processor), EA, \
305 #define STORE(EA, NR_BYTES, VAL) \
307 vm_data_map_write_##NR_BYTES(cpu_data_map(processor), EA, VAL, \
313 /* some FPSCR update macros. */
315 #define FPSCR_BEGIN \
317 fpscreg old_fpscr UNUSED = FPSCR
319 #define FPSCR_END(Rc) { \
320 /* always update VX */ \
321 if ((FPSCR & fpscr_vx_bits)) \
324 FPSCR &= ~fpscr_vx; \
325 /* always update FEX */ \
326 if (((FPSCR & fpscr_vx) && (FPSCR & fpscr_ve)) \
327 || ((FPSCR & fpscr_ox) && (FPSCR & fpscr_oe)) \
328 || ((FPSCR & fpscr_ux) && (FPSCR & fpscr_ue)) \
329 || ((FPSCR & fpscr_zx) && (FPSCR & fpscr_ze)) \
330 || ((FPSCR & fpscr_xx) && (FPSCR & fpscr_xe))) \
331 FPSCR |= fpscr_fex; \
333 FPSCR &= ~fpscr_fex; \
335 /* interrupt enabled? */ \
336 if ((MSR & (msr_floating_point_exception_mode_0 \
337 | msr_floating_point_exception_mode_1)) \
338 && (FPSCR & fpscr_fex)) \
339 program_interrupt(processor, cia, \
340 floating_point_enabled_program_interrupt); \
343 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL)
344 #define FPSCR_FIELD(REG) EXTRACTED32(FPSCR, REG*4, REG*4+3)
346 #define FPSCR_SET_FPCC(VAL) MBLIT32(FPSCR, fpscr_fpcc_bit, fpscr_fpcc_bit+3, VAL)
348 /* Handle various exceptions */
350 #define FPSCR_OR_VX(VAL) \
352 /* NOTE: VAL != 0 */ \
357 #define FPSCR_SET_OX(COND) \
364 FPSCR &= ~fpscr_ox; \
367 #define FPSCR_SET_UX(COND) \
374 FPSCR &= ~fpscr_ux; \
377 #define FPSCR_SET_ZX(COND) \
384 FPSCR &= ~fpscr_zx; \
387 #define FPSCR_SET_XX(COND) \
395 /* Note: code using SET_FI must also explicitly call SET_XX */
397 #define FPSCR_SET_FR(COND) do { \
401 FPSCR &= ~fpscr_fr; \
404 #define FPSCR_SET_FI(COND) \
410 FPSCR &= ~fpscr_fi; \
413 #define FPSCR_SET_FPRF(VAL) \
415 FPSCR = (FPSCR & ~fpscr_fprf) | (VAL); \
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