sim/ppc/igen.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994,1995,1996, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 /* What does the instruction look like - bit ordering and size */
  23 extern int hi_bit_nr;
  24 extern int insn_bit_size;
  25
  26
  27 /* generation options: */
  28
  29
  30 enum {
  31   generate_with_icache = 0x1,
  32   generate_with_semantic_icache = 0x2,
  33   generate_with_direct_access_icache = 0x4,
  34 };
  35
  36
  37 typedef enum {
  38
  39   /* Transfer control to an instructions semantic code using the the
  40      standard call/return mechanism */
  41
  42   generate_calls = 0x10,
  43
  44   /* In addition, pre-decode an instructions opcode fields (entering
  45      them into an icache) so that semantic code can avoid the need to
  46      re-decode fields each time it is executed */
  47
  48   generate_calls_with_icache
  49     = generate_calls | generate_with_icache,
  50
  51   /* In addition, the instruction decode code includes a duplicated
  52      copy of the instructions semantic code.  This avoids the need to
  53      perform two calls (one to decode an instructions opcode fields
  54      and one to execute the instruction) when there is a miss of the
  55      icache */
  56
  57   generate_calls_with_semantic_icache
  58     = generate_calls_with_icache | generate_with_semantic_icache,
  59
  60   /* In addition, the semantic function refers to icache entries
  61      directly instead of first moving them into local variables */
  62
  63   generate_calls_with_direct_access_icache
  64     = generate_calls_with_icache | generate_with_direct_access_icache,
  65
  66   generate_calls_with_direct_access_semantic_icache
  67     = generate_calls_with_direct_access_icache | generate_with_semantic_icache,
  68
  69
  70   /* Transfer control to an instructions semantic code using
  71      (computed) goto's instead of the more conventional call/return
  72      mechanism */
  73
  74   generate_jumps = 0x20,
  75
  76   /* As for generate_calls_with_icache but applies to jumping code */
  77
  78   generate_jumps_with_icache
  79     = generate_jumps | generate_with_icache,
  80
  81   /* As for generate_calls_with_semantic_icache but applies to jumping
  82      code */
  83
  84   generate_jumps_with_semantic_icache
  85     = generate_jumps_with_icache | generate_with_semantic_icache,
  86
  87   /* As for generate_calls_with_direct_access_icache */
  88
  89   generate_jumps_with_direct_access_icache
  90     = generate_jumps_with_icache | generate_with_direct_access_icache,
  91
  92   generate_jumps_with_direct_access_semantic_icache
  93     = generate_jumps_with_direct_access_icache | generate_with_semantic_icache,
  94
  95 } igen_code;
  96
  97 extern igen_code code;
  98
  99
 100
 101
 102 extern int icache_size;
 103
 104
 105 /* Instruction expansion?
 106
 107    Should the semantic code for each instruction, when the oportunity
 108    arrises, be expanded according to the variable opcode files that
 109    the instruction decode process renders constant */
 110
 111 extern int generate_expanded_instructions;
 112
 113
 114 /* SMP?
 115
 116    Should the generated code include SMP support (>0) and if so, for
 117    how many processors? */
 118
 119 extern int generate_smp;
 120
 121
 122
 123
 124 /* Misc junk */
 125
 126
 127
 128 /* Function header definitions */
 129
 130
 131 /* Cache functions: */
 132
 133 #define ICACHE_FUNCTION_FORMAL \
 134 "cpu *processor,\n\
 135  instruction_word instruction,\n\
 136  unsigned_word cia,\n\
 137  idecode_cache *cache_entry"
 138
 139 #define ICACHE_FUNCTION_ACTUAL "processor, instruction, cia, cache_entry"
 140
 141 #define ICACHE_FUNCTION_TYPE \
 142 ((code & generate_with_semantic_icache) \
 143  ? SEMANTIC_FUNCTION_TYPE \
 144  : "idecode_semantic *")
 145
 146
 147 /* Semantic functions: */
 148
 149 #define SEMANTIC_FUNCTION_FORMAL \
 150 ((code & generate_with_icache) \
 151  ? "cpu *processor,\n idecode_cache *cache_entry,\n unsigned_word cia" \
 152  : "cpu *processor,\n instruction_word instruction,\n unsigned_word cia")
 153
 154 #define SEMANTIC_FUNCTION_ACTUAL \
 155 ((code & generate_with_icache) \
 156  ? "processor, instruction, cia, cache_entry" \
 157  : "processor, instruction, cia")
 158
 159 #define SEMANTIC_FUNCTION_TYPE "unsigned_word"
 160
 161
 162
 163 extern void print_define_my_index
 164 (lf *file,
 165  table_entry *file_entry);
 166
 167 extern void print_itrace
 168 (lf *file,
 169  table_entry *file_entry,
 170  int idecode);
 171
 172
 173 typedef enum {
 174   function_name_prefix_semantics,
 175   function_name_prefix_idecode,
 176   function_name_prefix_itable,
 177   function_name_prefix_goto,
 178   function_name_prefix_icache,
 179   function_name_prefix_none
 180 } lf_function_name_prefixes;
 181
 182 extern int print_function_name
 183 (lf *file,
 184  const char *basename,
 185  insn_bits *expanded_bits,
 186  lf_function_name_prefixes prefix);