1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #ifndef _INTERRUPTS_H_
23 #define _INTERRUPTS_H_
27 The code below handles two different types of interrupts.
28 Synchronous and Asynchronous.
32 Interrupts that must immediately force either an abort or restart
33 of a current instruction are implemented by forcing an instruction
34 restart. (or to put it another way, long jump). In looking at the
35 code it may occure to you that, for some interrupts, they could
36 return instead of restarting the cpu (eg system_call). While true
37 (it once was like that) I've decided to make the behavour of all
38 interrupt routines roughly identical.
40 Because, a cpu's recorded state (ie what is in the cpu structure)
41 is allowed to lag behind the cpu's true current state (eg PC not
42 updated) sycnronous interrupt handers are parameterized with the
43 the cpu being interrupted so that, as part of moddeling the
44 interrupt, the cpu's state can be updated.
48 Interrupts such as reset or external exception are delivered using
49 more normal (returning) functions. It is assumed that these
50 functions are called out side of the normal processor execution
54 /* Software generated interrupts.
56 The below are generated by software driven events. For instance,
57 an invalid instruction or access (virtual or physical) to an
61 direct_store_storage_interrupt
,
62 hash_table_miss_storage_interrupt
,
63 protection_violation_storage_interrupt
,
64 earwax_violation_storage_interrupt
,
65 segment_table_miss_storage_interrupt
,
66 earwax_disabled_storage_interrupt
,
67 vea_storage_interrupt
,
68 } storage_interrupt_reasons
;
71 void INLINE_INTERRUPTS data_storage_interrupt
75 storage_interrupt_reasons reason
,
78 void INLINE_INTERRUPTS instruction_storage_interrupt
81 storage_interrupt_reasons reason
);
83 void INLINE_INTERRUPTS alignment_interrupt
89 floating_point_enabled_program_interrupt
,
90 illegal_instruction_program_interrupt
,
91 privileged_instruction_program_interrupt
,
92 trap_program_interrupt
,
93 nr_program_interrupt_reasons
94 } program_interrupt_reasons
;
96 void INLINE_INTERRUPTS program_interrupt
99 program_interrupt_reasons reason
);
101 void INLINE_INTERRUPTS floating_point_unavailable_interrupt
105 void INLINE_INTERRUPTS system_call_interrupt
109 void INLINE_INTERRUPTS trace_interrupt
113 void INLINE_INTERRUPTS floating_point_assist_interrupt
117 void INLINE_INTERRUPTS machine_check_interrupt
121 /* Bit of a funny one. One of the trap instructions has been marked
122 as the breakpoint instruction. This special case calls this
125 void INLINE_INTERRUPTS breakpoint_interrupt
129 /* Hardware generated interrupts
131 These hardware generated interrupt routines are called outside of
132 the instruction execution cycle and so return normally.
134 More importantly, they assume that the current instruction address
135 held within the processor is correct.
137 Return a non zero value if the interrupt was not successfully
140 int INLINE_INTERRUPTS decrementer_interrupt
143 int INLINE_INTERRUPTS hard_system_reset
146 int INLINE_INTERRUPTS soft_system_reset
149 int INLINE_INTERRUPTS external_interrupt
152 #endif /* _INTERRUPTS_H_ */