sim/ppc/ppc-opcode-test-2

   1 #
   2 #   This file is part of the program psim.
   3 #
   4 #   Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
   5 #
   6 #   This program is free software; you can redistribute it and/or modify
   7 #   it under the terms of the GNU General Public License as published by
   8 #   the Free Software Foundation; either version 2 of the License, or
   9 #   (at your option) any later version.
  10 #
  11 #   This program is distributed in the hope that it will be useful,
  12 #   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 #   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 #   GNU General Public License for more details.
  15 #
  16 #   You should have received a copy of the GNU General Public License
  17 #   along with this program; if not, write to the Free Software
  18 #   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19 #
  20 #   Instruction decode:
  21 #
  22 #   The table that follows is used by gen to construct a decision tree
  23 #   that can identify each possible instruction.  Gen then outputs this
  24 #   decision tree as (according to config) a table or switch statement
  25 #   as the function idecode.
  26 #
  27 #   In parallel to this, as mentioned above, WITH_EXPANDED_SEMANTICS
  28 #   determines of the semantic functions themselves should be expanded
  29 #   in a similar way.
  30 #
  31 #   The table contains the following entries:
  32 #
  33 #   <valid>
  34 #
  35 #   Must be 1 for the entry to be considered.  The last entry must be
  36 #   zero.
  37 #
  38 #   <first>
  39 #   <last>
  40 #
  41 #   Range of bits (within the instruction) that should be searched for
  42 #   an instruction field.  Within such ranges, gen looks for opcodes
  43 #   (constants), registers (strings) and reserved bits (slash) and
  44 #   according to the rules that follows includes or excludes them from
  45 #   a possible instruction field.
  46 #
  47 #   <force_first>
  48 #   <force_last>
  49 #
  50 #   If an instructioin field was found, enlarge the field size so that
  51 #   it is forced to at least include bits starting from <force_first>
  52 #   (<force_last>).  To stop this occuring, use <force_first> = <last>
  53 #   + 1 and <force_last> = <first> - 1.
  54 #
  55 #   <force_slash>
  56 #
  57 #   Treat `/' fields as a constant instead of variable when looking for
  58 #   an instruction field.
  59 #
  60 #   <force_expansion>
  61 #
  62 #   Treat any contained register (string) fields as constant when
  63 #   determining the instruction field.  For the instruction decode (and
  64 #   controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
  65 #   what would otherwize be non constant bits of an instruction.
  66 #
  67 #   <use_switch>
  68 #
  69 #   Should this table be expanded using a switch statement (val 1) and
  70 #   if so, should it be padded with entries so as to force the compiler
  71 #   to generate a jump table (val 2).
  72 #
  73 #   <special_mask>
  74 #   <special_value>
  75 #   <special_rule>
  76 #
  77 #   Special rule to fine tune how specific (or groups) of instructions
  78 #   are expanded.  The applicability of the rule is determined by
  79 #
  80 #     <special_mask> != 0 && (instruction> & <special_mask>) == <special_value>
  81 #
  82 #   Where <instruction> is obtained by looking only at constant fields
  83 #   with in an instructions spec.  When determining an expansion, the
  84 #   rule is only considered when a node contains a single instruction.
  85 #   <special_rule> can be any of:
  86 #
  87 #        0: for this instruction, expand by earlier rules
  88 #       1: expand bits <force_low> .. <force_hi> only
  89 #       2: boolean expansion of only zero/non-zero cases
  90 #
  91  0: 5: 0: 5:0::              0:0x00000000:0x00000000:0
  92 21:31:32:-1:0:OE,LR,AA,Rc,LK:0:0x00000000:0x00000000:0
  93  6: 9: 6: 9:0:BO:            0:0xfc000000:0x40000000:1
  94 11:15:11:15:0:RA:            1:0xfc000000:0x38000000:2
  95 11:15:11:15:0:RA:            1:0xfc000000:0x3c000000:2