1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * The PowerPC registers
33 ** General Purpose Registers
36 typedef signed_word gpreg
;
41 ** Floating Point Registers
44 typedef unsigned64 fpreg
;
49 ** The condition register
53 typedef unsigned32 creg
;
55 /* The following sub bits are defined for the condition register */
57 cr_i_negative
= BIT4(0),
58 cr_i_positive
= BIT4(1),
60 cr_i_summary_overflow
= BIT4(3),
62 /* cr0 - integer status */
63 cr0_i_summary_overflow_bit
= 3,
64 cr0_i_negative
= BIT32(0),
65 cr0_i_positive
= BIT32(1),
66 cr0_i_zero
= BIT32(2),
67 cr0_i_summary_overflow
= BIT32(3),
68 cr0_i_mask
= MASK32(0,3),
70 /* cr1 - floating-point status */
71 cr1_i_floating_point_exception_summary_bit
= 4,
72 cr1_i_floating_point_enabled_exception_summary_bit
= 5,
73 cr1_i_floating_point_invalid_operation_exception_summary_bit
= 6,
74 cr1_i_floating_point_overflow_exception_bit
= 7,
75 cr1_i_floating_point_exception_summary
= BIT32(4),
76 cr1_i_floating_point_enabled_exception_summary
= BIT32(5),
77 cr1_i_floating_point_invalid_operation_exception_summary
= BIT32(6),
78 cr1_i_floating_point_overflow_exception
= BIT32(7),
79 cr1_i_mask
= MASK32(4,7),
83 /* Condition register 1 contains the result of floating point arithmetic */
85 cr_fp_exception
= BIT4(0),
86 cr_fp_enabled_exception
= BIT4(1),
87 cr_fp_invalid_exception
= BIT4(2),
88 cr_fp_overflow_exception
= BIT4(3),
94 ** Floating-Point Status and Control Register
97 typedef unsigned32 fpscreg
;
102 fpscr_fex
= BIT32(1),
110 fpscr_vxsnan
= BIT32(7), /* SNAN */
111 fpscr_vxisi
= BIT32(8), /* INF - INF */
112 fpscr_vxidi
= BIT32(9), /* INF / INF */
113 fpscr_vxzdz
= BIT32(10), /* 0 / 0 */
114 fpscr_vximz
= BIT32(11), /* INF * 0 */
115 fpscr_vxvc
= BIT32(12),
116 fpscr_fr
= BIT32(13),
117 fpscr_fi
= BIT32(14),
118 fpscr_fprf
= MASK32(15, 19),
120 fpscr_fpcc_bit
= 16, /* well sort of */
121 fpscr_fpcc
= MASK32(16, 19),
122 fpscr_fl
= BIT32(16),
123 fpscr_fg
= BIT32(17),
124 fpscr_fe
= BIT32(18),
125 fpscr_fu
= BIT32(19),
126 fpscr_rf_quiet_nan
= fpscr_c
| fpscr_fu
,
127 fpscr_rf_neg_infinity
= fpscr_fl
| fpscr_fu
,
128 fpscr_rf_neg_normal_number
= fpscr_fl
,
129 fpscr_rf_neg_denormalized_number
= fpscr_c
| fpscr_fl
,
130 fpscr_rf_neg_zero
= fpscr_c
| fpscr_fe
,
131 fpscr_rf_pos_zero
= fpscr_fe
,
132 fpscr_rf_pos_denormalized_number
= fpscr_c
| fpscr_fg
,
133 fpscr_rf_pos_normal_number
= fpscr_fg
,
134 fpscr_rf_pos_infinity
= fpscr_fg
| fpscr_fu
,
135 fpscr_reserved_20
= BIT32(20),
136 fpscr_vxsoft
= BIT32(21),
137 fpscr_vxsqrt
= BIT32(22),
138 fpscr_vxcvi
= BIT32(23),
139 fpscr_ve
= BIT32(24),
140 fpscr_oe
= BIT32(25),
141 fpscr_ue
= BIT32(26),
142 fpscr_ze
= BIT32(27),
143 fpscr_xe
= BIT32(28),
144 fpscr_ni
= BIT32(29),
145 fpscr_rn
= MASK32(30, 31),
146 fpscr_rn_round_to_nearest
= 0,
147 fpscr_rn_round_towards_zero
= MASK32(31,31),
148 fpscr_rn_round_towards_pos_infinity
= MASK32(30,30),
149 fpscr_rn_round_towards_neg_infinity
= MASK32(30,31),
150 fpscr_vx_bits
= (fpscr_vxsnan
| fpscr_vxisi
| fpscr_vxidi
151 | fpscr_vxzdz
| fpscr_vximz
| fpscr_vxvc
152 | fpscr_vxsoft
| fpscr_vxsqrt
| fpscr_vxcvi
),
161 typedef unsigned32 xereg
;
164 xer_summary_overflow
= BIT32(0), xer_summary_overflow_bit
= 0,
165 xer_carry
= BIT32(2), xer_carry_bit
= 2,
166 xer_overflow
= BIT32(1),
167 xer_reserved_3_24
= MASK32(3,24),
168 xer_byte_count_mask
= MASK32(25,31)
183 typedef unsigned32 sreg
;
190 ** Machine state register
192 typedef unsigned_word msreg
; /* 32 or 64 bits */
195 #if (WITH_TARGET_WORD_BITSIZE == 64)
196 msr_64bit_mode
= BIT(0),
198 #if (WITH_TARGET_WORD_BITSIZE == 32)
201 msr_power_management_enable
= BIT(45),
202 msr_tempoary_gpr_remapping
= BIT(46), /* 603 specific */
203 msr_interrupt_little_endian_mode
= BIT(47),
204 msr_external_interrupt_enable
= BIT(48),
205 msr_problem_state
= BIT(49),
206 msr_floating_point_available
= BIT(50),
207 msr_machine_check_enable
= BIT(51),
208 msr_floating_point_exception_mode_0
= BIT(52),
209 msr_single_step_trace_enable
= BIT(53),
210 msr_branch_trace_enable
= BIT(54),
211 msr_floating_point_exception_mode_1
= BIT(55),
212 msr_interrupt_prefix
= BIT(57),
213 msr_instruction_relocate
= BIT(58),
214 msr_data_relocate
= BIT(59),
215 msr_recoverable_interrupt
= BIT(62),
216 msr_little_endian_mode
= BIT(63)
220 srr1_hash_table_or_ibat_miss
= BIT(33),
221 srr1_direct_store_error_exception
= BIT(35),
222 srr1_protection_violation
= BIT(36),
223 srr1_segment_table_miss
= BIT(42),
224 srr1_floating_point_enabled
= BIT(43),
225 srr1_illegal_instruction
= BIT(44),
226 srr1_priviliged_instruction
= BIT(45),
228 srr1_subsequent_instruction
= BIT(47)
233 ** storage interrupt registers
237 dsisr_direct_store_error_exception
= BIT32(0),
238 dsisr_hash_table_or_dbat_miss
= BIT32(1),
239 dsisr_protection_violation
= BIT32(4),
240 dsisr_earwax_violation
= BIT32(5),
241 dsisr_store_operation
= BIT32(6),
242 dsisr_segment_table_miss
= BIT32(10),
243 dsisr_earwax_disabled
= BIT32(11)
249 ** And the registers proper
251 typedef struct _registers
{
258 /* Machine state register */
262 spreg spr
[nr_of_sprs
];
264 /* Segment Registers */
270 /* dump out all the registers */
273 (void) registers_dump
277 /* return information on a register based on name */
281 reg_gpr
, reg_fpr
, reg_spr
, reg_msr
,
282 reg_cr
, reg_fpscr
, reg_pc
, reg_sr
,
283 reg_insns
, reg_stalls
, reg_cycles
,
291 } register_descriptions
;
294 (register_descriptions
) register_description
298 /* Special purpose registers by their more common names */
300 #define SPREG(N) cpu_registers(processor)->spr[N]
301 #define XER SPREG(spr_xer)
302 #define LR SPREG(spr_lr)
303 #define CTR SPREG(spr_ctr)
304 #define SRR0 SPREG(spr_srr0)
305 #define SRR1 SPREG(spr_srr1)
306 #define DAR SPREG(spr_dar)
307 #define DSISR SPREG(spr_dsisr)
309 /* general purpose registers - indexed access */
310 #define GPR(N) cpu_registers(processor)->gpr[N]
312 /* segment registers */
313 #define SEGREG(N) cpu_registers(processor)->sr[N]
315 /* condition register */
316 #define CR cpu_registers(processor)->cr
318 /* machine status register */
319 #define MSR cpu_registers(processor)->msr
321 /* floating-point status condition register */
322 #define FPSCR cpu_registers(processor)->fpscr
324 #endif /* _REGISTERS_H_ */