1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 /* endianness of the host/target:
28 If the build process is aware (at compile time) of the endianness
29 of the host/target it is able to eliminate slower generic endian
32 Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
34 #ifndef WITH_HOST_BYTE_ORDER
35 #define WITH_HOST_BYTE_ORDER 0 /*unknown*/
38 #ifndef WITH_TARGET_BYTE_ORDER
39 #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/
42 extern int current_host_byte_order
;
43 #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \
44 ? WITH_HOST_BYTE_ORDER \
45 : current_host_byte_order)
46 extern int current_target_byte_order
;
47 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
48 ? WITH_TARGET_BYTE_ORDER \
49 : current_target_byte_order)
52 /* Intel host BSWAP support:
54 Whether to use bswap on the 486 and pentiums rather than the 386
55 sequence that uses xchgb/rorl/xchgb */
63 Sets a limit on the number of processors that can be simulated. If
64 WITH_SMP is set to zero (0), the simulator is restricted to
65 suporting only on processor (and as a consequence leaves the SMP
66 code out of the build process).
68 The actual number of processors is taken from the device
69 /options/smp@<nr-cpu> */
75 #define MAX_NR_PROCESSORS WITH_SMP
77 #define MAX_NR_PROCESSORS 1
81 /* Word size of host/target:
83 Set these according to your host and target requirements. At this
84 point in time, I've only compiled (not run) for a 64bit and never
85 built for a 64bit host. This will always remain a compile time
88 #ifndef WITH_TARGET_WORD_BITSIZE
89 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */
92 #ifndef WITH_HOST_WORD_BITSIZE
93 #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */
97 /* Program environment:
99 Two environments are available. VEA (or virtual environment
100 architecture) and OEA (or operating environment architecture). The
101 former is the environment that a user program would see while the
102 latter is the environment as seen by an operating system. By
103 setting these to specific values, the build process is able to
104 eliminate non relevent environment code
106 CURRENT_ENVIRONMENT specifies which of vea or oea is required for
107 the current runtime. */
109 #define VIRTUAL_ENVIRONMENT 1
110 #define OPERATING_ENVIRONMENT 2
112 #ifndef WITH_ENVIRONMENT
113 #define WITH_ENVIRONMENT 0
116 extern int current_environment
;
117 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
119 : current_environment)
122 /* Optional VEA/OEA code:
124 The below, required for the OEA model may also be included in the
125 VEA model however, as far as I can tell only make things
129 /* Events. Devices modeling real H/W need to be able to efficiently
130 schedule things to do at known times in the future. The event
131 queue implements this. Unfortunatly this adds the need to check
132 for any events once each full instruction cycle. */
134 #define WITH_EVENTS (WITH_ENVIRONMENT != VIRTUAL_ENVIRONMENT)
139 The PowerPC architecture includes the addition of both a time base
140 register and a decrement timer. Like events adds to the overhead
141 of of some instruction cycles. */
143 #ifndef WITH_TIME_BASE
144 #define WITH_TIME_BASE 1
148 /* Callback/Default Memory.
150 Core includes a builtin memory type (raw_memory) that is
151 implemented using an array. raw_memory does not require any
152 additional functions etc.
154 Callback memory is where the core calls a core device for the data
157 Default memory is an extenstion of this where for addresses that do
158 not map into either a callback or core memory range a default map
161 The OEA model uses callback memory for devices and default memory
164 The VEA model uses callback memory to capture `page faults'.
166 While it may be possible to eliminate callback/default memory (and
167 hence also eliminate an additional test per memory fetch) it
168 probably is not worth the effort.
170 BTW, while raw_memory could have been implemented as a callback,
171 profiling has shown that there is a biger win (at least for the
172 x86) in eliminating a function call for the most common
173 (raw_memory) case. */
175 #define WITH_CALLBACK_MEMORY 1
180 The PowerPC may or may not handle miss aligned transfers. An
181 implementation normally handles miss aligned transfers in big
182 endian mode but generates an exception in little endian mode.
184 This model. Instead allows both little and big endian modes to
185 either take exceptions or handle miss aligned transfers.
187 If 0 is specified then for big-endian mode miss alligned accesses
188 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
189 processor will fault on them (STRICT_ALIGNMENT). */
191 #define NONSTRICT_ALIGNMENT 1
192 #define STRICT_ALIGNMENT 2
194 #ifndef WITH_ALIGNMENT
195 #define WITH_ALIGNMENT 0
198 extern int current_alignment
;
199 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
204 /* Floating point suport:
206 Still under development. */
208 #define SOFT_FLOATING_POINT 1
209 #define HARD_FLOATING_POINT 2
211 #ifndef WITH_FLOATING_POINT
212 #define WITH_FLOATING_POINT HARD_FLOATING_POINT
214 extern int current_floating_point
;
215 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
216 ? WITH_FLOATING_POINT \
217 : current_floating_point)
222 Control the inclusion of debugging code. */
224 /* Include the tracing code. Disabling this eliminates all tracing
231 /* include code that checks assertions scattered through out the
235 #define WITH_ASSERT 1
238 /* include monitoring code */
240 #define MONITOR_INSTRUCTION_ISSUE 1
241 #define MONITOR_LOAD_STORE_UNIT 2
243 #define WITH_MON (MONITOR_LOAD_STORE_UNIT \
244 | MONITOR_INSTRUCTION_ISSUE)
249 /* INLINE CODE SELECTION:
251 GCC -O3 attempts to inline any function or procedure in scope. The
252 options below facilitate fine grained control over what is and what
253 isn't made inline. For instance it can control things down to a
254 specific modules static routines. This control is implemented in
255 two parts. Doing this allows the compiler to both eliminate the
256 overhead of function calls and (as a consequence) also eliminate
259 Experementing with CISC (x86) I've found that I can achieve an
260 order of magintude speed improvement (x3-x5). In the case of RISC
261 (sparc) while the performance gain isn't as great it is still
264 Part One - Static functions: It is possible to control how static
265 functions within each module are to be compiled. On a per module
266 or global basis, it is possible to specify that a modules static
267 functions should be compiled inline. This is controled by the the
268 macro's STATIC_INLINE and INLINE_STATIC_<module>.
270 Part Two - External functions: Again it is possible to allow the
271 inlining of calls to external functions. This is far more
272 complicated and much heaver on the compiler. In this case, it is
273 controled by the <module>_INLINE macro's. Where each can have a
276 0 Make a normal external call to functions in the module.
278 1 Include the module but to not inline functions within it.
279 This allows functions within the module to inline functions
280 from other modules that have been included.
282 2 Both include the module and inline functions contained within
285 Finally, this is not for the faint harted. I've seen GCC get up to
286 200mb trying to compile what this can create */
288 /* Your compilers inline reserved word */
291 #if defined(__GNUC__) && defined(__OPTIMIZE__)
292 #define INLINE __inline__
294 #define INLINE /*inline*/
298 /* Default prefix for static functions */
300 #ifndef STATIC_INLINE
301 #define STATIC_INLINE static INLINE
304 /* Default macro to simplify control several of key the inlines */
306 #ifndef DEFAULT_INLINE
307 #if defined(__GNUC__) && defined(__OPTIMIZE__)
308 #define DEFAULT_INLINE 2
310 #define DEFAULT_INLINE 0
314 /* Code that converts between hosts and target byte order. Used on
315 every memory access (instruction and data). (See ppc-endian.h for
316 additional byte swapping configuration information) */
318 #ifndef ENDIAN_INLINE
319 #define ENDIAN_INLINE DEFAULT_INLINE
322 /* Code that gives access to various CPU internals such as registers.
323 Used every time an instruction is executed */
326 #define CPU_INLINE DEFAULT_INLINE
329 /* Code that translates between an effective and real address. Used
330 by every load or store. */
333 #define VM_INLINE DEFAULT_INLINE
336 /* Code that loads/stores data to/from the memory data structure.
337 Used by every load or store */
340 #define CORE_INLINE DEFAULT_INLINE
343 /* Code to check for and process any events scheduled in the future.
344 Called once per instruction cycle */
346 #ifndef EVENTS_INLINE
347 #define EVENTS_INLINE DEFAULT_INLINE
350 /* Code monotoring the processors performance. It counts events on
351 every instruction cycle */
354 #define MON_INLINE DEFAULT_INLINE
357 /* Code called on the rare occasions that an interrupt occures. */
359 #ifndef INTERRUPTS_INLINE
360 #define INTERRUPTS_INLINE 0
363 /* Code called on the rare occasion that either gdb or the device tree
364 need to manipulate a register within a processor */
366 #ifndef REGISTERS_INLINE
367 #define REGISTERS_INLINE 0
370 /* Code called on the rare occasion that a processor is manipulating
371 real hardware instead of RAM.
373 Also, most of the functions in devices.c are always called through
376 There seems to be some problem with making either device_tree or
377 devices inline. It reports the message: device_tree_find_node()
380 #ifndef DEVICE_TREE_INLINE
381 #define DEVICE_TREE_INLINE DEFAULT_INLINE
384 #ifndef DEVICES_INLINE
385 #define DEVICES_INLINE 0
388 /* Code called whenever information on a Special Purpose Register is
389 required. Called by the mflr/mtlr pseudo instructions */
392 #define SPREG_INLINE DEFAULT_INLINE
395 /* Functions modeling the semantics of each instruction. Two cases to
396 consider, firstly of idecode is implemented with a switch then this
397 allows the idecode function to inline each semantic function
398 (avoiding a call). The second case is when idecode is using a
399 table, even then while the semantic functions can't be inlined,
400 setting it to one still enables each semantic function to inline
401 anything they call (if that code is marked for being inlined).
403 WARNING: you need lots (like 200mb of swap) of swap. Setting this
404 to 1 is useful when using a table as it enables the sematic code to
405 inline all of their called functions */
407 #ifndef SEMANTICS_INLINE
408 #define SEMANTICS_INLINE (DEFAULT_INLINE ? 1 : 0)
411 /* Code to decode an instruction. Normally called on every instruction
414 #ifndef IDECODE_INLINE
415 #define IDECODE_INLINE DEFAULT_INLINE
418 #endif /* _CONFIG_H */