sim/sh/gencode.c

   1 /* Simulator/Opcode generator for the Hitachi Super-H architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 /* This program generates the opcode table for the assembler and
  22    the simulator code
  23
  24    -t           prints a pretty table for the assembler manual
  25    -s           generates the simulator code jump table
  26    -d           generates a define table
  27    -x           generates the simulator code switch statement
  28    default      used to generate the opcode tables
  29
  30 */
  31
  32 #include <stdio.h>
  33
  34 #define MAX_NR_STUFF 42
  35
  36 typedef struct
  37 {
  38   char *defs;
  39   char *refs;
  40   char *name;
  41   char *code;
  42   char *stuff[MAX_NR_STUFF];
  43   int index;
  44 } op;
  45
  46
  47 op tab[] =
  48 {
  49
  50   { "n", "", "add #<imm>,<REG_N>", "0111nnnni8*1....",
  51     "R[n] += SEXT(i);",
  52     "if (i == 0) {",
  53     "  UNDEF(n); /* see #ifdef PARANOID */",
  54     "  break;",
  55     "}",
  56   },
  57   { "n", "mn", "add <REG_M>,<REG_N>", "0011nnnnmmmm1100",
  58     "R[n] += R[m];",
  59   },
  60
  61   { "n", "mn", "addc <REG_M>,<REG_N>", "0011nnnnmmmm1110",
  62     "ult = R[n] + T;",
  63     "SET_SR_T (ult < R[n]);",
  64     "R[n] = ult + R[m];",
  65     "SET_SR_T (T || (R[n] < ult));",
  66   },
  67
  68   { "n", "mn", "addv <REG_M>,<REG_N>", "0011nnnnmmmm1111",
  69     "ult = R[n] + R[m];",
  70     "SET_SR_T ((~(R[n] ^ R[m]) & (ult ^ R[n])) >> 31);",
  71     "R[n] = ult;",
  72   },
  73
  74   { "0", "", "and #<imm>,R0", "11001001i8*1....",
  75     "R0 &= i;",
  76   },
  77   { "n", "nm", "and <REG_M>,<REG_N>", "0010nnnnmmmm1001",
  78     "R[n] &= R[m];",
  79   },
  80   { "", "0", "and.b #<imm>,@(R0,GBR)", "11001101i8*1....",
  81     "MA (1);",
  82     "WBAT (GBR + R0, RBAT (GBR + R0) & i);",
  83   },
  84
  85   { "", "", "bf <bdisp8>", "10001011i8p1....",
  86     "if (!T) {",
  87     "  SET_NIP (PC + 4 + (SEXT(i) * 2));",
  88     "  cycles += 2;",
  89     "}",
  90   },
  91
  92   { "", "", "bf.s <bdisp8>", "10001111i8p1....",
  93     "if (!T) {",
  94     "  SET_NIP (PC + 4 + (SEXT (i) * 2));",
  95     "  cycles += 2;",
  96     "  Delay_Slot (PC + 2);",
  97     "}",
  98   },
  99
 100   { "", "", "bra <bdisp12>", "1010i12.........",
 101     "SET_NIP (PC + 4 + (SEXT12 (i) * 2));",
 102     "cycles += 2;",
 103     "Delay_Slot (PC + 2);",
 104   },
 105
 106   { "", "n", "braf <REG_N>", "0000nnnn00100011",
 107     "SET_NIP (PC + 4 + R[n]);",
 108     "cycles += 2;",
 109     "Delay_Slot (PC + 2);",
 110   },
 111
 112   { "", "", "bsr <bdisp12>", "1011i12.........",
 113     "PR = PH2T (PC + 4);",
 114     "SET_NIP (PC + 4 + (SEXT12 (i) * 2));",
 115     "cycles += 2;",
 116     "Delay_Slot (PC + 2);",
 117   },
 118
 119   { "", "n", "bsrf <REG_N>", "0000nnnn00000011",
 120     "PR = PH2T (PC) + 4;",
 121     "SET_NIP (PC + 4 + R[n]);",
 122     "cycles += 2;",
 123     "Delay_Slot (PC + 2);",
 124   },
 125
 126   { "", "", "bt <bdisp8>", "10001001i8p1....",
 127     "if (T) {",
 128     "  SET_NIP (PC + 4 + (SEXT (i) * 2));",
 129     "  cycles += 2;",
 130     "}",
 131   },
 132
 133   { "", "", "bt.s <bdisp8>", "10001101i8p1....",
 134     "if (T) {",
 135     "  SET_NIP (PC + 4 + (SEXT (i) * 2));",
 136     "  cycles += 2;",
 137     "  Delay_Slot (PC + 2);",
 138     "}",
 139   },
 140
 141   { "", "", "clrmac", "0000000000101000",
 142     "MACH = 0;",
 143     "MACL = 0;",
 144   },
 145
 146   { "", "", "clrs", "0000000001001000",
 147     "SET_SR_S (0);",
 148   },
 149
 150   { "", "", "clrt", "0000000000001000",
 151     "SET_SR_T (0);",
 152   },
 153
 154   { "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....",
 155     "SET_SR_T (R0 == SEXT (i));",
 156   },
 157   { "", "mn", "cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000",
 158     "SET_SR_T (R[n] == R[m]);",
 159   },
 160   { "", "mn", "cmp/ge <REG_M>,<REG_N>", "0011nnnnmmmm0011",
 161     "SET_SR_T (R[n] >= R[m]);",
 162   },
 163   { "", "mn", "cmp/gt <REG_M>,<REG_N>", "0011nnnnmmmm0111",
 164     "SET_SR_T (R[n] > R[m]);",
 165   },
 166   { "", "mn", "cmp/hi <REG_M>,<REG_N>", "0011nnnnmmmm0110",
 167     "SET_SR_T (UR[n] > UR[m]);",
 168   },
 169   { "", "mn", "cmp/hs <REG_M>,<REG_N>", "0011nnnnmmmm0010",
 170     "SET_SR_T (UR[n] >= UR[m]);",
 171   },
 172   { "", "n", "cmp/pl <REG_N>", "0100nnnn00010101",
 173     "SET_SR_T (R[n] > 0);",
 174   },
 175   { "", "n", "cmp/pz <REG_N>", "0100nnnn00010001",
 176     "SET_SR_T (R[n] >= 0);",
 177   },
 178   { "", "mn", "cmp/str <REG_M>,<REG_N>", "0010nnnnmmmm1100",
 179     "ult = R[n] ^ R[m];",
 180     "SET_SR_T (((ult & 0xff000000) == 0)",
 181     "          | ((ult & 0xff0000) == 0)",
 182     "          | ((ult & 0xff00) == 0)",
 183     "          | ((ult & 0xff) == 0));",
 184   },
 185
 186   { "", "mn", "div0s <REG_M>,<REG_N>", "0010nnnnmmmm0111",
 187     "SET_SR_Q ((R[n] & sbit) != 0);",
 188     "SET_SR_M ((R[m] & sbit) != 0);",
 189     "SET_SR_T (M != Q);",
 190   },
 191
 192   { "", "", "div0u", "0000000000011001",
 193     "SET_SR_M (0);",
 194     "SET_SR_Q (0);",
 195     "SET_SR_T (0);",
 196   },
 197
 198   { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", /* ? MVS */
 199     "div1 (R, m, n/*, T*/);",
 200   },
 201
 202   { "", "nm", "dmuls.l <REG_M>,<REG_N>", "0011nnnnmmmm1101",
 203     "dmul (1/*signed*/, R[n], R[m]);",
 204   },
 205
 206   { "", "nm", "dmulu.l <REG_M>,<REG_N>", "0011nnnnmmmm0101",
 207     "dmul (0/*unsigned*/, R[n], R[m]);",
 208   },
 209
 210   { "n", "n", "dt <REG_N>", "0100nnnn00010000",
 211     "R[n]--;",
 212     "SET_SR_T (R[n] == 0);",
 213   },
 214
 215   { "n", "m", "exts.b <REG_M>,<REG_N>", "0110nnnnmmmm1110",
 216     "R[n] = SEXT (R[m]);",
 217   },
 218   { "n", "m", "exts.w <REG_M>,<REG_N>", "0110nnnnmmmm1111",
 219     "R[n] = SEXTW (R[m]);",
 220   },
 221
 222   { "n", "m", "extu.b <REG_M>,<REG_N>", "0110nnnnmmmm1100",
 223     "R[n] = (R[m] & 0xff);",
 224   },
 225   { "n", "m", "extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101",
 226     "R[n] = (R[m] & 0xffff);",
 227   },
 228
 229   /* sh2e */
 230   { "", "", "fabs <FREG_N>", "1111nnnn01011101",
 231     "FP_UNARY (n, fabs);",
 232     "/* FIXME: FR(n) &= 0x7fffffff; */",
 233   },
 234
 235   /* sh2e */
 236   { "", "", "fadd <FREG_M>,<FREG_N>", "1111nnnnmmmm0000",
 237     "FP_OP (n, +, m);",
 238   },
 239
 240   /* sh2e */
 241   { "", "", "fcmp/eq <FREG_M>,<FREG_N>", "1111nnnnmmmm0100",
 242     "FP_CMP (n, ==, m);",
 243   },
 244   /* sh2e */
 245   { "", "", "fcmp/gt <FREG_M>,<FREG_N>", "1111nnnnmmmm0101",
 246     "FP_CMP (n, >, m);",
 247   },
 248
 249   /* sh4 */
 250   { "", "", "fcnvds <DR_N>,FPUL", "1111nnnn10111101",
 251     "if (! FPSCR_PR || n & 1)",
 252     "  RAISE_EXCEPTION (SIGILL);",
 253     "else",
 254     "{",
 255     "  union",
 256     "  {",
 257     "    int i;",
 258     "    float f;",
 259     "  } u;",
 260     "  u.f = DR(n);",
 261     "  FPUL = u.i;",
 262     "}",
 263   },
 264
 265   /* sh4 */
 266   { "", "", "fcnvsd FPUL,<DR_N>", "1111nnnn10101101",
 267     "if (! FPSCR_PR || n & 1)",
 268     "  RAISE_EXCEPTION (SIGILL);",
 269     "else",
 270     "{",
 271     "  union",
 272     "  {",
 273     "    int i;",
 274     "    float f;",
 275     "  } u;",
 276     "  u.i = FPUL;",
 277     "  SET_DR(n, u.f);",
 278     "}",
 279   },
 280
 281   /* sh2e */
 282   { "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011",
 283     "FP_OP (n, /, m);",
 284     "/* FIXME: check for DP and (n & 1) == 0? */",
 285   },
 286
 287   /* sh4 */
 288   { "", "", "fipr <FV_M>,<FV_N>", "1111nnmm11101101",
 289     "/* FIXME: not implemented */",
 290     "RAISE_EXCEPTION (SIGILL);",
 291     "/* FIXME: check for DP and (n & 1) == 0? */",
 292   },
 293
 294   /* sh2e */
 295   { "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
 296     "SET_FR (n, (float)0.0);",
 297     "/* FIXME: check for DP and (n & 1) == 0? */",
 298   },
 299
 300   /* sh2e */
 301   { "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
 302     "SET_FR (n, (float)1.0);",
 303     "/* FIXME: check for DP and (n & 1) == 0? */",
 304   },
 305
 306   /* sh2e */
 307   { "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101",
 308     "  union",
 309     "  {",
 310     "    int i;",
 311     "    float f;",
 312     "  } u;",
 313     "  u.f = FR(n);",
 314     "  FPUL = u.i;",
 315   },
 316
 317   /* sh2e */
 318   { "", "", "float FPUL,<FREG_N>", "1111nnnn00101101",
 319     /* sh4 */
 320     "if (FPSCR_PR)",
 321     "  SET_DR (n, (double)FPUL);",
 322     "else",
 323     "{",
 324     "  SET_FR (n, (float)FPUL);",
 325     "}",
 326   },
 327
 328   /* sh2e */
 329   { "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110",
 330     "SET_FR (n, FR(m) * FR(0) + FR(n));",
 331     "/* FIXME: check for DP and (n & 1) == 0? */",
 332   },
 333
 334   /* sh2e */
 335   { "", "", "fmov <FREG_M>,<FREG_N>", "1111nnnnmmmm1100",
 336     /* sh4 */
 337     "if (FPSCR_SZ) {",
 338     "  int ni = XD_TO_XF (n);",
 339     "  int mi = XD_TO_XF (m);",
 340     "  SET_XF (ni + 0, XF (mi + 0));",
 341     "  SET_XF (ni + 1, XF (mi + 1));",
 342     "}",
 343     "else",
 344     "{",
 345     "  SET_FR (n, FR (m));",
 346     "}",
 347   },
 348   /* sh2e */
 349   { "", "n", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
 350     /* sh4 */
 351     "if (FPSCR_SZ) {",
 352     "  MA (2);",
 353     "  WDAT (R[n], m);",
 354     "}",
 355     "else",
 356     "{",
 357     "  MA (1);",
 358     "  WLAT (R[n], FI(m));",
 359     "}",
 360   },
 361   /* sh2e */
 362   { "", "m", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
 363     /* sh4 */
 364     "if (FPSCR_SZ) {",
 365     "  MA (2);",
 366     "  RDAT (R[m], n);",
 367     "}",
 368     "else",
 369     "{",
 370     "  MA (1);",
 371     "  SET_FI(n, RLAT(R[m]));",
 372     "}",
 373   },
 374   /* sh2e */
 375   { "m", "m", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
 376     /* sh4 */
 377     "if (FPSCR_SZ) {",
 378     "  MA (2);",
 379     "  RDAT (R[m], n);",
 380     "  R[m] += 8;",
 381     "}",
 382     "else",
 383     "{",
 384     "  MA (1);",
 385     "  SET_FI (n, RLAT (R[m]));",
 386     "  R[m] += 4;",
 387     "}",
 388   },
 389   /* sh2e */
 390   { "n", "n", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
 391     /* sh4 */
 392     "if (FPSCR_SZ) {",
 393     "  MA (2);",
 394     "  R[n] -= 8;",
 395     "  WDAT (R[n], m);",
 396     "}",
 397     "else",
 398     "{",
 399     "  MA (1);",
 400     "  R[n] -= 4;",
 401     "  WLAT (R[n], FI(m));",
 402     "}",
 403   },
 404   /* sh2e */
 405   { "", "0m", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
 406     /* sh4 */
 407     "if (FPSCR_SZ) {",
 408     "  MA (2);",
 409     "  RDAT (R[0]+R[m], n);",
 410     "}",
 411     "else",
 412     "{",
 413     "  MA (1);",
 414     "  SET_FI(n, RLAT(R[0] + R[m]));",
 415     "}",
 416   },
 417   /* sh2e */
 418   { "", "0n", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
 419     /* sh4 */
 420     "if (FPSCR_SZ) {",
 421     "  MA (2);",
 422     "  WDAT (R[0]+R[n], m);",
 423     "}",
 424     "else",
 425     "{",
 426     "  MA (1);",
 427     "  WLAT((R[0]+R[n]), FI(m));",
 428     "}",
 429   },
 430
 431   /* sh4: See fmov instructions above for move to/from extended fp registers */
 432
 433   /* sh2e */
 434   { "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
 435     "FP_OP(n, *, m);",
 436   },
 437
 438   /* sh2e */
 439   { "", "", "fneg <FREG_N>", "1111nnnn01001101",
 440     "FP_UNARY(n, -);",
 441   },
 442
 443   /* sh4 */
 444   { "", "", "frchg", "1111101111111101",
 445     "if (FPSCR_PR)",
 446     "  RAISE_EXCEPTION (SIGILL);",
 447     "else",
 448     "  SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);",
 449   },
 450
 451   /* sh4 */
 452   { "", "", "fschg", "1111001111111101",
 453     "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_SZ);",
 454   },
 455
 456   /* sh3e */
 457   { "", "", "fsqrt <FREG_N>", "1111nnnn01101101",
 458     "FP_UNARY(n, sqrt);",
 459   },
 460
 461   /* sh2e */
 462   { "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001",
 463     "FP_OP(n, -, m);",
 464   },
 465
 466   /* sh2e */
 467   { "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101",
 468     /* sh4 */
 469     "if (FPSCR_PR) {",
 470     "  if (DR(n) != DR(n)) /* NaN */",
 471     "    FPUL = 0x80000000;",
 472     "  else",
 473     "    FPUL =  (int)DR(n);",
 474     "}",
 475     "else",
 476     "if (FR(n) != FR(n)) /* NaN */",
 477     "  FPUL = 0x80000000;",
 478     "else",
 479     "  FPUL = (int)FR(n);",
 480   },
 481
 482   /* sh2e */
 483   { "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
 484     "  union",
 485     "  {",
 486     "    int i;",
 487     "    float f;",
 488     "  } u;",
 489     "  u.i = FPUL;",
 490     "  SET_FR (n, u.f);",
 491   },
 492
 493   { "", "n", "jmp @<REG_N>", "0100nnnn00101011",
 494     "SET_NIP (PT2H (R[n]));",
 495     "cycles += 2;",
 496     "Delay_Slot (PC + 2);",
 497   },
 498
 499   { "", "n", "jsr @<REG_N>", "0100nnnn00001011",
 500     "PR = PH2T (PC + 4);",
 501     "if (~doprofile)",
 502     "  gotcall (PR, R[n]);",
 503     "SET_NIP (PT2H (R[n]));",
 504     "cycles += 2;",
 505     "Delay_Slot (PC + 2);",
 506   },
 507
 508   { "", "n", "ldc <REG_N>,<CREG_M>", "0100nnnnmmmm1110",
 509     "CREG (m) = R[n];",
 510     "/* FIXME: user mode */",
 511   },
 512   { "", "n", "ldc <REG_N>,SR", "0100nnnn00001110",
 513     "SET_SR (R[n]);",
 514     "/* FIXME: user mode */",
 515   },
 516   { "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
 517     "SET_MOD (R[n]);",
 518   },
 519 #if 0
 520   { "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
 521     "DBR = R[n];",
 522     "/* FIXME: user mode */",
 523   },
 524 #endif
 525   { "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
 526     "MA (1);",
 527     "CREG (m) = RLAT (R[n]);",
 528     "R[n] += 4;",
 529     "/* FIXME: user mode */",
 530   },
 531   { "n", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
 532     "MA (1);",
 533     "SET_SR (RLAT (R[n]));",
 534     "R[n] += 4;",
 535     "/* FIXME: user mode */",
 536   },
 537   { "n", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
 538     "MA (1);",
 539     "SET_MOD (RLAT (R[n]));",
 540     "R[n] += 4;",
 541   },
 542 #if 0
 543   { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
 544     "MA (1);",
 545     "DBR = RLAT (R[n]);",
 546     "R[n] += 4;",
 547     "/* FIXME: user mode */",
 548   },
 549 #endif
 550
 551   /* sh-dsp */
 552   { "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
 553     "RE = SEXT (i) * 2 + 4 + PH2T (PC);",
 554   },
 555   { "", "", "ldrs @(<disp>,PC)", "10001100i8p1....",
 556     "RS = SEXT (i) * 2 + 4 + PH2T (PC);",
 557   },
 558
 559   { "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
 560     "SREG (m) = R[n];",
 561   },
 562   { "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
 563     "MA (1);",
 564     "SREG (m) = RLAT(R[n]);",
 565     "R[n] += 4;",
 566   },
 567   /* sh2e / sh-dsp (lds <REG_N>,DSR) */
 568   { "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010",
 569     "SET_FPSCR(R[n]);",
 570   },
 571   /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
 572   { "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
 573     "MA (1);",
 574     "SET_FPSCR (RLAT(R[n]));",
 575     "R[n] += 4;",
 576   },
 577
 578   { "", "", "ldtlb", "0000000000111000",
 579     "/* We don't implement cache or tlb, so this is a noop.  */",
 580   },
 581
 582   { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
 583     "macl(&R0,memory,n,m);",
 584   },
 585
 586   { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
 587     "macw(&R0,memory,n,m,endianw);",
 588   },
 589
 590   { "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
 591     "R[n] = SEXT(i);",
 592   },
 593   { "n", "m", "mov <REG_M>,<REG_N>", "0110nnnnmmmm0011",
 594     "R[n] = R[m];",
 595   },
 596
 597   { "0", "", "mov.b @(<disp>,GBR),R0", "11000100i8*1....",
 598     "MA (1);",
 599     "R0 = RSBAT (i + GBR);",
 600     "L (0);",
 601   },
 602   { "0", "m", "mov.b @(<disp>,<REG_M>),R0", "10000100mmmmi4*1",
 603     "MA (1);",
 604     "R0 = RSBAT (i + R[m]);",
 605     "L (0);",
 606   },
 607   { "n", "0m", "mov.b @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1100",
 608     "MA (1);",
 609     "R[n] = RSBAT (R0 + R[m]);",
 610     "L (n);",
 611   },
 612   { "nm", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
 613     "MA (1);",
 614     "R[n] = RSBAT (R[m]);",
 615     "R[m] += 1;",
 616     "L (n);",
 617   },
 618   { "", "mn", "mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000",
 619     "MA (1);",
 620     "WBAT (R[n], R[m]);",
 621   },
 622   { "", "0", "mov.b R0,@(<disp>,GBR)", "11000000i8*1....",
 623     "MA (1);",
 624     "WBAT (i + GBR, R0);",
 625   },
 626   { "", "m0", "mov.b R0,@(<disp>,<REG_M>)", "10000000mmmmi4*1",
 627     "MA (1);",
 628     "WBAT (i + R[m], R0);",
 629   },
 630   { "", "mn0", "mov.b <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0100",
 631     "MA (1);",
 632     "WBAT (R[n] + R0, R[m]);",
 633   },
 634   { "n", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
 635     "MA (1);",
 636     "R[n] -= 1;",
 637     "WBAT (R[n], R[m]);",
 638   },
 639   { "n", "m", "mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000",
 640     "MA (1);",
 641     "R[n] = RSBAT (R[m]);",
 642     "L (n);",
 643   },
 644
 645   { "0", "", "mov.l @(<disp>,GBR),R0", "11000110i8*4....",
 646     "MA (1);",
 647     "R0 = RLAT (i + GBR);",
 648     "L (0);",
 649   },
 650   { "n", "", "mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....",
 651     "MA (1);",
 652     "R[n] = RLAT ((PH2T (PC) & ~3) + 4 + i);",
 653     "L (n);",
 654   },
 655   { "n", "m", "mov.l @(<disp>,<REG_M>),<REG_N>", "0101nnnnmmmmi4*4",
 656     "MA (1);",
 657     "R[n] = RLAT (i + R[m]);",
 658     "L (n);",
 659   },
 660   { "n", "m0", "mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110",
 661     "MA (1);",
 662     "R[n] = RLAT (R0 + R[m]);",
 663     "L (n);",
 664   },
 665   { "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110",
 666     "MA (1);",
 667     "R[n] = RLAT (R[m]);",
 668     "R[m] += 4;",
 669     "L (n);",
 670   },
 671   { "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010",
 672     "MA (1);",
 673     "R[n] = RLAT (R[m]);",
 674     "L (n);",
 675   },
 676   { "", "0", "mov.l R0,@(<disp>,GBR)", "11000010i8*4....",
 677     "MA (1);",
 678     "WLAT (i + GBR, R0);",
 679   },
 680   { "", "nm", "mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4",
 681     "MA (1);",
 682     "WLAT (i + R[n], R[m]);",
 683   },
 684   { "", "nm0", "mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110",
 685     "MA (1);",
 686     "WLAT (R0 + R[n], R[m]);",
 687   },
 688   { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
 689     "MA (1) ;",
 690     "R[n] -= 4;",
 691     "WLAT (R[n], R[m]);",
 692   },
 693   { "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010",
 694     "MA (1);",
 695     "WLAT (R[n], R[m]);",
 696   },
 697
 698   { "0", "", "mov.w @(<disp>,GBR),R0", "11000101i8*2....",
 699     "MA (1);",
 700     "R0 = RSWAT (i + GBR);",
 701     "L (0);",
 702   },
 703   { "n", "", "mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....",
 704     "MA (1);",
 705     "R[n] = RSWAT (PH2T (PC + 4 + i));",
 706     "L (n);",
 707   },
 708   { "0", "m", "mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2",
 709     "MA (1);",
 710     "R0 = RSWAT (i + R[m]);",
 711     "L (0);",
 712   },
 713   { "n", "m0", "mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101",
 714     "MA (1);",
 715     "R[n] = RSWAT (R0 + R[m]);",
 716     "L (n);",
 717   },
 718   { "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101",
 719     "MA (1);",
 720     "R[n] = RSWAT (R[m]);",
 721     "R[m] += 2;",
 722     "L (n);",
 723   },
 724   { "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001",
 725     "MA (1);",
 726     "R[n] = RSWAT (R[m]);",
 727     "L (n);",
 728   },
 729   { "", "0", "mov.w R0,@(<disp>,GBR)", "11000001i8*2....",
 730     "MA (1);",
 731     "WWAT (i + GBR, R0);",
 732   },
 733   { "", "0m", "mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2",
 734     "MA (1);",
 735     "WWAT (i + R[m], R0);",
 736   },
 737   { "", "m0n", "mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101",
 738     "MA (1);",
 739     "WWAT (R0 + R[n], R[m]);",
 740   },
 741   { "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101",
 742     "MA (1);",
 743     "R[n] -= 2;",
 744     "WWAT (R[n], R[m]);",
 745   },
 746   { "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001",
 747     "MA (1);",
 748     "WWAT (R[n], R[m]);",
 749   },
 750
 751   { "0", "", "mova @(<disp>,PC),R0", "11000111i8p4....",
 752     "R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
 753   },
 754
 755   { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
 756     "/* We don't simulate cache, so this insn is identical to mov.  */",
 757     "MA (1);",
 758     "WLAT (R[n], R[0]);",
 759   },
 760
 761   { "n", "", "movt <REG_N>", "0000nnnn00101001",
 762     "R[n] = T;",
 763   },
 764
 765   { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
 766     "MACL = ((int)R[n]) * ((int)R[m]);",
 767   },
 768 #if 0
 769   { "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
 770     "MACL = R[n] * R[m];",
 771   },
 772 #endif
 773
 774   /* muls.w - see muls */
 775   { "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
 776     "MACL = ((int)(short)R[n]) * ((int)(short)R[m]);",
 777   },
 778
 779   /* mulu.w - see mulu */
 780   { "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110",
 781     "MACL = (((unsigned int)(unsigned short)R[n])",
 782     "        * ((unsigned int)(unsigned short)R[m]));",
 783   },
 784
 785   { "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011",
 786     "R[n] = - R[m];",
 787   },
 788
 789   { "n", "m", "negc <REG_M>,<REG_N>", "0110nnnnmmmm1010",
 790     "ult = -T;",
 791     "SET_SR_T (ult > 0);",
 792     "R[n] = ult - R[m];",
 793     "SET_SR_T (T || (R[n] > ult));",
 794   },
 795
 796   { "", "", "nop", "0000000000001001",
 797     "/* nop */",
 798   },
 799
 800   { "n", "m", "not <REG_M>,<REG_N>", "0110nnnnmmmm0111",
 801     "R[n] = ~R[m];",
 802   },
 803
 804   { "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
 805     "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
 806     "/* FIXME: Cache not implemented */",
 807   },
 808
 809   { "", "n", "ocbp @<REG_N>", "0000nnnn10100011",
 810     "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
 811     "/* FIXME: Cache not implemented */",
 812   },
 813
 814   { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
 815     "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
 816     "/* FIXME: Cache not implemented */",
 817   },
 818
 819   { "0", "", "or #<imm>,R0", "11001011i8*1....",
 820     "R0 |= i;",
 821   },
 822   { "n", "m", "or <REG_M>,<REG_N>", "0010nnnnmmmm1011",
 823     "R[n] |= R[m];",
 824   },
 825   { "", "0", "or.b #<imm>,@(R0,GBR)", "11001111i8*1....",
 826     "MA (1);",
 827     "WBAT (R0 + GBR, (RBAT (R0 + GBR) | i));",
 828   },
 829
 830   { "", "n", "pref @<REG_N>", "0000nnnn10000011",
 831     "/* Except for the effect on the cache - which is not simulated -",
 832     "   this is like a nop.  */",
 833   },
 834
 835   { "n", "n", "rotcl <REG_N>", "0100nnnn00100100",
 836     "ult = R[n] < 0;",
 837     "R[n] = (R[n] << 1) | T;",
 838     "SET_SR_T (ult);",
 839   },
 840
 841   { "n", "n", "rotcr <REG_N>", "0100nnnn00100101",
 842     "ult = R[n] & 1;",
 843     "R[n] = (UR[n] >> 1) | (T << 31);",
 844     "SET_SR_T (ult);",
 845   },
 846
 847   { "n", "n", "rotl <REG_N>", "0100nnnn00000100",
 848     "SET_SR_T (R[n] < 0);",
 849     "R[n] <<= 1;",
 850     "R[n] |= T;",
 851   },
 852
 853   { "n", "n", "rotr <REG_N>", "0100nnnn00000101",
 854     "SET_SR_T (R[n] & 1);",
 855     "R[n] = UR[n] >> 1;",
 856     "R[n] |= (T << 31);",
 857   },
 858
 859   { "", "", "rte", "0000000000101011",
 860 #if 0
 861     /* SH-[12] */
 862     "int tmp = PC;",
 863     "SET_NIP (PT2H (RLAT (R[15]) + 2));",
 864     "R[15] += 4;",
 865     "SET_SR (RLAT (R[15]) & 0x3f3);",
 866     "R[15] += 4;",
 867     "Delay_Slot (PC + 2);",
 868 #else
 869     "SET_SR (SSR);",
 870     "SET_NIP (PT2H (SPC));",
 871     "cycles += 2;",
 872     "Delay_Slot (PC + 2);",
 873 #endif
 874   },
 875
 876   { "", "", "rts", "0000000000001011",
 877     "SET_NIP (PT2H (PR));",
 878     "cycles += 2;",
 879     "Delay_Slot (PC + 2);",
 880   },
 881
 882   /* sh-dsp */
 883   { "", "n", "setrc <REG_N>", "0100nnnn00010100",
 884     "SET_RC (R[n]);",
 885   },
 886   { "", "", "setrc #<imm>", "10000010i8*1....",
 887     /* It would be more realistic to let loop_start point to some static
 888        memory that contains an illegal opcode and then give a bus error when
 889        the loop is eventually encountered, but it seems not only simpler,
 890        but also more debugging-friendly to just catch the failure here.  */
 891     "if (BUSERROR (RS | RE, maskw))",
 892     "  RAISE_EXCEPTION (SIGILL);",
 893     "else {",
 894     "  SET_RC (i);",
 895     "  loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);",
 896     "  CHECK_INSN_PTR (insn_ptr);",
 897     "}",
 898   },
 899
 900   { "", "", "sets", "0000000001011000",
 901     "SET_SR_S (1);",
 902   },
 903
 904   { "", "", "sett", "0000000000011000",
 905     "SET_SR_T (1);",
 906   },
 907
 908   { "n", "mn", "shad <REG_M>,<REG_N>", "0100nnnnmmmm1100",
 909     "R[n] = (R[m] < 0) ? (R[n] >> ((-R[m])&0x1f)) : (R[n] << (R[m] & 0x1f));",
 910   },
 911
 912   { "n", "n", "shal <REG_N>", "0100nnnn00100000",
 913     "SET_SR_T (R[n] < 0);",
 914     "R[n] <<= 1;",
 915   },
 916
 917   { "n", "n", "shar <REG_N>", "0100nnnn00100001",
 918     "SET_SR_T (R[n] & 1);",
 919     "R[n] = R[n] >> 1;",
 920   },
 921
 922   { "n", "mn", "shld <REG_M>,<REG_N>", "0100nnnnmmmm1101",
 923     "R[n] = (R[m] < 0) ? (UR[n] >> ((-R[m])&0x1f)): (R[n] << (R[m] & 0x1f));",
 924   },
 925
 926   { "n", "n", "shll <REG_N>", "0100nnnn00000000",
 927     "SET_SR_T (R[n] < 0);",
 928     "R[n] <<= 1;",
 929   },
 930
 931   { "n", "n", "shll2 <REG_N>", "0100nnnn00001000",
 932     "R[n] <<= 2;",
 933   },
 934   { "n", "n", "shll8 <REG_N>", "0100nnnn00011000",
 935     "R[n] <<= 8;",
 936   },
 937   { "n", "n", "shll16 <REG_N>", "0100nnnn00101000",
 938     "R[n] <<= 16;",
 939   },
 940
 941   { "n", "n", "shlr <REG_N>", "0100nnnn00000001",
 942     "SET_SR_T (R[n] & 1);",
 943     "R[n] = UR[n] >> 1;",
 944   },
 945
 946   { "n", "n", "shlr2 <REG_N>", "0100nnnn00001001",
 947     "R[n] = UR[n] >> 2;",
 948   },
 949   { "n", "n", "shlr8 <REG_N>", "0100nnnn00011001",
 950     "R[n] = UR[n] >> 8;",
 951   },
 952   { "n", "n", "shlr16 <REG_N>", "0100nnnn00101001",
 953     "R[n] = UR[n] >> 16;",
 954   },
 955
 956   { "", "", "sleep", "0000000000011011",
 957     "nip += trap (0xc3, R0, PC, memory, maskl, maskw, endianw);",
 958   },
 959
 960   { "n", "", "stc <CREG_M>,<REG_N>", "0000nnnnmmmm0010",
 961     "R[n] = CREG (m);",
 962   },
 963
 964 #if 0
 965   { "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
 966     "R[n] = SGR;",
 967   },
 968   { "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
 969     "R[n] = DBR;",
 970   },
 971 #endif
 972   { "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
 973     "MA (1);",
 974     "R[n] -= 4;",
 975     "WLAT (R[n], CREG (m));",
 976   },
 977 #if 0
 978   { "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
 979     "MA (1);",
 980     "R[n] -= 4;",
 981     "WLAT (R[n], SGR);",
 982   },
 983   { "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
 984     "MA (1);",
 985     "R[n] -= 4;",
 986     "WLAT (R[n], DBR);",
 987   },
 988 #endif
 989
 990   { "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
 991     "R[n] = SREG (m);",
 992   },
 993   { "n", "n", "sts.l <SREG_M>,@-<REG_N>", "0100nnnnssss0010",
 994     "MA (1);",
 995     "R[n] -= 4;",
 996     "WLAT (R[n], SREG (m));",
 997   },
 998
 999   { "n", "nm", "sub <REG_M>,<REG_N>", "0011nnnnmmmm1000",
1000     "R[n] -= R[m];",
1001   },
1002
1003   { "n", "nm", "subc <REG_M>,<REG_N>", "0011nnnnmmmm1010",
1004     "ult = R[n] - T;",
1005     "SET_SR_T (ult > R[n]);",
1006     "R[n] = ult - R[m];",
1007     "SET_SR_T (T || (R[n] > ult));",
1008   },
1009
1010   { "n", "nm", "subv <REG_M>,<REG_N>", "0011nnnnmmmm1011",
1011     "ult = R[n] - R[m];",
1012     "SET_SR_T (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31);",
1013     "R[n] = ult;",
1014   },
1015
1016   { "n", "nm", "swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000",
1017     "R[n] = ((R[m] & 0xffff0000)",
1018     "        | ((R[m] << 8) & 0xff00)",
1019     "        | ((R[m] >> 8) & 0x00ff));",
1020   },
1021   { "n", "nm", "swap.w <REG_M>,<REG_N>", "0110nnnnmmmm1001",
1022     "R[n] = (((R[m] << 16) & 0xffff0000)",
1023     "        | ((R[m] >> 16) & 0x00ffff));",
1024   },
1025
1026   { "", "n", "tas.b @<REG_N>", "0100nnnn00011011",
1027     "MA (1);",
1028     "ult = RBAT(R[n]);",
1029     "SET_SR_T (ult == 0);",
1030     "WBAT(R[n],ult|0x80);",
1031   },
1032
1033   { "0", "", "trapa #<imm>", "11000011i8*1....",
1034     "long imm = 0xff & i;",
1035     "if (i < 20 || i == 33 || i == 34 || i == 0xc3)",
1036     "  nip += trap (i, R, PC, memory, maskl, maskw,endianw);",
1037 #if 0
1038     "else {",
1039     /* SH-[12] */
1040     "  R[15]-=4;",
1041     "  WLAT (R[15], GET_SR());",
1042     "  R[15]-=4;",
1043     "  WLAT (R[15], PH2T (PC + 2));",
1044 #else
1045     "else if (!SR_BL) {",
1046     "  SSR = GET_SR();",
1047     "  SPC = PH2T (PC + 2);",
1048     "  SET_SR (GET_SR() | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);",
1049     "  /* FIXME: EXPEVT = 0x00000160; */",
1050 #endif
1051     "  SET_NIP (PT2H (RLAT (VBR + (imm<<2))));",
1052     "}",
1053   },
1054
1055   { "", "mn", "tst <REG_M>,<REG_N>", "0010nnnnmmmm1000",
1056     "SET_SR_T ((R[n] & R[m]) == 0);",
1057   },
1058   { "", "0", "tst #<imm>,R0", "11001000i8*1....",
1059     "SET_SR_T ((R0 & i) == 0);",
1060   },
1061   { "", "0", "tst.b #<imm>,@(R0,GBR)", "11001100i8*1....",
1062     "MA (1);",
1063     "SET_SR_T ((RBAT (GBR+R0) & i) == 0);",
1064   },
1065
1066   { "", "0", "xor #<imm>,R0", "11001010i8*1....",
1067     "R0 ^= i;",
1068   },
1069   { "n", "mn", "xor <REG_M>,<REG_N>", "0010nnnnmmmm1010",
1070     "R[n] ^= R[m];",
1071   },
1072   { "", "0", "xor.b #<imm>,@(R0,GBR)", "11001110i8*1....",
1073     "MA (1);",
1074     "ult = RBAT (GBR+R0);",
1075     "ult ^= i;",
1076     "WBAT (GBR + R0, ult);",
1077   },
1078
1079   { "n", "nm", "xtrct <REG_M>,<REG_N>", "0010nnnnmmmm1101",
1080     "R[n] = (((R[n] >> 16) & 0xffff)",
1081     "        | ((R[m] << 16) & 0xffff0000));",
1082   },
1083
1084 #if 0
1085   { "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110",
1086     "divl(0,R[n],R[m]);",
1087   },
1088   { "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101",
1089     "divl(0,R[n],R[m]);",
1090   },
1091 #endif
1092
1093   {0, 0}};
1094
1095 op movsxy_tab[] =
1096 {
1097 /* If this is disabled, the simulator speeds up by about 12% on a
1098    450 MHz PIII - 9% with ACE_FAST.
1099    Maybe we should have separate simulator loops?  */
1100 #if 1
1101   { "n", "n", "movs.w @-<REG_N>,<DSP_REG_M>", "111101NNMMMM0000",
1102     "MA (1);",
1103     "R[n] -= 2;",
1104     "DSP_R (m) = RSWAT (R[n]) << 16;",
1105     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1106   },
1107   { "", "n",  "movs.w @<REG_N>,<DSP_REG_M>",  "111101NNMMMM0100",
1108     "MA (1);",
1109     "DSP_R (m) = RSWAT (R[n]) << 16;",
1110     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1111   },
1112   { "n", "n", "movs.w @<REG_N>+,<DSP_REG_M>", "111101NNMMMM1000",
1113     "MA (1);",
1114     "DSP_R (m) = RSWAT (R[n]) << 16;",
1115     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1116     "R[n] += 2;",
1117   },
1118   { "n", "n8","movs.w @<REG_N>+REG_8,<DSP_REG_M>", "111101NNMMMM1100",
1119     "MA (1);",
1120     "DSP_R (m) = RSWAT (R[n]) << 16;",
1121     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1122     "R[n] += R[8];",
1123   },
1124   { "n", "n", "movs.w @-<REG_N>,<DSP_GRD_M>", "111101NNGGGG0000",
1125     "MA (1);",
1126     "R[n] -= 2;",
1127     "DSP_R (m) = RSWAT (R[n]);",
1128   },
1129   { "", "n",  "movs.w @<REG_N>,<DSP_GRD_M>",  "111101NNGGGG0100",
1130     "MA (1);",
1131     "DSP_R (m) = RSWAT (R[n]);",
1132   },
1133   { "n", "n", "movs.w @<REG_N>+,<DSP_GRD_M>", "111101NNGGGG1000",
1134     "MA (1);",
1135     "DSP_R (m) = RSWAT (R[n]);",
1136     "R[n] += 2;",
1137   },
1138   { "n", "n8","movs.w @<REG_N>+REG_8,<DSP_GRD_M>", "111101NNGGGG1100",
1139     "MA (1);",
1140     "DSP_R (m) = RSWAT (R[n]);",
1141     "R[n] += R[8];",
1142   },
1143   { "n", "n", "movs.w <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0001",
1144     "MA (1);",
1145     "R[n] -= 2;",
1146     "WWAT (R[n], DSP_R (m) >> 16);",
1147   },
1148   { "", "n",  "movs.w <DSP_REG_M>,@<REG_N>",  "111101NNMMMM0101",
1149     "MA (1);",
1150     "WWAT (R[n], DSP_R (m) >> 16);",
1151   },
1152   { "n", "n", "movs.w <DSP_REG_M>,@<REG_N>+", "111101NNMMMM1001",
1153     "MA (1);",
1154     "WWAT (R[n], DSP_R (m) >> 16);",
1155     "R[n] += 2;",
1156   },
1157   { "n", "n8","movs.w <DSP_REG_M>,@<REG_N>+REG_8", "111101NNMMMM1101",
1158     "MA (1);",
1159     "WWAT (R[n], DSP_R (m) >> 16);",
1160     "R[n] += R[8];",
1161   },
1162   { "n", "n", "movs.w <DSP_GRD_M>,@-<REG_N>", "111101NNGGGG0001",
1163     "MA (1);",
1164     "R[n] -= 2;",
1165     "WWAT (R[n], SEXT (DSP_R (m)));",
1166   },
1167   { "", "n",  "movs.w <DSP_GRD_M>,@<REG_N>",  "111101NNGGGG0101",
1168     "MA (1);",
1169     "WWAT (R[n], SEXT (DSP_R (m)));",
1170   },
1171   { "n", "n", "movs.w <DSP_GRD_M>,@<REG_N>+", "111101NNGGGG1001",
1172     "MA (1);",
1173     "WWAT (R[n], SEXT (DSP_R (m)));",
1174     "R[n] += 2;",
1175   },
1176   { "n", "n8","movs.w <DSP_GRD_M>,@<REG_N>+REG_8", "111101NNGGGG1101",
1177     "MA (1);",
1178     "WWAT (R[n], SEXT (DSP_R (m)));",
1179     "R[n] += R[8];",
1180   },
1181   { "n", "n", "movs.l @-<REG_N>,<DSP_REG_M>", "111101NNMMMM0010",
1182     "MA (1);",
1183     "R[n] -= 4;",
1184     "DSP_R (m) = RLAT (R[n]);",
1185     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1186   },
1187   { "", "n",  "movs.l @<REG_N>,<DSP_REG_M>",  "111101NNMMMM0110",
1188     "MA (1);",
1189     "DSP_R (m) = RLAT (R[n]);",
1190     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1191   },
1192   { "n", "n", "movs.l @<REG_N>+,<DSP_REG_M>", "111101NNMMMM1010",
1193     "MA (1);",
1194     "DSP_R (m) = RLAT (R[n]);",
1195     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1196     "R[n] += 4;",
1197   },
1198   { "n", "n8","movs.l @<REG_N>+REG_8,<DSP_REG_M>", "111101NNMMMM1110",
1199     "MA (1);",
1200     "DSP_R (m) = RLAT (R[n]);",
1201     "DSP_GRD (m) = SIGN32 (DSP_R (m));",
1202     "R[n] += R[8];",
1203   },
1204   { "n", "n", "movs.l <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0011",
1205     "MA (1);",
1206     "R[n] -= 4;",
1207     "WLAT (R[n], DSP_R (m));",
1208   },
1209   { "", "n",  "movs.l <DSP_REG_M>,@<REG_N>",  "111101NNMMMM0111",
1210     "MA (1);",
1211     "WLAT (R[n], DSP_R (m));",
1212   },
1213   { "n", "n", "movs.l <DSP_REG_M>,@<REG_N>+", "111101NNMMMM1011",
1214     "MA (1);",
1215     "WLAT (R[n], DSP_R (m));",
1216     "R[n] += 4;",
1217   },
1218   { "n", "n8","movs.l <DSP_REG_M>,@<REG_N>+REG_8", "111101NNMMMM1111",
1219     "MA (1);",
1220     "WLAT (R[n], DSP_R (m));",
1221     "R[n] += R[8];",
1222   },
1223   { "n", "n", "movs.l <DSP_GRD_M>,@-<REG_N>", "111101NNGGGG0011",
1224     "MA (1);",
1225     "R[n] -= 4;",
1226     "WLAT (R[n], SEXT (DSP_R (m)));",
1227   },
1228   { "", "n",  "movs.l <DSP_GRD_M>,@<REG_N>",  "111101NNGGGG0111",
1229     "MA (1);",
1230     "WLAT (R[n], SEXT (DSP_R (m)));",
1231   },
1232   { "n", "n", "movs.l <DSP_GRD_M>,@<REG_N>+", "111101NNGGGG1011",
1233     "MA (1);",
1234     "WLAT (R[n], SEXT (DSP_R (m)));",
1235     "R[n] += 4;",
1236   },
1237   { "n", "n8","movs.l <DSP_GRD_M>,@<REG_N>+REG_8", "111101NNGGGG1111",
1238     "MA (1);",
1239     "WLAT (R[n], SEXT (DSP_R (m)));",
1240     "R[n] += R[8];",
1241   },
1242   { "", "n", "movx.w @<REG_x>,<DSP_XX>",   "111100xxXX000100",
1243     "DSP_R (m) = RSWAT (R[n]) << 16;",
1244     "iword &= 0xfd53; goto top;",
1245   },
1246   { "n", "n", "movx.w @<REG_x>+,<DSP_XX>", "111100xxXX001000",
1247     "DSP_R (m) = RSWAT (R[n]) << 16;",
1248     "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
1249     "iword &= 0xfd53; goto top;",
1250   },
1251   { "n", "n8","movx.w @<REG_x>+REG_8,<DSP_XX>", "111100xxXX001100",
1252     "DSP_R (m) = RSWAT (R[n]) << 16;",
1253     "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
1254     "iword &= 0xfd53; goto top;",
1255   },
1256   { "", "n", "movx.w <DSP_Aa>,@<REG_x>",   "111100xxaa100100",
1257     "WWAT (R[n], DSP_R (m) >> 16);",
1258     "iword &= 0xfd53; goto top;",
1259   },
1260   { "n", "n", "movx.w <DSP_Aa>,@<REG_x>+", "111100xxaa101000",
1261     "WWAT (R[n], DSP_R (m) >> 16);",
1262     "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
1263     "iword &= 0xfd53; goto top;",
1264   },
1265   { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100",
1266     "WWAT (R[n], DSP_R (m) >> 16);",
1267     "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
1268     "iword &= 0xfd53; goto top;",
1269   },
1270   { "", "n", "movy.w @<REG_y>,<DSP_YY>",   "111100yyYY000001",
1271     "DSP_R (m) = RSWAT (R[n]) << 16;",
1272   },
1273   { "n", "n", "movy.w @<REG_y>+,<DSP_YY>", "111100yyYY000010",
1274     "DSP_R (m) = RSWAT (R[n]) << 16;",
1275     "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
1276   },
1277   { "n", "n9","movy.w @<REG_y>+REG_9,<DSP_YY>", "111100yyYY000011",
1278     "DSP_R (m) = RSWAT (R[n]) << 16;",
1279     "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
1280   },
1281   { "", "n", "movy.w <DSP_Aa>,@<REG_y>",   "111100yyAA010001",
1282     "WWAT (R[n], DSP_R (m) >> 16);",
1283   },
1284   { "n", "n", "movy.w <DSP_Aa>,@<REG_y>+", "111100yyAA010010",
1285     "WWAT (R[n], DSP_R (m) >> 16);",
1286     "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
1287   },
1288   { "n", "n9", "movy.w <DSP_Aa>,@<REG_y>+REG_9", "111100yyAA010011",
1289     "WWAT (R[n], DSP_R (m) >> 16);",
1290     "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
1291   },
1292   { "", "", "nopx nopy", "1111000000000000",
1293     "/* nop */",
1294   },
1295   { "", "", "ppi", "1111100000000000",
1296     "ppi_insn (RIAT (nip));",
1297     "nip += 2;",
1298     "iword &= 0xf7ff; goto top;",
1299   },
1300 #endif
1301   {0, 0}};
1302
1303 op ppi_tab[] =
1304 {
1305   { "","", "pshl #<imm>,dz",    "00000iiim16.zzzz",
1306     "int Sz = DSP_R (z) & 0xffff0000;",
1307     "",
1308     "if (i <= 16)",
1309     "  res = Sz << i;",
1310     "else if (i >= 128 - 16)",
1311     "  res = (unsigned) Sz >> 128 - i;  /* no sign extension */",
1312     "else",
1313     "  {",
1314     "    RAISE_EXCEPTION (SIGILL);",
1315     "    return;",
1316     "  }",
1317     "res &= 0xffff0000;",
1318     "res_grd = 0;",
1319     "goto logical;",
1320   },
1321   { "","", "psha #<imm>,dz",    "00010iiim32.zzzz",
1322     "int Sz = DSP_R (z);",
1323     "int Sz_grd = GET_DSP_GRD (z);",
1324     "",
1325     "if (i <= 32)",
1326     "  {",
1327     "    if (i == 32)",
1328     "      {",
1329     "        res = 0;",
1330     "        res_grd = Sz;",
1331     "      }",
1332     "    else",
1333     "      {",
1334     "        res = Sz << i;",
1335     "        res_grd = Sz_grd << i | (unsigned) Sz >> 32 - i;",
1336     "      }",
1337     "    res_grd = SEXT (res_grd);",
1338     "    carry = res_grd & 1;",
1339     "  }",
1340     "else if (i >= 96)",
1341     "  {",
1342     "    i = 128 - i;",
1343     "    if (i == 32)",
1344     "      {",
1345     "        res_grd = SIGN32 (Sz_grd);",
1346     "        res = Sz_grd;",
1347     "      }",
1348     "    else",
1349     "      {",
1350     "        res = Sz >> i | Sz_grd << 32 - i;",
1351     "        res_grd = Sz_grd >> i;",
1352     "      }",
1353     "    carry = Sz >> (i - 1) & 1;",
1354     "  }",
1355     "else",
1356     "  {",
1357     "    RAISE_EXCEPTION (SIGILL);",
1358     "    return;",
1359     "  }",
1360     "COMPUTE_OVERFLOW;",
1361     "greater_equal = 0;",
1362   },
1363   { "","", "pmuls Se,Sf,Dg",    "0100eeffxxyygguu",
1364     "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
1365     "if (res == 0x80000000)",
1366     "  res = 0x7fffffff;",
1367     "DSP_R (g) = res;",
1368     "DSP_GRD (g) = SIGN32 (res);",
1369     "return;",
1370   },
1371   { "","", "psub Sx,Sy,Du pmuls Se,Sf,Dg",      "0110eeffxxyygguu",
1372     "int Sx = DSP_R (x);",
1373     "int Sx_grd = GET_DSP_GRD (x);",
1374     "int Sy = DSP_R (y);",
1375     "int Sy_grd = SIGN32 (Sy);",
1376     "",
1377     "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
1378     "if (res == 0x80000000)",
1379     "  res = 0x7fffffff;",
1380     "DSP_R (g) = res;",
1381     "DSP_GRD (g) = SIGN32 (res);",
1382     "",
1383     "z = u;",
1384     "res = Sx - Sy;",
1385     "carry = (unsigned) res > (unsigned) Sx;",
1386     "res_grd = Sx_grd - Sy_grd - carry;",
1387     "COMPUTE_OVERFLOW;",
1388     "ADD_SUB_GE;",
1389   },
1390   { "","", "padd Sx,Sy,Du pmuls Se,Sf,Dg",      "0111eeffxxyygguu",
1391     "int Sx = DSP_R (x);",
1392     "int Sx_grd = GET_DSP_GRD (x);",
1393     "int Sy = DSP_R (y);",
1394     "int Sy_grd = SIGN32 (Sy);",
1395     "",
1396     "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
1397     "if (res == 0x80000000)",
1398     "  res = 0x7fffffff;",
1399     "DSP_R (g) = res;",
1400     "DSP_GRD (g) = SIGN32 (res);",
1401     "",
1402     "z = u;",
1403     "res = Sx + Sy;",
1404     "carry = (unsigned) res < (unsigned) Sx;",
1405     "res_grd = Sx_grd + Sy_grd + carry;",
1406     "COMPUTE_OVERFLOW;",
1407   },
1408   { "","", "psubc Sx,Sy,Dz",            "10100000xxyyzzzz",
1409     "int Sx = DSP_R (x);",
1410     "int Sx_grd = GET_DSP_GRD (x);",
1411     "int Sy = DSP_R (y);",
1412     "int Sy_grd = SIGN32 (Sy);",
1413     "",
1414     "res = Sx - Sy - (DSR & 1);",
1415     "carry = (unsigned) res > (unsigned) Sx || (res == Sx && Sy);",
1416     "res_grd = Sx_grd + Sy_grd + carry;",
1417     "COMPUTE_OVERFLOW;",
1418     "ADD_SUB_GE;",
1419     "DSR &= ~0xf1;\n",
1420     "if (res || res_grd)\n",
1421     "  DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
1422     "else\n",
1423     "  DSR |= DSR_MASK_Z | overflow;\n",
1424     "DSR |= carry;\n",
1425     "goto assign_z;\n",
1426   },
1427   { "","", "paddc Sx,Sy,Dz",    "10110000xxyyzzzz",
1428     "int Sx = DSP_R (x);",
1429     "int Sx_grd = GET_DSP_GRD (x);",
1430     "int Sy = DSP_R (y);",
1431     "int Sy_grd = SIGN32 (Sy);",
1432     "",
1433     "res = Sx + Sy + (DSR & 1);",
1434     "carry = (unsigned) res < (unsigned) Sx || (res == Sx && Sy);",
1435     "res_grd = Sx_grd + Sy_grd + carry;",
1436     "COMPUTE_OVERFLOW;",
1437     "ADD_SUB_GE;",
1438     "DSR &= ~0xf1;\n",
1439     "if (res || res_grd)\n",
1440     "  DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
1441     "else\n",
1442     "  DSR |= DSR_MASK_Z | overflow;\n",
1443     "DSR |= carry;\n",
1444     "goto assign_z;\n",
1445   },
1446   { "","", "pcmp Sx,Sy",        "10000100xxyy....",
1447     "int Sx = DSP_R (x);",
1448     "int Sx_grd = GET_DSP_GRD (x);",
1449     "int Sy = DSP_R (y);",
1450     "int Sy_grd = SIGN32 (Sy);",
1451     "",
1452     "z = 17; /* Ignore result.  */",
1453     "res = Sx - Sy;",
1454     "carry = (unsigned) res > (unsigned) Sx;",
1455     "res_grd = Sx_grd - Sy_grd - carry;",
1456     "COMPUTE_OVERFLOW;",
1457     "ADD_SUB_GE;",
1458   },
1459   { "","", "pwsb Sx,Sy,Dz",     "10100100xxyyzzzz",
1460   },
1461   { "","", "pwad Sx,Sy,Dz",     "10110100xxyyzzzz",
1462   },
1463   { "","", "pabs Sx,Dz",        "10001000xx..zzzz",
1464     "res = DSP_R (x);",
1465     "res_grd = GET_DSP_GRD (x);",
1466     "if (res >= 0)",
1467     "  carry = 0;",
1468     "else",
1469     "  {",
1470     "    res = -res;",
1471     "    carry = (res != 0); /* The manual has a bug here.  */",
1472     "    res_grd = -res_grd - carry;",
1473     "  }",
1474     "COMPUTE_OVERFLOW;",
1475     "/* ??? The re-computing of overflow after",
1476     "   saturation processing is specific to pabs.  */",
1477     "overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;",
1478     "ADD_SUB_GE;",
1479   },
1480   { "","", "prnd Sx,Dz",        "10011000xx..zzzz",
1481     "int Sx = DSP_R (x);",
1482     "int Sx_grd = GET_DSP_GRD (x);",
1483     "",
1484     "res = (Sx + 0x8000) & 0xffff0000;",
1485     "carry = (unsigned) res < (unsigned) Sx;",
1486     "res_grd = Sx_grd + carry;",
1487     "COMPUTE_OVERFLOW;",
1488     "ADD_SUB_GE;",
1489   },
1490   { "","", "pabs Sy,Dz",        "10101000..yyzzzz",
1491     "res = DSP_R (y);",
1492     "res_grd = 0;",
1493     "overflow = 0;",
1494     "greater_equal = DSR_MASK_G;",
1495     "if (res >= 0)",
1496     "  carry = 0;",
1497     "else",
1498     "  {",
1499     "    res = -res;",
1500     "    carry = 1;",
1501     "    if (res < 0)",
1502     "      {",
1503     "        if (S)",
1504     "          res = 0x7fffffff;",
1505     "        else",
1506     "          {",
1507     "            overflow = DSR_MASK_V;",
1508     "            greater_equal = 0;",
1509     "          }",
1510     "      }",
1511     "  }",
1512   },
1513   { "","", "prnd Sy,Dz",        "10111000..yyzzzz",
1514     "int Sy = DSP_R (y);",
1515     "int Sy_grd = SIGN32 (Sy);",
1516     "",
1517     "res = (Sy + 0x8000) & 0xffff0000;",
1518     "carry = (unsigned) res < (unsigned) Sy;",
1519     "res_grd = Sy_grd + carry;",
1520     "COMPUTE_OVERFLOW;",
1521     "ADD_SUB_GE;",
1522   },
1523   { "","", "(if cc) pshl Sx,Sy,Dz",     "100000ccxxyyzzzz",
1524     "int Sx = DSP_R (x) & 0xffff0000;",
1525     "int Sy = DSP_R (y) >> 16 & 0x7f;",
1526     "",
1527     "if (Sy <= 16)",
1528     "  res = Sx << Sy;",
1529     "else if (Sy >= 128 - 16)",
1530     "  res = (unsigned) Sx >> 128 - Sy; /* no sign extension */",
1531     "else",
1532     "  {",
1533     "    RAISE_EXCEPTION (SIGILL);",
1534     "    return;",
1535     "  }",
1536     "goto cond_logical;",
1537   },
1538   { "","", "(if cc) psha Sx,Sy,Dz",     "100100ccxxyyzzzz",
1539     "int Sx = DSP_R (x);",
1540     "int Sx_grd = GET_DSP_GRD (x);",
1541     "int Sy = DSP_R (y) >> 16 & 0x7f;",
1542     "",
1543     "if (Sy <= 32)",
1544     "  {",
1545     "    if (Sy == 32)",
1546     "      {",
1547     "        res = 0;",
1548     "        res_grd = Sx;",
1549     "      }",
1550     "    else",
1551     "      {",
1552     "        res = Sx << Sy;",
1553     "        res_grd = Sx_grd << Sy | (unsigned) Sx >> 32 - Sy;",
1554     "      }",
1555     "    res_grd = SEXT (res_grd);",
1556     "    carry = res_grd & 1;",
1557     "  }",
1558     "else if (Sy >= 96)",
1559     "  {",
1560     "    Sy = 128 - Sy;",
1561     "    if (Sy == 32)",
1562     "      {",
1563     "        res_grd = SIGN32 (Sx_grd);",
1564     "        res = Sx_grd;",
1565     "      }",
1566     "    else",
1567     "      {",
1568     "        res = Sx >> Sy | Sx_grd << 32 - Sy;",
1569     "        res_grd = Sx_grd >> Sy;",
1570     "      }",
1571     "    carry = Sx >> (Sy - 1) & 1;",
1572     "  }",
1573     "else",
1574     "  {",
1575     "    RAISE_EXCEPTION (SIGILL);",
1576     "    return;",
1577     "  }",
1578     "COMPUTE_OVERFLOW;",
1579     "greater_equal = 0;",
1580   },
1581   { "","", "(if cc) psub Sx,Sy,Dz",     "101000ccxxyyzzzz",
1582     "int Sx = DSP_R (x);",
1583     "int Sx_grd = GET_DSP_GRD (x);",
1584     "int Sy = DSP_R (y);",
1585     "int Sy_grd = SIGN32 (Sy);",
1586     "",
1587     "res = Sx - Sy;",
1588     "carry = (unsigned) res > (unsigned) Sx;",
1589     "res_grd = Sx_grd - Sy_grd - carry;",
1590     "COMPUTE_OVERFLOW;",
1591     "ADD_SUB_GE;",
1592   },
1593   { "","", "(if cc) padd Sx,Sy,Dz",     "101100ccxxyyzzzz",
1594     "int Sx = DSP_R (x);",
1595     "int Sx_grd = GET_DSP_GRD (x);",
1596     "int Sy = DSP_R (y);",
1597     "int Sy_grd = SIGN32 (Sy);",
1598     "",
1599     "res = Sx + Sy;",
1600     "carry = (unsigned) res < (unsigned) Sx;",
1601     "res_grd = Sx_grd + Sy_grd + carry;",
1602     "COMPUTE_OVERFLOW;",
1603     "ADD_SUB_GE;",
1604   },
1605   { "","", "(if cc) pand Sx,Sy,Dz",     "100101ccxxyyzzzz",
1606     "res = DSP_R (x) & DSP_R (y);",
1607   "cond_logical:",
1608     "res &= 0xffff0000;",
1609     "res_grd = 0;",
1610     "if (iword & 0x200)\n",
1611     "  goto assign_z;\n",
1612   "logical:",
1613     "carry = 0;",
1614     "overflow = 0;",
1615     "greater_equal = 0;",
1616     "DSR &= ~0xf1;\n",
1617     "if (res)\n",
1618     "  DSR |= res >> 26 & DSR_MASK_N;\n",
1619     "else\n",
1620     "  DSR |= DSR_MASK_Z;\n",
1621     "goto assign_dc;\n",
1622   },
1623   { "","", "(if cc) pxor Sx,Sy,Dz",     "101001ccxxyyzzzz",
1624     "res = DSP_R (x) ^ DSP_R (y);",
1625     "goto cond_logical;",
1626   },
1627   { "","", "(if cc) por Sx,Sy,Dz",      "101101ccxxyyzzzz",
1628     "res = DSP_R (x) | DSP_R (y);",
1629     "goto cond_logical;",
1630   },
1631   { "","", "(if cc) pdec Sx,Dz",        "100010ccxx..zzzz",
1632     "int Sx = DSP_R (x);",
1633     "int Sx_grd = GET_DSP_GRD (x);",
1634     "",
1635     "res = Sx - 0x10000;",
1636     "carry = res > Sx;",
1637     "res_grd = Sx_grd - carry;",
1638     "COMPUTE_OVERFLOW;",
1639     "ADD_SUB_GE;",
1640     "res &= 0xffff0000;",
1641   },
1642   { "","", "(if cc) pinc Sx,Dz",        "100110ccxx..zzzz",
1643     "int Sx = DSP_R (x);",
1644     "int Sx_grd = GET_DSP_GRD (x);",
1645     "",
1646     "res = Sx + 0x10000;",
1647     "carry = res < Sx;",
1648     "res_grd = Sx_grd + carry;",
1649     "COMPUTE_OVERFLOW;",
1650     "ADD_SUB_GE;",
1651     "res &= 0xffff0000;",
1652   },
1653   { "","", "(if cc) pdec Sy,Dz",        "101010cc..yyzzzz",
1654     "int Sy = DSP_R (y);",
1655     "int Sy_grd = SIGN32 (Sy);",
1656     "",
1657     "res = Sy - 0x10000;",
1658     "carry = res > Sy;",
1659     "res_grd = Sy_grd - carry;",
1660     "COMPUTE_OVERFLOW;",
1661     "ADD_SUB_GE;",
1662     "res &= 0xffff0000;",
1663   },
1664   { "","", "(if cc) pinc Sy,Dz",        "101110cc..yyzzzz",
1665     "int Sy = DSP_R (y);",
1666     "int Sy_grd = SIGN32 (Sy);",
1667     "",
1668     "res = Sy + 0x10000;",
1669     "carry = res < Sy;",
1670     "res_grd = Sy_grd + carry;",
1671     "COMPUTE_OVERFLOW;",
1672     "ADD_SUB_GE;",
1673     "res &= 0xffff0000;",
1674   },
1675   { "","", "(if cc) pclr Dz",           "100011cc....zzzz",
1676     "res = 0;",
1677     "res_grd = 0;",
1678     "carry = 0;",
1679     "overflow = 0;",
1680     "greater_equal = 1;",
1681   },
1682   { "","", "(if cc) pdmsb Sx,Dz",       "100111ccxx..zzzz",
1683     "unsigned Sx = DSP_R (x);",
1684     "int Sx_grd = GET_DSP_GRD (x);",
1685     "int i = 16;",
1686     "",
1687     "if (Sx_grd < 0)",
1688     "  {",
1689     "    Sx_grd = ~Sx_grd;",
1690     "    Sx = ~Sx;",
1691     "  }",
1692     "if (Sx_grd)",
1693     "  {",
1694     "    Sx = Sx_grd;",
1695     "    res = -2;",
1696     "  }",
1697     "else if (Sx)",
1698     "  res = 30;",
1699     "else",
1700     "  res = 31;",
1701     "do",
1702     "  {",
1703     "    if (Sx & ~0 << i)",
1704     "      {",
1705     "        res -= i;",
1706     "        Sx >>= i;",
1707     "      }",
1708     "  }",
1709     "while (i >>= 1);",
1710     "res <<= 16;",
1711     "res_grd = SIGN32 (res);",
1712     "carry = 0;",
1713     "overflow = 0;",
1714     "ADD_SUB_GE;",
1715   },
1716   { "","", "(if cc) pdmsb Sy,Dz",       "101111cc..yyzzzz",
1717     "unsigned Sy = DSP_R (y);",
1718     "int i;",
1719     "",
1720     "if (Sy < 0)",
1721     "  Sy = ~Sy;",
1722     "Sy <<= 1;",
1723     "res = 31;",
1724     "do",
1725     "  {",
1726     "    if (Sy & ~0 << i)",
1727     "      {",
1728     "        res -= i;",
1729     "        Sy >>= i;",
1730     "      }",
1731     "  }",
1732     "while (i >>= 1);",
1733     "res <<= 16;",
1734     "res_grd = SIGN32 (res);",
1735     "carry = 0;",
1736     "overflow = 0;",
1737     "ADD_SUB_GE;",
1738   },
1739   { "","", "(if cc) pneg Sx,Dz",        "110010ccxx..zzzz",
1740     "int Sx = DSP_R (x);",
1741     "int Sx_grd = GET_DSP_GRD (x);",
1742     "",
1743     "res = 0 - Sx;",
1744     "carry = res != 0;",
1745     "res_grd = 0 - Sx_grd - carry;",
1746     "COMPUTE_OVERFLOW;",
1747     "ADD_SUB_GE;",
1748   },
1749   { "","", "(if cc) pcopy Sx,Dz",       "110110ccxx..zzzz",
1750     "res = DSP_R (x);",
1751     "res_grd = GET_DSP_GRD (x);",
1752     "carry = 0;",
1753     "COMPUTE_OVERFLOW;",
1754     "ADD_SUB_GE;",
1755   },
1756   { "","", "(if cc) pneg Sy,Dz",        "111010cc..yyzzzz",
1757     "int Sy = DSP_R (y);",
1758     "int Sy_grd = SIGN32 (Sy);",
1759     "",
1760     "res = 0 - Sy;",
1761     "carry = res != 0;",
1762     "res_grd = 0 - Sy_grd - carry;",
1763     "COMPUTE_OVERFLOW;",
1764     "ADD_SUB_GE;",
1765   },
1766   { "","", "(if cc) pcopy Sy,Dz",       "111110cc..yyzzzz",
1767     "res = DSP_R (y);",
1768     "res_grd = SIGN32 (res);",
1769     "carry = 0;",
1770     "COMPUTE_OVERFLOW;",
1771     "ADD_SUB_GE;",
1772   },
1773   { "","", "(if cc) psts MACH,Dz",      "110011cc....zzzz",
1774     "res = MACH;",
1775     "res_grd = SIGN32 (res);",
1776     "goto assign_z;",
1777   },
1778   { "","", "(if cc) psts MACL,Dz",      "110111cc....zzzz",
1779     "res = MACL;",
1780     "res_grd = SIGN32 (res);",
1781     "goto assign_z;",
1782   },
1783   { "","", "(if cc) plds Dz,MACH",      "111011cc....zzzz",
1784     "if (0xa05f >> z & 1)",
1785     "  RAISE_EXCEPTION (SIGILL);",
1786     "else",
1787     "  MACH = DSP_R (z);",
1788     "return;",
1789   },
1790   { "","", "(if cc) plds Dz,MACL",      "111111cc....zzzz",
1791     "if (0xa05f >> z & 1)",
1792     "  RAISE_EXCEPTION (SIGILL);",
1793     "else",
1794     "  MACL = DSP_R (z) = res;",
1795     "return;",
1796   },
1797   {0, 0}
1798 };
1799
1800 /* Tables of things to put into enums for sh-opc.h */
1801 static char *nibble_type_list[] =
1802 {
1803   "HEX_0",
1804   "HEX_1",
1805   "HEX_2",
1806   "HEX_3",
1807   "HEX_4",
1808   "HEX_5",
1809   "HEX_6",
1810   "HEX_7",
1811   "HEX_8",
1812   "HEX_9",
1813   "HEX_A",
1814   "HEX_B",
1815   "HEX_C",
1816   "HEX_D",
1817   "HEX_E",
1818   "HEX_F",
1819   "REG_N",
1820   "REG_M",
1821   "BRANCH_12",
1822   "BRANCH_8",
1823   "DISP_8",
1824   "DISP_4",
1825   "IMM_4",
1826   "IMM_4BY2",
1827   "IMM_4BY4",
1828   "PCRELIMM_8BY2",
1829   "PCRELIMM_8BY4",
1830   "IMM_8",
1831   "IMM_8BY2",
1832   "IMM_8BY4",
1833   0
1834 };
1835 static
1836 char *arg_type_list[] =
1837 {
1838   "A_END",
1839   "A_BDISP12",
1840   "A_BDISP8",
1841   "A_DEC_M",
1842   "A_DEC_N",
1843   "A_DISP_GBR",
1844   "A_DISP_PC",
1845   "A_DISP_REG_M",
1846   "A_DISP_REG_N",
1847   "A_GBR",
1848   "A_IMM",
1849   "A_INC_M",
1850   "A_INC_N",
1851   "A_IND_M",
1852   "A_IND_N",
1853   "A_IND_R0_REG_M",
1854   "A_IND_R0_REG_N",
1855   "A_MACH",
1856   "A_MACL",
1857   "A_PR",
1858   "A_R0",
1859   "A_R0_GBR",
1860   "A_REG_M",
1861   "A_REG_N",
1862   "A_SR",
1863   "A_VBR",
1864   "A_SSR",
1865   "A_SPC",
1866   0,
1867 };
1868
1869 static void
1870 make_enum_list (name, s)
1871      char *name;
1872      char **s;
1873 {
1874   int i = 1;
1875   printf ("typedef enum {\n");
1876   while (*s)
1877     {
1878       printf ("\t%s,\n", *s);
1879       s++;
1880       i++;
1881     }
1882   printf ("} %s;\n", name);
1883 }
1884
1885 static int
1886 qfunc (a, b)
1887      op *a;
1888      op *b;
1889 {
1890   char bufa[9];
1891   char bufb[9];
1892   int diff;
1893
1894   memcpy (bufa, a->code, 4);
1895   memcpy (bufa + 4, a->code + 12, 4);
1896   bufa[8] = 0;
1897
1898   memcpy (bufb, b->code, 4);
1899   memcpy (bufb + 4, b->code + 12, 4);
1900   bufb[8] = 0;
1901   diff = strcmp (bufa, bufb);
1902   /* Stabilize the sort, so that later entries can override more general
1903      preceding entries.  */
1904   return diff ? diff : a - b;
1905 }
1906
1907 static void
1908 sorttab ()
1909 {
1910   op *p = tab;
1911   int len = 0;
1912
1913   while (p->name)
1914     {
1915       p++;
1916       len++;
1917     }
1918   qsort (tab, len, sizeof (*p), qfunc);
1919 }
1920
1921 static void
1922 gengastab ()
1923 {
1924   op *p;
1925   sorttab ();
1926   for (p = tab; p->name; p++)
1927     {
1928       printf ("%s %-30s\n", p->code, p->name);
1929     }
1930
1931
1932 }
1933
1934 /* Convert a string of 4 binary digits into an int */
1935
1936 static
1937 int
1938 bton (s)
1939      char *s;
1940
1941 {
1942   int n = 0;
1943   int v = 8;
1944   while (v)
1945     {
1946       if (*s == '1')
1947         n |= v;
1948       v >>= 1;
1949       s++;
1950     }
1951   return n;
1952 }
1953
1954 static unsigned char table[1 << 16];
1955
1956 /* Take an opcode expand all varying fields in it out and fill all the
1957   right entries in 'table' with the opcode index*/
1958
1959 static void
1960 expand_opcode (shift, val, i, s)
1961      int shift;
1962      int val;
1963      int i;
1964      char *s;
1965 {
1966   int j;
1967
1968   if (*s == 0)
1969     {
1970       table[val] = i;
1971     }
1972   else
1973     {
1974       switch (s[0])
1975         {
1976
1977         case '0':
1978         case '1':
1979           {
1980             int m, mv;
1981
1982             val |= bton (s) << shift;
1983             if (s[2] == '0' || s[2] == '1')
1984               expand_opcode (shift - 4, val, i, s + 4);
1985             else if (s[2] == 'N')
1986               for (j = 0; j < 4; j++)
1987                 expand_opcode (shift - 4, val | (j << shift), i, s + 4);
1988             else if (s[2] == 'x')
1989               for (j = 0; j < 4; j += 2)
1990                 for (m = 0; m < 32; m++)
1991                   {
1992                     /* Ignore illegal nopy */
1993                     if ((m & 7) == 0 && m != 0)
1994                       continue;
1995                     mv = m & 3 | (m & 4) << 2 | (m & 8) << 3 | (m & 16) << 4;
1996                     expand_opcode (shift - 4, val | mv | (j << shift), i,
1997                                    s + 4);
1998                   }
1999             else if (s[2] == 'y')
2000               for (j = 0; j < 2; j++)
2001                 expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2002             break;
2003           }
2004         case 'n':
2005         case 'm':
2006           for (j = 0; j < 16; j++)
2007             {
2008               expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2009
2010             }
2011           break;
2012         case 'M':
2013           /* A1, A0,X0,X1,Y0,Y1,M0,A1G,M1,M1G */
2014           for (j = 5; j < 16; j++)
2015             if (j != 6)
2016               expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2017           break;
2018         case 'G':
2019           /* A1G, A0G: */
2020           for (j = 13; j <= 15; j +=2)
2021             expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2022           break;
2023         case 's':
2024           /* System registers mach, macl, pr: */
2025           for (j = 0; j < 3; j++)
2026             expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2027           /* System registers fpul, fpscr/dsr, a0, x0, x1, y0, y1: */
2028           for (j = 5; j < 12; j++)
2029             expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2030           break;
2031         case 'X':
2032         case 'a':
2033           val |= bton (s) << shift;
2034           for (j = 0; j < 16; j += 8)
2035             expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2036           break;
2037         case 'Y':
2038         case 'A':
2039           val |= bton (s) << shift;
2040           for (j = 0; j < 8; j += 4)
2041             expand_opcode (shift - 4, val | (j << shift), i, s + 4);
2042           break;
2043
2044         default:
2045           for (j = 0; j < (1 << (shift + 4)); j++)
2046             {
2047               table[val | j] = i;
2048             }
2049         }
2050     }
2051 }
2052
2053 /* Print the jump table used to index an opcode into a switch
2054    statement entry. */
2055
2056 static void
2057 dumptable (name, size, start)
2058      char *name;
2059      int size;
2060      int start;
2061 {
2062   int lump = 256;
2063   int online = 16;
2064
2065   int i = start;
2066
2067   printf ("unsigned char %s[%d]={\n", name, size);
2068   while (i < start + size)
2069     {
2070       int j = 0;
2071
2072       printf ("/* 0x%x */\n", i);
2073
2074       while (j < lump)
2075         {
2076           int k = 0;
2077           while (k < online)
2078             {
2079               printf ("%2d", table[i + j + k]);
2080               if (j + k < lump)
2081                 printf (",");
2082
2083               k++;
2084             }
2085           j += k;
2086           printf ("\n");
2087         }
2088       i += j;
2089     }
2090   printf ("};\n");
2091 }
2092
2093
2094 static void
2095 filltable (p)
2096      op *p;
2097 {
2098   static int index = 1;
2099
2100   sorttab ();
2101   for (; p->name; p++)
2102     {
2103       p->index = index++;
2104       expand_opcode (12, 0, p->index, p->code);
2105     }
2106 }
2107
2108 /* Table already contains all the switch case tags for 16-bit opcode double
2109    data transfer (ddt) insns, and the switch case tag for processing parallel
2110    processing insns (ppi) for code 0xf800 (ppi nopx nopy).  Copy the
2111    latter tag to represent all combinations of ppi with ddt.  */
2112 static void
2113 ppi_moves ()
2114 {
2115   int i;
2116
2117   for (i = 0xf000; i < 0xf400; i++)
2118     if (table[i])
2119       table[i + 0x800] = table[0xf800];
2120 }
2121
2122 static void
2123 gensim_caselist (p)
2124      op *p;
2125 {
2126   for (; p->name; p++)
2127     {
2128       int j;
2129       int sextbit = -1;
2130       int needm = 0;
2131       int needn = 0;
2132
2133       char *s = p->code;
2134
2135       printf ("  /* %s %s */\n", p->name, p->code);
2136       printf ("  case %d:      \n", p->index);
2137
2138       printf ("    {\n");
2139       while (*s)
2140         {
2141           switch (*s)
2142             {
2143             default:
2144               fprintf (stderr, "gencode/gensim_caselist: illegal char '%c'\n",
2145                        *s);
2146               exit (1);
2147               break;
2148             case '0':
2149             case '1':
2150               s += 2;
2151               break;
2152             case '.':
2153               s += 4;
2154               break;
2155             case 'n':
2156               printf ("      int n = (iword >>8) & 0xf;\n");
2157               needn = 1;
2158               s += 4;
2159               break;
2160             case 'N':
2161               printf ("      int n = (((iword >> 8) - 2) & 0x3) + 2;\n");
2162               s += 2;
2163               break;
2164             case 'x':
2165               printf ("      int n = ((iword >> 9) & 1) + 4;\n");
2166               needn = 1;
2167               s += 2;
2168               break;
2169             case 'y':
2170               printf ("      int n = ((iword >> 8) & 1) + 6;\n");
2171               needn = 1;
2172               s += 2;
2173               break;
2174             case 'm':
2175               needm = 1;
2176             case 's':
2177             case 'M':
2178             case 'G':
2179               printf ("      int m = (iword >>4) & 0xf;\n");
2180               s += 4;
2181               break;
2182             case 'X':
2183               printf ("      int m = ((iword >> 7) & 1) + 8;\n");
2184               s += 2;
2185               break;
2186             case 'a':
2187               printf ("      int m = 7 - ((iword >> 6) & 2);\n");
2188               s += 2;
2189               break;
2190             case 'Y':
2191               printf ("      int m = ((iword >> 6) & 1) + 10;\n");
2192               s += 2;
2193               break;
2194             case 'A':
2195               printf ("      int m = 7 - ((iword >> 5) & 2);\n");
2196               s += 2;
2197               break;
2198
2199             case 'i':
2200               printf ("      int i = (iword & 0x");
2201
2202               switch (s[1])
2203                 {
2204                 case '4':
2205                   printf ("f");
2206                   break;
2207                 case '8':
2208                   printf ("ff");
2209                   break;
2210                 case '1':
2211                   sextbit = 12;
2212
2213                   printf ("fff");
2214                   break;
2215                 }
2216               printf (")");
2217
2218               switch (s[3])
2219                 {
2220                 case '1':
2221                   break;
2222                 case '2':
2223                   printf ("<<1");
2224                   break;
2225                 case '4':
2226                   printf ("<<2");
2227                   break;
2228                 }
2229               printf (";\n");
2230               s += 4;
2231             }
2232         }
2233       if (sextbit > 0)
2234         {
2235           printf ("      i = (i ^ (1<<%d))-(1<<%d);\n",
2236                   sextbit - 1, sextbit - 1);
2237         }
2238
2239       if (needm && needn)
2240         printf ("      TB(m,n);\n");
2241       else if (needm)
2242         printf ("      TL(m);\n");
2243       else if (needn)
2244         printf ("      TL(n);\n");
2245
2246       {
2247         /* Do the refs */
2248         char *r;
2249         for (r = p->refs; *r; r++)
2250           {
2251             if (*r == '0') printf("      CREF(0);\n");
2252             if (*r == '8') printf("      CREF(8);\n");
2253             if (*r == '9') printf("      CREF(9);\n");
2254             if (*r == 'n') printf("      CREF(n);\n");
2255             if (*r == 'm') printf("      CREF(m);\n");
2256           }
2257       }
2258
2259       printf ("      {\n");
2260       for (j = 0; j < MAX_NR_STUFF; j++)
2261         {
2262           if (p->stuff[j])
2263             {
2264               printf ("        %s\n", p->stuff[j]);
2265             }
2266         }
2267       printf ("      }\n");
2268
2269       {
2270         /* Do the defs */
2271         char *r;
2272         for (r = p->defs; *r; r++)
2273           {
2274             if (*r == '0') printf("      CDEF(0);\n");
2275             if (*r == 'n') printf("      CDEF(n);\n");
2276             if (*r == 'm') printf("      CDEF(m);\n");
2277           }
2278       }
2279
2280       printf ("      break;\n");
2281       printf ("    }\n");
2282     }
2283 }
2284
2285 static void
2286 gensim ()
2287 {
2288   printf ("{\n");
2289   printf ("  switch (jump_table[iword]) {\n");
2290
2291   gensim_caselist (tab);
2292   gensim_caselist (movsxy_tab);
2293
2294   printf ("  default:\n");
2295   printf ("    {\n");
2296   printf ("      RAISE_EXCEPTION (SIGILL);\n");
2297   printf ("    }\n");
2298   printf ("  }\n");
2299   printf ("}\n");
2300 }
2301
2302 static void
2303 gendefines ()
2304 {
2305   op *p;
2306   filltable (tab);
2307   for (p = tab; p->name; p++)
2308     {
2309       char *s = p->name;
2310       printf ("#define OPC_");
2311       while (*s) {
2312         if (isupper(*s))
2313           *s = tolower(*s);
2314         if (isalpha(*s)) printf("%c", *s);
2315         if (*s == ' ') printf("_");
2316         if (*s == '@') printf("ind_");
2317         if (*s == ',') printf("_");
2318         s++;
2319       }
2320       printf(" %d\n",p->index);
2321     }
2322 }
2323
2324 static int ppi_index;
2325
2326 /* Take a ppi code, expand all varying fields in it and fill all the
2327    right entries in 'table' with the opcode index.  */
2328
2329 static void
2330 expand_ppi_code (val, i, s)
2331      int val;
2332      int i;
2333      char *s;
2334 {
2335   int j;
2336
2337   for (;;)
2338     {
2339       switch (s[0])
2340         {
2341         default:
2342           fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n",
2343                    s[0]);
2344           exit (2);
2345           break;
2346         /* The last eight bits are disregarded for the switch table.  */
2347         case 'm':
2348         case 'x':
2349         case '.':
2350           table[val] = i;
2351           return;
2352         case '0':
2353           val += val;
2354           s++;
2355           break;
2356         case '1':
2357           val += val + 1;
2358           s++;
2359           break;
2360         case 'i':
2361         case 'e': case 'f':
2362           val += val;
2363           s++;
2364           expand_ppi_code (val, i, s);
2365           val++;
2366           break;
2367         case 'c':
2368           val <<= 2;
2369           s += 2;
2370           val++;
2371           expand_ppi_code (val, ppi_index++, s);
2372           val++;
2373           expand_ppi_code (val, i, s);
2374           val++;
2375           break;
2376         }
2377     }
2378 }
2379
2380 static void
2381 ppi_filltable ()
2382 {
2383   op *p;
2384   ppi_index = 1;
2385
2386   for (p = ppi_tab; p->name; p++)
2387     {
2388       p->index = ppi_index++;
2389       expand_ppi_code (0, p->index, p->code);
2390     }
2391 }
2392
2393 static void
2394 ppi_gensim ()
2395 {
2396   op *p = ppi_tab;
2397
2398   printf ("#define DSR_MASK_G 0x80\n");
2399   printf ("#define DSR_MASK_Z 0x40\n");
2400   printf ("#define DSR_MASK_N 0x20\n");
2401   printf ("#define DSR_MASK_V 0x10\n");
2402   printf ("\n");
2403   printf ("#define COMPUTE_OVERFLOW do {\\\n");
2404   printf ("  overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0; \\\n");
2405   printf ("  if (overflow && S) \\\n");
2406   printf ("    { \\\n");
2407   printf ("      if (res_grd & 0x80) \\\n");
2408   printf ("        { \\\n");
2409   printf ("          res = 0x80000000; \\\n");
2410   printf ("          res_grd |=  0xff; \\\n");
2411   printf ("        } \\\n");
2412   printf ("      else \\\n");
2413   printf ("        { \\\n");
2414   printf ("          res = 0x7fffffff; \\\n");
2415   printf ("          res_grd &= ~0xff; \\\n");
2416   printf ("        } \\\n");
2417   printf ("      overflow = 0; \\\n");
2418   printf ("    } \\\n");
2419   printf ("} while (0)\n");
2420   printf ("\n");
2421   printf ("#define ADD_SUB_GE \\\n");
2422   printf ("  (greater_equal = ~(overflow << 3 & res_grd) & DSR_MASK_G)\n");
2423   printf ("\n");
2424   printf ("static void\n");
2425   printf ("ppi_insn (iword)\n");
2426   printf ("     int iword;\n");
2427   printf ("{\n");
2428   printf ("  static char e_tab[] = { 8,  9, 10,  5};\n");
2429   printf ("  static char f_tab[] = {10, 11,  8,  5};\n");
2430   printf ("  static char x_tab[] = { 8,  9,  7,  5};\n");
2431   printf ("  static char y_tab[] = {10, 11, 12, 14};\n");
2432   printf ("  static char g_tab[] = {12, 14,  7,  5};\n");
2433   printf ("  static char u_tab[] = { 8, 10,  7,  5};\n");
2434   printf ("\n");
2435   printf ("  int z;\n");
2436   printf ("  int res, res_grd;\n");
2437   printf ("  int carry, overflow, greater_equal;\n");
2438   printf ("\n");
2439   printf ("  switch (ppi_table[iword >> 8]) {\n");
2440
2441   for (; p->name; p++)
2442     {
2443       int shift, j;
2444       int cond = 0;
2445       int havedecl = 0;
2446
2447       char *s = p->code;
2448
2449       printf ("  /* %s %s */\n", p->name, p->code);
2450       printf ("  case %d:      \n", p->index);
2451
2452       printf ("    {\n");
2453       for (shift = 16; *s; )
2454         {
2455           switch (*s)
2456             {
2457             case 'i':
2458               printf ("      int i = (iword >> 4) & 0x7f;\n");
2459               s += 6;
2460               break;
2461             case 'e':
2462             case 'f':
2463             case 'x':
2464             case 'y':
2465             case 'g':
2466             case 'u':
2467               shift -= 2;
2468               printf ("      int %c = %c_tab[(iword >> %d) & 3];\n",
2469                       *s, *s, shift);
2470               havedecl = 1;
2471               s += 2;
2472               break;
2473             case 'c':
2474               printf ("      if ((((iword >> 8) ^ DSR) & 1) == 0)\n");
2475               printf ("\treturn;\n");
2476               printf ("    }\n");
2477               printf ("  case %d:      \n", p->index + 1);
2478               printf ("    {\n");
2479               cond = 1;
2480             case '0':
2481             case '1':
2482             case '.':
2483               shift -= 2;
2484               s += 2;
2485               break;
2486             case 'z':
2487               if (havedecl)
2488                 printf ("\n");
2489               printf ("      z = iword & 0xf;\n");
2490               havedecl = 2;
2491               s += 4;
2492               break;
2493             }
2494         }
2495       if (havedecl == 1)
2496         printf ("\n");
2497       else if (havedecl == 2)
2498         printf ("      {\n");
2499       for (j = 0; j < MAX_NR_STUFF; j++)
2500         {
2501           if (p->stuff[j])
2502             {
2503               printf ("      %s%s\n",
2504                       (havedecl == 2 ? "  " : ""),
2505                       p->stuff[j]);
2506             }
2507         }
2508       if (havedecl == 2)
2509         printf ("      }\n");
2510       if (cond)
2511         {
2512           printf ("      if (iword & 0x200)\n");
2513           printf ("        goto assign_z;\n");
2514         }
2515       printf ("      break;\n");
2516       printf ("    }\n");
2517     }
2518
2519   printf ("  default:\n");
2520   printf ("    {\n");
2521   printf ("      RAISE_EXCEPTION (SIGILL);\n");
2522   printf ("      return;\n");
2523   printf ("    }\n");
2524   printf ("  }\n");
2525   printf ("  DSR &= ~0xf1;\n");
2526   printf ("  if (res || res_grd)\n");
2527   printf ("    DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n");
2528   printf ("  else\n");
2529   printf ("    DSR |= DSR_MASK_Z | overflow;\n");
2530   printf (" assign_dc:\n");
2531   printf ("  switch (DSR >> 1 & 7)\n");
2532   printf ("    {\n");
2533   printf ("    case 0: /* Carry Mode */\n");
2534   printf ("      DSR |= carry;\n");
2535   printf ("    case 1: /* Negative Value Mode */\n");
2536   printf ("      DSR |= res_grd >> 7 & 1;\n");
2537   printf ("    case 2: /* Zero Value Mode */\n");
2538   printf ("      DSR |= DSR >> 6 & 1;\n");
2539   printf ("    case 3: /* Overflow mode\n");
2540   printf ("      DSR |= overflow >> 4;\n");
2541   printf ("    case 4: /* Signed Greater Than Mode */\n");
2542   printf ("      DSR |= DSR >> 7 & 1;\n");
2543   printf ("    case 4: /* Signed Greater Than Or Equal Mode */\n");
2544   printf ("      DSR |= greater_equal >> 7;\n");
2545   printf ("    }\n");
2546   printf (" assign_z:\n");
2547   printf ("  if (0xa05f >> z & 1)\n");
2548   printf ("    {\n");
2549   printf ("      RAISE_EXCEPTION (SIGILL);\n");
2550   printf ("      return;\n");
2551   printf ("    }\n");
2552   printf ("  DSP_R (z) = res;\n");
2553   printf ("  DSP_GRD (z) = res_grd;\n");
2554   printf ("}\n");
2555 }
2556
2557 int
2558 main (ac, av)
2559      int ac;
2560      char **av;
2561 {
2562   /* verify the table before anything else */
2563   {
2564     op *p;
2565     for (p = tab; p->name; p++)
2566       {
2567         /* check that the code field contains 16 bits */
2568         if (strlen (p->code) != 16)
2569           {
2570             fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n",
2571                      p->code, strlen (p->code), p->name);
2572             abort ();
2573           }
2574       }
2575   }
2576
2577   /* now generate the requested data */
2578   if (ac > 1)
2579     {
2580       if (strcmp (av[1], "-t") == 0)
2581         {
2582           gengastab ();
2583         }
2584       else if (strcmp (av[1], "-d") == 0)
2585         {
2586           gendefines ();
2587         }
2588       else if (strcmp (av[1], "-s") == 0)
2589         {
2590           filltable (tab);
2591           dumptable ("sh_jump_table", 1 << 16, 0);
2592
2593           memset (table, 0, sizeof table);
2594           filltable (movsxy_tab);
2595           ppi_moves ();
2596           dumptable ("sh_dsp_table", 1 << 12, 0xf000);
2597
2598           memset (table, 0, sizeof table);
2599           ppi_filltable ();
2600           dumptable ("ppi_table", 1 << 8, 0);
2601         }
2602       else if (strcmp (av[1], "-x") == 0)
2603         {
2604           filltable (tab);
2605           filltable (movsxy_tab);
2606           gensim ();
2607         }
2608       else if (strcmp (av[1], "-p") == 0)
2609         {
2610           ppi_filltable ();
2611           ppi_gensim ();
2612         }
2613     }
2614   else
2615     fprintf (stderr, "Opcode table generation no longer supported.\n");
2616   return 0;
2617 }