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2004-01-27 Michael Snyder <msnyder@redhat.com>
[deliverable/binutils-gdb.git] / sim / sh / interp.c
1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
2
3 Written by Steve Chamberlain of Cygnus Support.
4 sac@cygnus.com
5
6 This file is part of SH sim
7
8
9 THIS SOFTWARE IS NOT COPYRIGHTED
10
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
14
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18
19 */
20
21 #include "config.h"
22
23 #include <signal.h>
24 #ifdef HAVE_UNISTD_H
25 #include <unistd.h>
26 #endif
27
28 #include "sysdep.h"
29 #include "bfd.h"
30 #include "gdb/callback.h"
31 #include "gdb/remote-sim.h"
32 #include "gdb/sim-sh.h"
33
34 /* This file is local - if newlib changes, then so should this. */
35 #include "syscall.h"
36
37 #include <math.h>
38
39 #ifdef _WIN32
40 #include <float.h> /* Needed for _isnan() */
41 #define isnan _isnan
42 #endif
43
44 #ifndef SIGBUS
45 #define SIGBUS SIGSEGV
46 #endif
47
48 #ifndef SIGQUIT
49 #define SIGQUIT SIGTERM
50 #endif
51
52 #ifndef SIGTRAP
53 #define SIGTRAP 5
54 #endif
55
56 extern unsigned char sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
57
58 int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size);
59
60 #define O_RECOMPILE 85
61 #define DEFINE_TABLE
62 #define DISASSEMBLER_TABLE
63
64 /* Define the rate at which the simulator should poll the host
65 for a quit. */
66 #define POLL_QUIT_INTERVAL 0x60000
67
68 typedef union
69 {
70
71 struct
72 {
73 int regs[16];
74 int pc;
75
76 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
77 which are located in fregs, i.e. strictly speaking, these are
78 out-of-bounds accesses of sregs.i . This wart of the code could be
79 fixed by making fregs part of sregs, and including pc too - to avoid
80 alignment repercussions - but this would cause very onerous union /
81 structure nesting, which would only be managable with anonymous
82 unions and structs. */
83 union
84 {
85 struct
86 {
87 int mach;
88 int macl;
89 int pr;
90 int dummy3, dummy4;
91 int fpul; /* A1 for sh-dsp - but only for movs etc. */
92 int fpscr; /* dsr for sh-dsp */
93 } named;
94 int i[7];
95 } sregs;
96
97 /* sh3e / sh-dsp */
98 union fregs_u
99 {
100 float f[16];
101 double d[8];
102 int i[16];
103 }
104 fregs[2];
105
106 /* Control registers; on the SH4, ldc / stc is privileged, except when
107 accessing gbr. */
108 union
109 {
110 struct
111 {
112 int sr;
113 int gbr;
114 int vbr;
115 int ssr;
116 int spc;
117 int mod;
118 /* sh-dsp */
119 int rs;
120 int re;
121 /* sh3 */
122 int bank[8];
123 int dbr; /* debug base register */
124 int sgr; /* saved gr15 */
125 int ldst; /* load/store flag (boolean) */
126 } named;
127 int i[16];
128 } cregs;
129
130 unsigned char *insn_end;
131
132 int ticks;
133 int stalls;
134 int memstalls;
135 int cycles;
136 int insts;
137
138 int prevlock;
139 int thislock;
140 int exception;
141
142 int end_of_registers;
143
144 int msize;
145 #define PROFILE_FREQ 1
146 #define PROFILE_SHIFT 2
147 int profile;
148 unsigned short *profile_hist;
149 unsigned char *memory;
150 int xyram_select, xram_start, yram_start;
151 unsigned char *xmem;
152 unsigned char *ymem;
153 unsigned char *xmem_offset;
154 unsigned char *ymem_offset;
155 }
156 asregs;
157 int asints[40];
158 } saved_state_type;
159
160 saved_state_type saved_state;
161
162 struct loop_bounds { unsigned char *start, *end; };
163
164 /* These variables are at file scope so that functions other than
165 sim_resume can use the fetch/store macros */
166
167 static int target_little_endian;
168 static int global_endianw, endianb;
169 static int target_dsp;
170 static int host_little_endian;
171 static char **prog_argv;
172
173 static int maskw = 0;
174 static int maskl = 0;
175
176 static SIM_OPEN_KIND sim_kind;
177 static char *myname;
178
179
180 /* Short hand definitions of the registers */
181
182 #define SBIT(x) ((x)&sbit)
183 #define R0 saved_state.asregs.regs[0]
184 #define Rn saved_state.asregs.regs[n]
185 #define Rm saved_state.asregs.regs[m]
186 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
187 #define UR (unsigned int) R
188 #define UR (unsigned int) R
189 #define SR0 saved_state.asregs.regs[0]
190 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
191 #define GBR saved_state.asregs.cregs.named.gbr
192 #define VBR saved_state.asregs.cregs.named.vbr
193 #define DBR saved_state.asregs.cregs.named.dbr
194 #define SSR saved_state.asregs.cregs.named.ssr
195 #define SPC saved_state.asregs.cregs.named.spc
196 #define SGR saved_state.asregs.cregs.named.sgr
197 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
198 #define MACH saved_state.asregs.sregs.named.mach
199 #define MACL saved_state.asregs.sregs.named.macl
200 #define PR saved_state.asregs.sregs.named.pr
201 #define FPUL saved_state.asregs.sregs.named.fpul
202
203 #define PC insn_ptr
204
205
206
207 /* Alternate bank of registers r0-r7 */
208
209 /* Note: code controling SR handles flips between BANK0 and BANK1 */
210 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
211 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
212
213
214 /* Manipulate SR */
215
216 #define SR_MASK_DMY (1 << 11)
217 #define SR_MASK_DMX (1 << 10)
218 #define SR_MASK_M (1 << 9)
219 #define SR_MASK_Q (1 << 8)
220 #define SR_MASK_I (0xf << 4)
221 #define SR_MASK_S (1 << 1)
222 #define SR_MASK_T (1 << 0)
223
224 #define SR_MASK_BL (1 << 28)
225 #define SR_MASK_RB (1 << 29)
226 #define SR_MASK_MD (1 << 30)
227 #define SR_MASK_RC 0x0fff0000
228 #define SR_RC_INCREMENT -0x00010000
229
230 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
231 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
232 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
233 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
234 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
235
236 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
237 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
238 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
239 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
240 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
241 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
242
243 /* Note: don't use this for privileged bits */
244 #define SET_SR_BIT(EXP, BIT) \
245 do { \
246 if ((EXP) & 1) \
247 saved_state.asregs.cregs.named.sr |= (BIT); \
248 else \
249 saved_state.asregs.cregs.named.sr &= ~(BIT); \
250 } while (0)
251
252 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
253 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
254 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
255 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
256 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
257
258 /* stc currently relies on being able to read SR without modifications. */
259 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
260
261 #define SET_SR(x) set_sr (x)
262
263 #define SET_RC(x) \
264 (saved_state.asregs.cregs.named.sr \
265 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
266
267 /* Manipulate FPSCR */
268
269 #define FPSCR_MASK_FR (1 << 21)
270 #define FPSCR_MASK_SZ (1 << 20)
271 #define FPSCR_MASK_PR (1 << 19)
272
273 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
274 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
275 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
276
277 /* Count the number of arguments in an argv. */
278 static int
279 count_argc (char **argv)
280 {
281 int i;
282
283 if (! argv)
284 return -1;
285
286 for (i = 0; argv[i] != NULL; ++i)
287 continue;
288 return i;
289 }
290
291 static void
292 set_fpscr1 (x)
293 int x;
294 {
295 int old = saved_state.asregs.sregs.named.fpscr;
296 saved_state.asregs.sregs.named.fpscr = (x);
297 /* swap the floating point register banks */
298 if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
299 /* Ignore bit change if simulating sh-dsp. */
300 && ! target_dsp)
301 {
302 union fregs_u tmpf = saved_state.asregs.fregs[0];
303 saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
304 saved_state.asregs.fregs[1] = tmpf;
305 }
306 }
307
308 /* sts relies on being able to read fpscr directly. */
309 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
310 #define SET_FPSCR(x) \
311 do { \
312 set_fpscr1 (x); \
313 } while (0)
314
315 #define DSR (saved_state.asregs.sregs.named.fpscr)
316
317 int
318 fail ()
319 {
320 abort ();
321 }
322
323 #define RAISE_EXCEPTION(x) \
324 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
325
326 /* This function exists mainly for the purpose of setting a breakpoint to
327 catch simulated bus errors when running the simulator under GDB. */
328
329 void
330 raise_exception (x)
331 int x;
332 {
333 RAISE_EXCEPTION (x);
334 }
335
336 void
337 raise_buserror ()
338 {
339 raise_exception (SIGBUS);
340 }
341
342 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
343 forbidden_addr_bits, data, retval) \
344 do { \
345 if (addr & forbidden_addr_bits) \
346 { \
347 raise_buserror (); \
348 return retval; \
349 } \
350 else if ((addr & saved_state.asregs.xyram_select) \
351 == saved_state.asregs.xram_start) \
352 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
353 else if ((addr & saved_state.asregs.xyram_select) \
354 == saved_state.asregs.yram_start) \
355 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
356 else if ((unsigned) addr >> 24 == 0xf0 \
357 && bits_written == 32 && (data & 1) == 0) \
358 /* This invalidates (if not associative) or might invalidate \
359 (if associative) an instruction cache line. This is used for \
360 trampolines. Since we don't simulate the cache, this is a no-op \
361 as far as the simulator is concerned. */ \
362 return retval; \
363 else \
364 { \
365 if (bits_written == 8 && addr > 0x5000000) \
366 IOMEM (addr, 1, data); \
367 /* We can't do anything useful with the other stuff, so fail. */ \
368 raise_buserror (); \
369 return retval; \
370 } \
371 } while (0)
372
373 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
374 being implemented by ../common/sim_resume.c and the below should
375 make a call to sim_engine_halt */
376
377 #define BUSERROR(addr, mask) ((addr) & (mask))
378
379 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
380 do \
381 { \
382 if (addr & mask) \
383 { \
384 addr_func (addr, data); \
385 return; \
386 } \
387 } \
388 while (0)
389
390 #define READ_BUSERROR(addr, mask, addr_func) \
391 do \
392 { \
393 if (addr & mask) \
394 return addr_func (addr); \
395 } \
396 while (0)
397
398 /* Define this to enable register lifetime checking.
399 The compiler generates "add #0,rn" insns to mark registers as invalid,
400 the simulator uses this info to call fail if it finds a ref to an invalid
401 register before a def
402
403 #define PARANOID
404 */
405
406 #ifdef PARANOID
407 int valid[16];
408 #define CREF(x) if (!valid[x]) fail ();
409 #define CDEF(x) valid[x] = 1;
410 #define UNDEF(x) valid[x] = 0;
411 #else
412 #define CREF(x)
413 #define CDEF(x)
414 #define UNDEF(x)
415 #endif
416
417 static void parse_and_set_memory_size PARAMS ((char *str));
418 static int IOMEM PARAMS ((int addr, int write, int value));
419 static struct loop_bounds get_loop_bounds PARAMS ((int, int, unsigned char *,
420 unsigned char *, int, int));
421 static void process_wlat_addr PARAMS ((int, int));
422 static void process_wwat_addr PARAMS ((int, int));
423 static void process_wbat_addr PARAMS ((int, int));
424 static int process_rlat_addr PARAMS ((int));
425 static int process_rwat_addr PARAMS ((int));
426 static int process_rbat_addr PARAMS ((int));
427 static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
428 static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
429 static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
430 static int INLINE rlat_fast PARAMS ((unsigned char *, int, int));
431 static int INLINE rwat_fast PARAMS ((unsigned char *, int, int, int));
432 static int INLINE rbat_fast PARAMS ((unsigned char *, int, int));
433
434 static host_callback *callback;
435
436
437
438 /* Floating point registers */
439
440 #define DR(n) (get_dr (n))
441 static double
442 get_dr (n)
443 int n;
444 {
445 n = (n & ~1);
446 if (host_little_endian)
447 {
448 union
449 {
450 int i[2];
451 double d;
452 } dr;
453 dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
454 dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
455 return dr.d;
456 }
457 else
458 return (saved_state.asregs.fregs[0].d[n >> 1]);
459 }
460
461 #define SET_DR(n, EXP) set_dr ((n), (EXP))
462 static void
463 set_dr (n, exp)
464 int n;
465 double exp;
466 {
467 n = (n & ~1);
468 if (host_little_endian)
469 {
470 union
471 {
472 int i[2];
473 double d;
474 } dr;
475 dr.d = exp;
476 saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
477 saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
478 }
479 else
480 saved_state.asregs.fregs[0].d[n >> 1] = exp;
481 }
482
483 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
484 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
485
486 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
487 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
488
489 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
490 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
491 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
492
493 #define RS saved_state.asregs.cregs.named.rs
494 #define RE saved_state.asregs.cregs.named.re
495 #define MOD (saved_state.asregs.cregs.named.mod)
496 #define SET_MOD(i) \
497 (MOD = (i), \
498 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
499 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
500
501 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
502 #define DSP_GRD(n) DSP_R ((n) + 8)
503 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
504 #define A1 DSP_R (5)
505 #define A0 DSP_R (7)
506 #define X0 DSP_R (8)
507 #define X1 DSP_R (9)
508 #define Y0 DSP_R (10)
509 #define Y1 DSP_R (11)
510 #define M0 DSP_R (12)
511 #define A1G DSP_R (13)
512 #define M1 DSP_R (14)
513 #define A0G DSP_R (15)
514 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
515 #define MOD_ME DSP_GRD (17)
516 #define MOD_DELTA DSP_GRD (18)
517
518 #define FP_OP(n, OP, m) \
519 { \
520 if (FPSCR_PR) \
521 { \
522 if (((n) & 1) || ((m) & 1)) \
523 RAISE_EXCEPTION (SIGILL); \
524 else \
525 SET_DR (n, (DR (n) OP DR (m))); \
526 } \
527 else \
528 SET_FR (n, (FR (n) OP FR (m))); \
529 } while (0)
530
531 #define FP_UNARY(n, OP) \
532 { \
533 if (FPSCR_PR) \
534 { \
535 if ((n) & 1) \
536 RAISE_EXCEPTION (SIGILL); \
537 else \
538 SET_DR (n, (OP (DR (n)))); \
539 } \
540 else \
541 SET_FR (n, (OP (FR (n)))); \
542 } while (0)
543
544 #define FP_CMP(n, OP, m) \
545 { \
546 if (FPSCR_PR) \
547 { \
548 if (((n) & 1) || ((m) & 1)) \
549 RAISE_EXCEPTION (SIGILL); \
550 else \
551 SET_SR_T (DR (n) OP DR (m)); \
552 } \
553 else \
554 SET_SR_T (FR (n) OP FR (m)); \
555 } while (0)
556
557 static void
558 set_sr (new_sr)
559 int new_sr;
560 {
561 /* do we need to swap banks */
562 int old_gpr = SR_MD && SR_RB;
563 int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
564 if (old_gpr != new_gpr)
565 {
566 int i, tmp;
567 for (i = 0; i < 8; i++)
568 {
569 tmp = saved_state.asregs.cregs.named.bank[i];
570 saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
571 saved_state.asregs.regs[i] = tmp;
572 }
573 }
574 saved_state.asregs.cregs.named.sr = new_sr;
575 SET_MOD (MOD);
576 }
577
578 static void INLINE
579 wlat_fast (memory, x, value, maskl)
580 unsigned char *memory;
581 {
582 int v = value;
583 unsigned int *p = (unsigned int *) (memory + x);
584 WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
585 *p = v;
586 }
587
588 static void INLINE
589 wwat_fast (memory, x, value, maskw, endianw)
590 unsigned char *memory;
591 {
592 int v = value;
593 unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
594 WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
595 *p = v;
596 }
597
598 static void INLINE
599 wbat_fast (memory, x, value, maskb)
600 unsigned char *memory;
601 {
602 unsigned char *p = memory + (x ^ endianb);
603 WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
604
605 p[0] = value;
606 }
607
608 /* Read functions */
609
610 static int INLINE
611 rlat_fast (memory, x, maskl)
612 unsigned char *memory;
613 {
614 unsigned int *p = (unsigned int *) (memory + x);
615 READ_BUSERROR (x, maskl, process_rlat_addr);
616
617 return *p;
618 }
619
620 static int INLINE
621 rwat_fast (memory, x, maskw, endianw)
622 unsigned char *memory;
623 int x, maskw, endianw;
624 {
625 unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
626 READ_BUSERROR (x, maskw, process_rwat_addr);
627
628 return *p;
629 }
630
631 static int INLINE
632 riat_fast (insn_ptr, endianw)
633 unsigned char *insn_ptr;
634 {
635 unsigned short *p = (unsigned short *) ((size_t) insn_ptr ^ endianw);
636
637 return *p;
638 }
639
640 static int INLINE
641 rbat_fast (memory, x, maskb)
642 unsigned char *memory;
643 {
644 unsigned char *p = memory + (x ^ endianb);
645 READ_BUSERROR (x, maskb, process_rbat_addr);
646
647 return *p;
648 }
649
650 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
651 #define RLAT(x) (rlat_fast (memory, x, maskl))
652 #define RBAT(x) (rbat_fast (memory, x, maskb))
653 #define RIAT(p) (riat_fast ((p), endianw))
654 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
655 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
656 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
657
658 #define RUWAT(x) (RWAT (x) & 0xffff)
659 #define RSWAT(x) ((short) (RWAT (x)))
660 #define RSLAT(x) ((long) (RLAT (x)))
661 #define RSBAT(x) (SEXT (RBAT (x)))
662
663 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
664 static int
665 do_rdat (memory, x, n, maskl)
666 char *memory;
667 int x;
668 int n;
669 int maskl;
670 {
671 int f0;
672 int f1;
673 int i = (n & 1);
674 int j = (n & ~1);
675 f0 = rlat_fast (memory, x + 0, maskl);
676 f1 = rlat_fast (memory, x + 4, maskl);
677 saved_state.asregs.fregs[i].i[(j + 0)] = f0;
678 saved_state.asregs.fregs[i].i[(j + 1)] = f1;
679 return 0;
680 }
681
682 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
683 static int
684 do_wdat (memory, x, n, maskl)
685 char *memory;
686 int x;
687 int n;
688 int maskl;
689 {
690 int f0;
691 int f1;
692 int i = (n & 1);
693 int j = (n & ~1);
694 f0 = saved_state.asregs.fregs[i].i[(j + 0)];
695 f1 = saved_state.asregs.fregs[i].i[(j + 1)];
696 wlat_fast (memory, (x + 0), f0, maskl);
697 wlat_fast (memory, (x + 4), f1, maskl);
698 return 0;
699 }
700
701 static void
702 process_wlat_addr (addr, value)
703 int addr;
704 int value;
705 {
706 unsigned int *ptr;
707
708 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
709 *ptr = value;
710 }
711
712 static void
713 process_wwat_addr (addr, value)
714 int addr;
715 int value;
716 {
717 unsigned short *ptr;
718
719 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
720 *ptr = value;
721 }
722
723 static void
724 process_wbat_addr (addr, value)
725 int addr;
726 int value;
727 {
728 unsigned char *ptr;
729
730 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
731 *ptr = value;
732 }
733
734 static int
735 process_rlat_addr (addr)
736 int addr;
737 {
738 unsigned char *ptr;
739
740 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
741 return *ptr;
742 }
743
744 static int
745 process_rwat_addr (addr)
746 int addr;
747 {
748 unsigned char *ptr;
749
750 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
751 return *ptr;
752 }
753
754 static int
755 process_rbat_addr (addr)
756 int addr;
757 {
758 unsigned char *ptr;
759
760 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
761 return *ptr;
762 }
763
764 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
765 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
766 #define SEXTW(y) ((int) ((short) y))
767 #if 0
768 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
769 #else
770 #define SEXT32(x) ((int) (x))
771 #endif
772 #define SIGN32(x) (SEXT32 (x) >> 31)
773
774 /* convert pointer from target to host value. */
775 #define PT2H(x) ((x) + memory)
776 /* convert pointer from host to target value. */
777 #define PH2T(x) ((x) - memory)
778
779 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
780
781 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
782
783 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); goto top;
784
785 #define CHECK_INSN_PTR(p) \
786 do { \
787 if (saved_state.asregs.exception || PH2T (p) & maskw) \
788 saved_state.asregs.insn_end = 0; \
789 else if (p < loop.end) \
790 saved_state.asregs.insn_end = loop.end; \
791 else \
792 saved_state.asregs.insn_end = mem_end; \
793 } while (0)
794
795 #ifdef ACE_FAST
796
797 #define MA(n)
798 #define L(x)
799 #define TL(x)
800 #define TB(x)
801
802 #else
803
804 #define MA(n) \
805 do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
806
807 #define L(x) thislock = x;
808 #define TL(x) if ((x) == prevlock) stalls++;
809 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
810
811 #endif
812
813 #if defined(__GO32__) || defined(_WIN32)
814 int sim_memory_size = 19;
815 #else
816 int sim_memory_size = 24;
817 #endif
818
819 static int sim_profile_size = 17;
820 static int nsamples;
821
822 #undef TB
823 #define TB(x,y)
824
825 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
826 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
827 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
828 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
829 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
830 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
831
832 #define SCI_RDRF 0x40 /* Recieve data register full */
833 #define SCI_TDRE 0x80 /* Transmit data register empty */
834
835 static int
836 IOMEM (addr, write, value)
837 int addr;
838 int write;
839 int value;
840 {
841 if (write)
842 {
843 switch (addr)
844 {
845 case TDR1:
846 if (value != '\r')
847 {
848 putchar (value);
849 fflush (stdout);
850 }
851 break;
852 }
853 }
854 else
855 {
856 switch (addr)
857 {
858 case RDR1:
859 return getchar ();
860 }
861 }
862 return 0;
863 }
864
865 static int
866 get_now ()
867 {
868 return time ((long *) 0);
869 }
870
871 static int
872 now_persec ()
873 {
874 return 1;
875 }
876
877 static FILE *profile_file;
878
879 static unsigned INLINE
880 swap (n)
881 unsigned n;
882 {
883 if (endianb)
884 n = (n << 24 | (n & 0xff00) << 8
885 | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
886 return n;
887 }
888
889 static unsigned short INLINE
890 swap16 (n)
891 unsigned short n;
892 {
893 if (endianb)
894 n = n << 8 | (n & 0xff00) >> 8;
895 return n;
896 }
897
898 static void
899 swapout (n)
900 int n;
901 {
902 if (profile_file)
903 {
904 union { char b[4]; int n; } u;
905 u.n = swap (n);
906 fwrite (u.b, 4, 1, profile_file);
907 }
908 }
909
910 static void
911 swapout16 (n)
912 int n;
913 {
914 union { char b[4]; int n; } u;
915 u.n = swap16 (n);
916 fwrite (u.b, 2, 1, profile_file);
917 }
918
919 /* Turn a pointer in a register into a pointer into real memory. */
920
921 static char *
922 ptr (x)
923 int x;
924 {
925 return (char *) (x + saved_state.asregs.memory);
926 }
927
928 static int
929 strswaplen (str)
930 int str;
931 {
932 unsigned char *memory = saved_state.asregs.memory;
933 int start, end;
934 int endian = endianb;
935
936 if (! endian)
937 return 0;
938 end = str;
939 for (end = str; memory[end ^ endian]; end++) ;
940 return end - str;
941 }
942
943 static void
944 strnswap (str, len)
945 int str;
946 int len;
947 {
948 int *start, *end;
949
950 if (! endianb || ! len)
951 return;
952 start = (int *) ptr (str & ~3);
953 end = (int *) ptr (str + len);
954 do
955 {
956 int old = *start;
957 *start = (old << 24 | (old & 0xff00) << 8
958 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
959 start++;
960 }
961 while (start < end);
962 }
963
964 /* Simulate a monitor trap, put the result into r0 and errno into r1
965 return offset by which to adjust pc. */
966
967 static int
968 trap (i, regs, insn_ptr, memory, maskl, maskw, endianw)
969 int i;
970 int *regs;
971 unsigned char *insn_ptr;
972 unsigned char *memory;
973 {
974 switch (i)
975 {
976 case 1:
977 printf ("%c", regs[0]);
978 break;
979 case 2:
980 raise_exception (SIGQUIT);
981 break;
982 case 3: /* FIXME: for backwards compat, should be removed */
983 case 33:
984 {
985 unsigned int countp = * (unsigned int *) (insn_ptr + 4);
986
987 WLAT (countp, RLAT (countp) + 1);
988 return 6;
989 }
990 case 34:
991 {
992 extern int errno;
993 int perrno = errno;
994 errno = 0;
995
996 switch (regs[4])
997 {
998
999 #if !defined(__GO32__) && !defined(_WIN32)
1000 case SYS_fork:
1001 regs[0] = fork ();
1002 break;
1003 /* This would work only if endianness matched between host and target.
1004 Besides, it's quite dangerous. */
1005 #if 0
1006 case SYS_execve:
1007 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]),
1008 (char **) ptr (regs[7]));
1009 break;
1010 case SYS_execv:
1011 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0);
1012 break;
1013 #endif
1014 case SYS_pipe:
1015 {
1016 regs[0] = (BUSERROR (regs[5], maskl)
1017 ? -EINVAL
1018 : pipe ((int *) ptr (regs[5])));
1019 }
1020 break;
1021
1022 case SYS_wait:
1023 regs[0] = wait (ptr (regs[5]));
1024 break;
1025 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1026
1027 case SYS_read:
1028 strnswap (regs[6], regs[7]);
1029 regs[0]
1030 = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
1031 strnswap (regs[6], regs[7]);
1032 break;
1033 case SYS_write:
1034 strnswap (regs[6], regs[7]);
1035 if (regs[5] == 1)
1036 regs[0] = (int) callback->write_stdout (callback,
1037 ptr (regs[6]), regs[7]);
1038 else
1039 regs[0] = (int) callback->write (callback, regs[5],
1040 ptr (regs[6]), regs[7]);
1041 strnswap (regs[6], regs[7]);
1042 break;
1043 case SYS_lseek:
1044 regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
1045 break;
1046 case SYS_close:
1047 regs[0] = callback->close (callback,regs[5]);
1048 break;
1049 case SYS_open:
1050 {
1051 int len = strswaplen (regs[5]);
1052 strnswap (regs[5], len);
1053 regs[0] = callback->open (callback, ptr (regs[5]), regs[6]);
1054 strnswap (regs[5], len);
1055 break;
1056 }
1057 case SYS_exit:
1058 /* EXIT - caller can look in r5 to work out the reason */
1059 raise_exception (SIGQUIT);
1060 regs[0] = regs[5];
1061 break;
1062
1063 case SYS_stat: /* added at hmsi */
1064 /* stat system call */
1065 {
1066 struct stat host_stat;
1067 int buf;
1068 int len = strswaplen (regs[5]);
1069
1070 strnswap (regs[5], len);
1071 regs[0] = stat (ptr (regs[5]), &host_stat);
1072 strnswap (regs[5], len);
1073
1074 buf = regs[6];
1075
1076 WWAT (buf, host_stat.st_dev);
1077 buf += 2;
1078 WWAT (buf, host_stat.st_ino);
1079 buf += 2;
1080 WLAT (buf, host_stat.st_mode);
1081 buf += 4;
1082 WWAT (buf, host_stat.st_nlink);
1083 buf += 2;
1084 WWAT (buf, host_stat.st_uid);
1085 buf += 2;
1086 WWAT (buf, host_stat.st_gid);
1087 buf += 2;
1088 WWAT (buf, host_stat.st_rdev);
1089 buf += 2;
1090 WLAT (buf, host_stat.st_size);
1091 buf += 4;
1092 WLAT (buf, host_stat.st_atime);
1093 buf += 4;
1094 WLAT (buf, 0);
1095 buf += 4;
1096 WLAT (buf, host_stat.st_mtime);
1097 buf += 4;
1098 WLAT (buf, 0);
1099 buf += 4;
1100 WLAT (buf, host_stat.st_ctime);
1101 buf += 4;
1102 WLAT (buf, 0);
1103 buf += 4;
1104 WLAT (buf, 0);
1105 buf += 4;
1106 WLAT (buf, 0);
1107 buf += 4;
1108 }
1109 break;
1110
1111 #ifndef _WIN32
1112 case SYS_chown:
1113 {
1114 int len = strswaplen (regs[5]);
1115
1116 strnswap (regs[5], len);
1117 regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
1118 strnswap (regs[5], len);
1119 break;
1120 }
1121 #endif /* _WIN32 */
1122 case SYS_chmod:
1123 {
1124 int len = strswaplen (regs[5]);
1125
1126 strnswap (regs[5], len);
1127 regs[0] = chmod (ptr (regs[5]), regs[6]);
1128 strnswap (regs[5], len);
1129 break;
1130 }
1131 case SYS_utime:
1132 {
1133 /* Cast the second argument to void *, to avoid type mismatch
1134 if a prototype is present. */
1135 int len = strswaplen (regs[5]);
1136
1137 strnswap (regs[5], len);
1138 regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
1139 strnswap (regs[5], len);
1140 break;
1141 }
1142 case SYS_argc:
1143 regs[0] = count_argc (prog_argv);
1144 break;
1145 case SYS_argnlen:
1146 if (regs[5] < count_argc (prog_argv))
1147 regs[0] = strlen (prog_argv[regs[5]]);
1148 else
1149 regs[0] = -1;
1150 break;
1151 case SYS_argn:
1152 if (regs[5] < count_argc (prog_argv))
1153 {
1154 /* Include the termination byte. */
1155 int i = strlen (prog_argv[regs[5]]) + 1;
1156 regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i);
1157 }
1158 else
1159 regs[0] = -1;
1160 break;
1161 case SYS_time:
1162 regs[0] = get_now ();
1163 break;
1164 case SYS_ftruncate:
1165 regs[0] = callback->ftruncate (callback, regs[5], regs[6]);
1166 break;
1167 case SYS_truncate:
1168 {
1169 int len = strswaplen (regs[5]);
1170 strnswap (regs[5], len);
1171 regs[0] = callback->truncate (callback, ptr (regs[5]), regs[6]);
1172 strnswap (regs[5], len);
1173 break;
1174 }
1175 default:
1176 regs[0] = -1;
1177 break;
1178 }
1179 regs[1] = callback->get_errno (callback);
1180 errno = perrno;
1181 }
1182 break;
1183
1184 case 0xc3:
1185 case 255:
1186 raise_exception (SIGTRAP);
1187 if (i == 0xc3)
1188 return -2;
1189 break;
1190 }
1191 return 0;
1192 }
1193
1194 void
1195 control_c (sig, code, scp, addr)
1196 int sig;
1197 int code;
1198 char *scp;
1199 char *addr;
1200 {
1201 raise_exception (SIGINT);
1202 }
1203
1204 static int
1205 div1 (R, iRn2, iRn1/*, T*/)
1206 int *R;
1207 int iRn1;
1208 int iRn2;
1209 /* int T;*/
1210 {
1211 unsigned long tmp0;
1212 unsigned char old_q, tmp1;
1213
1214 old_q = Q;
1215 SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
1216 R[iRn1] <<= 1;
1217 R[iRn1] |= (unsigned long) T;
1218
1219 switch (old_q)
1220 {
1221 case 0:
1222 switch (M)
1223 {
1224 case 0:
1225 tmp0 = R[iRn1];
1226 R[iRn1] -= R[iRn2];
1227 tmp1 = (R[iRn1] > tmp0);
1228 switch (Q)
1229 {
1230 case 0:
1231 SET_SR_Q (tmp1);
1232 break;
1233 case 1:
1234 SET_SR_Q ((unsigned char) (tmp1 == 0));
1235 break;
1236 }
1237 break;
1238 case 1:
1239 tmp0 = R[iRn1];
1240 R[iRn1] += R[iRn2];
1241 tmp1 = (R[iRn1] < tmp0);
1242 switch (Q)
1243 {
1244 case 0:
1245 SET_SR_Q ((unsigned char) (tmp1 == 0));
1246 break;
1247 case 1:
1248 SET_SR_Q (tmp1);
1249 break;
1250 }
1251 break;
1252 }
1253 break;
1254 case 1:
1255 switch (M)
1256 {
1257 case 0:
1258 tmp0 = R[iRn1];
1259 R[iRn1] += R[iRn2];
1260 tmp1 = (R[iRn1] < tmp0);
1261 switch (Q)
1262 {
1263 case 0:
1264 SET_SR_Q (tmp1);
1265 break;
1266 case 1:
1267 SET_SR_Q ((unsigned char) (tmp1 == 0));
1268 break;
1269 }
1270 break;
1271 case 1:
1272 tmp0 = R[iRn1];
1273 R[iRn1] -= R[iRn2];
1274 tmp1 = (R[iRn1] > tmp0);
1275 switch (Q)
1276 {
1277 case 0:
1278 SET_SR_Q ((unsigned char) (tmp1 == 0));
1279 break;
1280 case 1:
1281 SET_SR_Q (tmp1);
1282 break;
1283 }
1284 break;
1285 }
1286 break;
1287 }
1288 /*T = (Q == M);*/
1289 SET_SR_T (Q == M);
1290 /*return T;*/
1291 }
1292
1293 static void
1294 dmul (sign, rm, rn)
1295 int sign;
1296 unsigned int rm;
1297 unsigned int rn;
1298 {
1299 unsigned long RnL, RnH;
1300 unsigned long RmL, RmH;
1301 unsigned long temp0, temp1, temp2, temp3;
1302 unsigned long Res2, Res1, Res0;
1303
1304 RnL = rn & 0xffff;
1305 RnH = (rn >> 16) & 0xffff;
1306 RmL = rm & 0xffff;
1307 RmH = (rm >> 16) & 0xffff;
1308 temp0 = RmL * RnL;
1309 temp1 = RmH * RnL;
1310 temp2 = RmL * RnH;
1311 temp3 = RmH * RnH;
1312 Res2 = 0;
1313 Res1 = temp1 + temp2;
1314 if (Res1 < temp1)
1315 Res2 += 0x00010000;
1316 temp1 = (Res1 << 16) & 0xffff0000;
1317 Res0 = temp0 + temp1;
1318 if (Res0 < temp0)
1319 Res2 += 1;
1320 Res2 += ((Res1 >> 16) & 0xffff) + temp3;
1321
1322 if (sign)
1323 {
1324 if (rn & 0x80000000)
1325 Res2 -= rm;
1326 if (rm & 0x80000000)
1327 Res2 -= rn;
1328 }
1329
1330 MACH = Res2;
1331 MACL = Res0;
1332 }
1333
1334 static void
1335 macw (regs, memory, n, m, endianw)
1336 int *regs;
1337 unsigned char *memory;
1338 int m, n;
1339 int endianw;
1340 {
1341 long tempm, tempn;
1342 long prod, macl, sum;
1343
1344 tempm=RSWAT (regs[m]); regs[m]+=2;
1345 tempn=RSWAT (regs[n]); regs[n]+=2;
1346
1347 macl = MACL;
1348 prod = (long) (short) tempm * (long) (short) tempn;
1349 sum = prod + macl;
1350 if (S)
1351 {
1352 if ((~(prod ^ macl) & (sum ^ prod)) < 0)
1353 {
1354 /* MACH's lsb is a sticky overflow bit. */
1355 MACH |= 1;
1356 /* Store the smallest negative number in MACL if prod is
1357 negative, and the largest positive number otherwise. */
1358 sum = 0x7fffffff + (prod < 0);
1359 }
1360 }
1361 else
1362 {
1363 long mach;
1364 /* Add to MACH the sign extended product, and carry from low sum. */
1365 mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
1366 /* Sign extend at 10:th bit in MACH. */
1367 MACH = (mach & 0x1ff) | -(mach & 0x200);
1368 }
1369 MACL = sum;
1370 }
1371
1372 static void
1373 macl (regs, memory, n, m)
1374 int *regs;
1375 unsigned char *memory;
1376 int m, n;
1377 {
1378 long tempm, tempn;
1379 long prod, macl, mach, sum;
1380 long long ans,ansl,ansh,t;
1381 unsigned long long high,low,combine;
1382 union mac64
1383 {
1384 long m[2]; /* mach and macl*/
1385 long long m64; /* 64 bit MAC */
1386 }mac64;
1387
1388 tempm = RSLAT (regs[m]);
1389 regs[m] += 4;
1390
1391 tempn = RSLAT (regs[n]);
1392 regs[n] += 4;
1393
1394 mach = MACH;
1395 macl = MACL;
1396
1397 mac64.m[0] = macl;
1398 mac64.m[1] = mach;
1399
1400 ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */
1401
1402 mac64.m64 += ans; /* Accumulate 64bit + 64 bit */
1403
1404 macl = mac64.m[0];
1405 mach = mac64.m[1];
1406
1407 if (S) /* Store only 48 bits of the result */
1408 {
1409 if (mach < 0) /* Result is negative */
1410 {
1411 mach = mach & 0x0000ffff; /* Mask higher 16 bits */
1412 mach |= 0xffff8000; /* Sign extend higher 16 bits */
1413 }
1414 else
1415 mach = mach & 0x00007fff; /* Postive Result */
1416 }
1417
1418 MACL = macl;
1419 MACH = mach;
1420 }
1421
1422
1423 /* GET_LOOP_BOUNDS {EXTENDED}
1424 These two functions compute the actual starting and ending point
1425 of the repeat loop, based on the RS and RE registers (repeat start,
1426 repeat stop). The extended version is called for LDRC, and the
1427 regular version is called for SETRC. The difference is that for
1428 LDRC, the loop start and end instructions are literally the ones
1429 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1430
1431 static struct loop_bounds
1432 get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
1433 int rs, re;
1434 unsigned char *memory, *mem_end;
1435 int maskw, endianw;
1436 {
1437 struct loop_bounds loop;
1438
1439 /* FIXME: should I verify RS < RE? */
1440 loop.start = PT2H (RS); /* FIXME not using the params? */
1441 loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
1442 SKIP_INSN (loop.end);
1443 if (loop.end >= mem_end)
1444 loop.end = PT2H (0);
1445 return loop;
1446 }
1447
1448 float
1449 fsca_s (int in, double (*f) (double))
1450 {
1451 double rad = ldexp ((in & 0xffff), -15) * 3.141592653589793238462643383;
1452 double result = (*f) (rad);
1453 double error, upper, lower, frac;
1454 int exp;
1455
1456 /* Search the value with the maximum error that is still within the
1457 architectural spec. */
1458 error = ldexp (1., -21);
1459 /* compensate for calculation inaccuracy by reducing error. */
1460 error = error - ldexp (1., -50);
1461 upper = result + error;
1462 frac = frexp (upper, &exp);
1463 upper = ldexp (floor (ldexp (frac, 24)), exp - 24);
1464 lower = result - error;
1465 frac = frexp (lower, &exp);
1466 lower = ldexp (ceil (ldexp (frac, 24)), exp - 24);
1467 return abs (upper - result) >= abs (lower - result) ? upper : lower;
1468 }
1469
1470 float
1471 fsrra_s (float in)
1472 {
1473 double result = 1. / sqrt (in);
1474 int exp;
1475 double frac, upper, lower, error, eps;
1476
1477 /* refine result */
1478 result = result - (result * result * in - 1) * 0.5 * result;
1479 /* Search the value with the maximum error that is still within the
1480 architectural spec. */
1481 frac = frexp (result, &exp);
1482 frac = ldexp (frac, 24);
1483 error = 4.0; /* 1 << 24-1-21 */
1484 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1485 eps = ldexp (1., -29);
1486 upper = floor (frac + error - eps);
1487 if (upper > 16777216.)
1488 upper = floor ((frac + error - eps) * 0.5) * 2.;
1489 lower = ceil ((frac - error + eps) * 2) * .5;
1490 if (lower > 8388608.)
1491 lower = ceil (frac - error + eps);
1492 upper = ldexp (upper, exp - 24);
1493 lower = ldexp (lower, exp - 24);
1494 return upper - result >= result - lower ? upper : lower;
1495 }
1496
1497 static struct loop_bounds
1498 get_loop_bounds (rs, re, memory, mem_end, maskw, endianw)
1499 int rs, re;
1500 unsigned char *memory, *mem_end;
1501 int maskw, endianw;
1502 {
1503 struct loop_bounds loop;
1504
1505 if (SR_RC)
1506 {
1507 if (RS >= RE)
1508 {
1509 loop.start = PT2H (RE - 4);
1510 SKIP_INSN (loop.start);
1511 loop.end = loop.start;
1512 if (RS - RE == 0)
1513 SKIP_INSN (loop.end);
1514 if (RS - RE <= 2)
1515 SKIP_INSN (loop.end);
1516 SKIP_INSN (loop.end);
1517 }
1518 else
1519 {
1520 loop.start = PT2H (RS);
1521 loop.end = PT2H (RE - 4);
1522 SKIP_INSN (loop.end);
1523 SKIP_INSN (loop.end);
1524 SKIP_INSN (loop.end);
1525 SKIP_INSN (loop.end);
1526 }
1527 if (loop.end >= mem_end)
1528 loop.end = PT2H (0);
1529 }
1530 else
1531 loop.end = PT2H (0);
1532
1533 return loop;
1534 }
1535
1536 static void ppi_insn ();
1537
1538 #include "ppi.c"
1539
1540 /* Set the memory size to the power of two provided. */
1541
1542 void
1543 sim_size (power)
1544 int power;
1545
1546 {
1547 saved_state.asregs.msize = 1 << power;
1548
1549 sim_memory_size = power;
1550
1551 if (saved_state.asregs.memory)
1552 {
1553 free (saved_state.asregs.memory);
1554 }
1555
1556 saved_state.asregs.memory =
1557 (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
1558
1559 if (!saved_state.asregs.memory)
1560 {
1561 fprintf (stderr,
1562 "Not enough VM for simulation of %d bytes of RAM\n",
1563 saved_state.asregs.msize);
1564
1565 saved_state.asregs.msize = 1;
1566 saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
1567 }
1568 }
1569
1570 static void
1571 init_dsp (abfd)
1572 struct bfd *abfd;
1573 {
1574 int was_dsp = target_dsp;
1575 unsigned long mach = bfd_get_mach (abfd);
1576
1577 if (mach == bfd_mach_sh_dsp ||
1578 mach == bfd_mach_sh4al_dsp ||
1579 mach == bfd_mach_sh3_dsp)
1580 {
1581 int ram_area_size, xram_start, yram_start;
1582 int new_select;
1583
1584 target_dsp = 1;
1585 if (mach == bfd_mach_sh_dsp)
1586 {
1587 /* SH7410 (orig. sh-sdp):
1588 4KB each for X & Y memory;
1589 On-chip X RAM 0x0800f000-0x0800ffff
1590 On-chip Y RAM 0x0801f000-0x0801ffff */
1591 xram_start = 0x0800f000;
1592 ram_area_size = 0x1000;
1593 }
1594 if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
1595 {
1596 /* SH7612:
1597 8KB each for X & Y memory;
1598 On-chip X RAM 0x1000e000-0x1000ffff
1599 On-chip Y RAM 0x1001e000-0x1001ffff */
1600 xram_start = 0x1000e000;
1601 ram_area_size = 0x2000;
1602 }
1603 yram_start = xram_start + 0x10000;
1604 new_select = ~(ram_area_size - 1);
1605 if (saved_state.asregs.xyram_select != new_select)
1606 {
1607 saved_state.asregs.xyram_select = new_select;
1608 free (saved_state.asregs.xmem);
1609 free (saved_state.asregs.ymem);
1610 saved_state.asregs.xmem = (unsigned char *) calloc (1, ram_area_size);
1611 saved_state.asregs.ymem = (unsigned char *) calloc (1, ram_area_size);
1612
1613 /* Disable use of X / Y mmeory if not allocated. */
1614 if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1615 {
1616 saved_state.asregs.xyram_select = 0;
1617 if (saved_state.asregs.xmem)
1618 free (saved_state.asregs.xmem);
1619 if (saved_state.asregs.ymem)
1620 free (saved_state.asregs.ymem);
1621 }
1622 }
1623 saved_state.asregs.xram_start = xram_start;
1624 saved_state.asregs.yram_start = yram_start;
1625 saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1626 saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1627 }
1628 else
1629 {
1630 target_dsp = 0;
1631 if (saved_state.asregs.xyram_select)
1632 {
1633 saved_state.asregs.xyram_select = 0;
1634 free (saved_state.asregs.xmem);
1635 free (saved_state.asregs.ymem);
1636 }
1637 }
1638
1639 if (! saved_state.asregs.xyram_select)
1640 {
1641 saved_state.asregs.xram_start = 1;
1642 saved_state.asregs.yram_start = 1;
1643 }
1644
1645 if (target_dsp != was_dsp)
1646 {
1647 int i, tmp;
1648
1649 for (i = sizeof sh_dsp_table - 1; i >= 0; i--)
1650 {
1651 tmp = sh_jump_table[0xf000 + i];
1652 sh_jump_table[0xf000 + i] = sh_dsp_table[i];
1653 sh_dsp_table[i] = tmp;
1654 }
1655 }
1656 }
1657
1658 static void
1659 init_pointers ()
1660 {
1661 host_little_endian = 0;
1662 * (char*) &host_little_endian = 1;
1663 host_little_endian &= 1;
1664
1665 if (saved_state.asregs.msize != 1 << sim_memory_size)
1666 {
1667 sim_size (sim_memory_size);
1668 }
1669
1670 if (saved_state.asregs.profile && !profile_file)
1671 {
1672 profile_file = fopen ("gmon.out", "wb");
1673 /* Seek to where to put the call arc data */
1674 nsamples = (1 << sim_profile_size);
1675
1676 fseek (profile_file, nsamples * 2 + 12, 0);
1677
1678 if (!profile_file)
1679 {
1680 fprintf (stderr, "Can't open gmon.out\n");
1681 }
1682 else
1683 {
1684 saved_state.asregs.profile_hist =
1685 (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
1686 }
1687 }
1688 }
1689
1690 static void
1691 dump_profile ()
1692 {
1693 unsigned int minpc;
1694 unsigned int maxpc;
1695 unsigned short *p;
1696 int i;
1697
1698 p = saved_state.asregs.profile_hist;
1699 minpc = 0;
1700 maxpc = (1 << sim_profile_size);
1701
1702 fseek (profile_file, 0L, 0);
1703 swapout (minpc << PROFILE_SHIFT);
1704 swapout (maxpc << PROFILE_SHIFT);
1705 swapout (nsamples * 2 + 12);
1706 for (i = 0; i < nsamples; i++)
1707 swapout16 (saved_state.asregs.profile_hist[i]);
1708
1709 }
1710
1711 static void
1712 gotcall (from, to)
1713 int from;
1714 int to;
1715 {
1716 swapout (from);
1717 swapout (to);
1718 swapout (1);
1719 }
1720
1721 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1722
1723 int
1724 sim_stop (sd)
1725 SIM_DESC sd;
1726 {
1727 raise_exception (SIGINT);
1728 return 1;
1729 }
1730
1731 void
1732 sim_resume (sd, step, siggnal)
1733 SIM_DESC sd;
1734 int step, siggnal;
1735 {
1736 register unsigned char *insn_ptr;
1737 unsigned char *mem_end;
1738 struct loop_bounds loop;
1739 register int cycles = 0;
1740 register int stalls = 0;
1741 register int memstalls = 0;
1742 register int insts = 0;
1743 register int prevlock;
1744 register int thislock;
1745 register unsigned int doprofile;
1746 register int pollcount = 0;
1747 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1748 endianb is used less often. */
1749 register int endianw = global_endianw;
1750
1751 int tick_start = get_now ();
1752 void (*prev) ();
1753 void (*prev_fpe) ();
1754
1755 register unsigned char *jump_table = sh_jump_table;
1756
1757 register int *R = &(saved_state.asregs.regs[0]);
1758 /*register int T;*/
1759 #ifndef PR
1760 register int PR;
1761 #endif
1762
1763 register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1764 register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1765 register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1766 register unsigned char *memory;
1767 register unsigned int sbit = ((unsigned int) 1 << 31);
1768
1769 prev = signal (SIGINT, control_c);
1770 prev_fpe = signal (SIGFPE, SIG_IGN);
1771
1772 init_pointers ();
1773 saved_state.asregs.exception = 0;
1774
1775 memory = saved_state.asregs.memory;
1776 mem_end = memory + saved_state.asregs.msize;
1777
1778 if (RE & 1)
1779 loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
1780 else
1781 loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
1782
1783 insn_ptr = PT2H (saved_state.asregs.pc);
1784 CHECK_INSN_PTR (insn_ptr);
1785
1786 #ifndef PR
1787 PR = saved_state.asregs.sregs.named.pr;
1788 #endif
1789 /*T = GET_SR () & SR_MASK_T;*/
1790 prevlock = saved_state.asregs.prevlock;
1791 thislock = saved_state.asregs.thislock;
1792 doprofile = saved_state.asregs.profile;
1793
1794 /* If profiling not enabled, disable it by asking for
1795 profiles infrequently. */
1796 if (doprofile == 0)
1797 doprofile = ~0;
1798
1799 loop:
1800 if (step && insn_ptr < saved_state.asregs.insn_end)
1801 {
1802 if (saved_state.asregs.exception)
1803 /* This can happen if we've already been single-stepping and
1804 encountered a loop end. */
1805 saved_state.asregs.insn_end = insn_ptr;
1806 else
1807 {
1808 saved_state.asregs.exception = SIGTRAP;
1809 saved_state.asregs.insn_end = insn_ptr + 2;
1810 }
1811 }
1812
1813 while (insn_ptr < saved_state.asregs.insn_end)
1814 {
1815 register unsigned int iword = RIAT (insn_ptr);
1816 register unsigned int ult;
1817 register unsigned char *nip = insn_ptr + 2;
1818
1819 #ifndef ACE_FAST
1820 insts++;
1821 #endif
1822 top:
1823
1824 #include "code.c"
1825
1826
1827 insn_ptr = nip;
1828
1829 if (--pollcount < 0)
1830 {
1831 pollcount = POLL_QUIT_INTERVAL;
1832 if ((*callback->poll_quit) != NULL
1833 && (*callback->poll_quit) (callback))
1834 {
1835 sim_stop (sd);
1836 }
1837 }
1838
1839 #ifndef ACE_FAST
1840 prevlock = thislock;
1841 thislock = 30;
1842 cycles++;
1843
1844 if (cycles >= doprofile)
1845 {
1846
1847 saved_state.asregs.cycles += doprofile;
1848 cycles -= doprofile;
1849 if (saved_state.asregs.profile_hist)
1850 {
1851 int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
1852 if (n < nsamples)
1853 {
1854 int i = saved_state.asregs.profile_hist[n];
1855 if (i < 65000)
1856 saved_state.asregs.profile_hist[n] = i + 1;
1857 }
1858
1859 }
1860 }
1861 #endif
1862 }
1863 if (saved_state.asregs.insn_end == loop.end)
1864 {
1865 saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
1866 if (SR_RC)
1867 insn_ptr = loop.start;
1868 else
1869 {
1870 saved_state.asregs.insn_end = mem_end;
1871 loop.end = PT2H (0);
1872 }
1873 goto loop;
1874 }
1875
1876 if (saved_state.asregs.exception == SIGILL
1877 || saved_state.asregs.exception == SIGBUS)
1878 {
1879 insn_ptr -= 2;
1880 }
1881 /* Check for SIGBUS due to insn fetch. */
1882 else if (! saved_state.asregs.exception)
1883 saved_state.asregs.exception = SIGBUS;
1884
1885 saved_state.asregs.ticks += get_now () - tick_start;
1886 saved_state.asregs.cycles += cycles;
1887 saved_state.asregs.stalls += stalls;
1888 saved_state.asregs.memstalls += memstalls;
1889 saved_state.asregs.insts += insts;
1890 saved_state.asregs.pc = PH2T (insn_ptr);
1891 #ifndef PR
1892 saved_state.asregs.sregs.named.pr = PR;
1893 #endif
1894
1895 saved_state.asregs.prevlock = prevlock;
1896 saved_state.asregs.thislock = thislock;
1897
1898 if (profile_file)
1899 {
1900 dump_profile ();
1901 }
1902
1903 signal (SIGFPE, prev_fpe);
1904 signal (SIGINT, prev);
1905 }
1906
1907 int
1908 sim_write (sd, addr, buffer, size)
1909 SIM_DESC sd;
1910 SIM_ADDR addr;
1911 unsigned char *buffer;
1912 int size;
1913 {
1914 int i;
1915
1916 init_pointers ();
1917
1918 for (i = 0; i < size; i++)
1919 {
1920 saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
1921 }
1922 return size;
1923 }
1924
1925 int
1926 sim_read (sd, addr, buffer, size)
1927 SIM_DESC sd;
1928 SIM_ADDR addr;
1929 unsigned char *buffer;
1930 int size;
1931 {
1932 int i;
1933
1934 init_pointers ();
1935
1936 for (i = 0; i < size; i++)
1937 {
1938 buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
1939 }
1940 return size;
1941 }
1942
1943 int
1944 sim_store_register (sd, rn, memory, length)
1945 SIM_DESC sd;
1946 int rn;
1947 unsigned char *memory;
1948 int length;
1949 {
1950 unsigned val;
1951
1952 init_pointers ();
1953 val = swap (* (int *) memory);
1954 switch (rn)
1955 {
1956 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
1957 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
1958 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
1959 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
1960 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
1961 case SIM_SH_R15_REGNUM:
1962 saved_state.asregs.regs[rn] = val;
1963 break;
1964 case SIM_SH_PC_REGNUM:
1965 saved_state.asregs.pc = val;
1966 break;
1967 case SIM_SH_PR_REGNUM:
1968 PR = val;
1969 break;
1970 case SIM_SH_GBR_REGNUM:
1971 GBR = val;
1972 break;
1973 case SIM_SH_VBR_REGNUM:
1974 VBR = val;
1975 break;
1976 case SIM_SH_MACH_REGNUM:
1977 MACH = val;
1978 break;
1979 case SIM_SH_MACL_REGNUM:
1980 MACL = val;
1981 break;
1982 case SIM_SH_SR_REGNUM:
1983 SET_SR (val);
1984 break;
1985 case SIM_SH_FPUL_REGNUM:
1986 FPUL = val;
1987 break;
1988 case SIM_SH_FPSCR_REGNUM:
1989 SET_FPSCR (val);
1990 break;
1991 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
1992 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
1993 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
1994 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
1995 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
1996 case SIM_SH_FR15_REGNUM:
1997 SET_FI (rn - SIM_SH_FR0_REGNUM, val);
1998 break;
1999 case SIM_SH_DSR_REGNUM:
2000 DSR = val;
2001 break;
2002 case SIM_SH_A0G_REGNUM:
2003 A0G = val;
2004 break;
2005 case SIM_SH_A0_REGNUM:
2006 A0 = val;
2007 break;
2008 case SIM_SH_A1G_REGNUM:
2009 A1G = val;
2010 break;
2011 case SIM_SH_A1_REGNUM:
2012 A1 = val;
2013 break;
2014 case SIM_SH_M0_REGNUM:
2015 M0 = val;
2016 break;
2017 case SIM_SH_M1_REGNUM:
2018 M1 = val;
2019 break;
2020 case SIM_SH_X0_REGNUM:
2021 X0 = val;
2022 break;
2023 case SIM_SH_X1_REGNUM:
2024 X1 = val;
2025 break;
2026 case SIM_SH_Y0_REGNUM:
2027 Y0 = val;
2028 break;
2029 case SIM_SH_Y1_REGNUM:
2030 Y1 = val;
2031 break;
2032 case SIM_SH_MOD_REGNUM:
2033 SET_MOD (val);
2034 break;
2035 case SIM_SH_RS_REGNUM:
2036 RS = val;
2037 break;
2038 case SIM_SH_RE_REGNUM:
2039 RE = val;
2040 break;
2041 case SIM_SH_SSR_REGNUM:
2042 SSR = val;
2043 break;
2044 case SIM_SH_SPC_REGNUM:
2045 SPC = val;
2046 break;
2047 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2048 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2049 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2050 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2051 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2052 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2053 if (SR_MD && SR_RB)
2054 Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
2055 else
2056 saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
2057 break;
2058 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2059 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2060 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2061 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2062 if (SR_MD && SR_RB)
2063 saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
2064 else
2065 Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
2066 break;
2067 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2068 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2069 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2070 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2071 SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
2072 break;
2073 default:
2074 return 0;
2075 }
2076 return -1;
2077 }
2078
2079 int
2080 sim_fetch_register (sd, rn, memory, length)
2081 SIM_DESC sd;
2082 int rn;
2083 unsigned char *memory;
2084 int length;
2085 {
2086 int val;
2087
2088 init_pointers ();
2089 switch (rn)
2090 {
2091 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
2092 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
2093 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
2094 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
2095 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
2096 case SIM_SH_R15_REGNUM:
2097 val = saved_state.asregs.regs[rn];
2098 break;
2099 case SIM_SH_PC_REGNUM:
2100 val = saved_state.asregs.pc;
2101 break;
2102 case SIM_SH_PR_REGNUM:
2103 val = PR;
2104 break;
2105 case SIM_SH_GBR_REGNUM:
2106 val = GBR;
2107 break;
2108 case SIM_SH_VBR_REGNUM:
2109 val = VBR;
2110 break;
2111 case SIM_SH_MACH_REGNUM:
2112 val = MACH;
2113 break;
2114 case SIM_SH_MACL_REGNUM:
2115 val = MACL;
2116 break;
2117 case SIM_SH_SR_REGNUM:
2118 val = GET_SR ();
2119 break;
2120 case SIM_SH_FPUL_REGNUM:
2121 val = FPUL;
2122 break;
2123 case SIM_SH_FPSCR_REGNUM:
2124 val = GET_FPSCR ();
2125 break;
2126 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
2127 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
2128 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
2129 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
2130 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
2131 case SIM_SH_FR15_REGNUM:
2132 val = FI (rn - SIM_SH_FR0_REGNUM);
2133 break;
2134 case SIM_SH_DSR_REGNUM:
2135 val = DSR;
2136 break;
2137 case SIM_SH_A0G_REGNUM:
2138 val = SEXT (A0G);
2139 break;
2140 case SIM_SH_A0_REGNUM:
2141 val = A0;
2142 break;
2143 case SIM_SH_A1G_REGNUM:
2144 val = SEXT (A1G);
2145 break;
2146 case SIM_SH_A1_REGNUM:
2147 val = A1;
2148 break;
2149 case SIM_SH_M0_REGNUM:
2150 val = M0;
2151 break;
2152 case SIM_SH_M1_REGNUM:
2153 val = M1;
2154 break;
2155 case SIM_SH_X0_REGNUM:
2156 val = X0;
2157 break;
2158 case SIM_SH_X1_REGNUM:
2159 val = X1;
2160 break;
2161 case SIM_SH_Y0_REGNUM:
2162 val = Y0;
2163 break;
2164 case SIM_SH_Y1_REGNUM:
2165 val = Y1;
2166 break;
2167 case SIM_SH_MOD_REGNUM:
2168 val = MOD;
2169 break;
2170 case SIM_SH_RS_REGNUM:
2171 val = RS;
2172 break;
2173 case SIM_SH_RE_REGNUM:
2174 val = RE;
2175 break;
2176 case SIM_SH_SSR_REGNUM:
2177 val = SSR;
2178 break;
2179 case SIM_SH_SPC_REGNUM:
2180 val = SPC;
2181 break;
2182 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2183 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2184 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2185 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2186 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2187 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2188 val = (SR_MD && SR_RB
2189 ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
2190 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
2191 break;
2192 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2193 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2194 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2195 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2196 val = (! SR_MD || ! SR_RB
2197 ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
2198 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
2199 break;
2200 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2201 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2202 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2203 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2204 val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
2205 break;
2206 default:
2207 return 0;
2208 }
2209 * (int *) memory = swap (val);
2210 return -1;
2211 }
2212
2213 int
2214 sim_trace (sd)
2215 SIM_DESC sd;
2216 {
2217 return 0;
2218 }
2219
2220 void
2221 sim_stop_reason (sd, reason, sigrc)
2222 SIM_DESC sd;
2223 enum sim_stop *reason;
2224 int *sigrc;
2225 {
2226 /* The SH simulator uses SIGQUIT to indicate that the program has
2227 exited, so we must check for it here and translate it to exit. */
2228 if (saved_state.asregs.exception == SIGQUIT)
2229 {
2230 *reason = sim_exited;
2231 *sigrc = saved_state.asregs.regs[5];
2232 }
2233 else
2234 {
2235 *reason = sim_stopped;
2236 *sigrc = saved_state.asregs.exception;
2237 }
2238 }
2239
2240 void
2241 sim_info (sd, verbose)
2242 SIM_DESC sd;
2243 int verbose;
2244 {
2245 double timetaken =
2246 (double) saved_state.asregs.ticks / (double) now_persec ();
2247 double virttime = saved_state.asregs.cycles / 36.0e6;
2248
2249 callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
2250 saved_state.asregs.insts);
2251 callback->printf_filtered (callback, "# cycles %10d\n",
2252 saved_state.asregs.cycles);
2253 callback->printf_filtered (callback, "# pipeline stalls %10d\n",
2254 saved_state.asregs.stalls);
2255 callback->printf_filtered (callback, "# misaligned load/store %10d\n",
2256 saved_state.asregs.memstalls);
2257 callback->printf_filtered (callback, "# real time taken %10.4f\n",
2258 timetaken);
2259 callback->printf_filtered (callback, "# virtual time taken %10.4f\n",
2260 virttime);
2261 callback->printf_filtered (callback, "# profiling size %10d\n",
2262 sim_profile_size);
2263 callback->printf_filtered (callback, "# profiling frequency %10d\n",
2264 saved_state.asregs.profile);
2265 callback->printf_filtered (callback, "# profile maxpc %10x\n",
2266 (1 << sim_profile_size) << PROFILE_SHIFT);
2267
2268 if (timetaken != 0)
2269 {
2270 callback->printf_filtered (callback, "# cycles/second %10d\n",
2271 (int) (saved_state.asregs.cycles / timetaken));
2272 callback->printf_filtered (callback, "# simulation ratio %10.4f\n",
2273 virttime / timetaken);
2274 }
2275 }
2276
2277 void
2278 sim_set_profile (n)
2279 int n;
2280 {
2281 saved_state.asregs.profile = n;
2282 }
2283
2284 void
2285 sim_set_profile_size (n)
2286 int n;
2287 {
2288 sim_profile_size = n;
2289 }
2290
2291 SIM_DESC
2292 sim_open (kind, cb, abfd, argv)
2293 SIM_OPEN_KIND kind;
2294 host_callback *cb;
2295 struct bfd *abfd;
2296 char **argv;
2297 {
2298 char **p;
2299 int endian_set = 0;
2300 int i;
2301 union
2302 {
2303 int i;
2304 short s[2];
2305 char c[4];
2306 }
2307 mem_word;
2308
2309 sim_kind = kind;
2310 myname = argv[0];
2311 callback = cb;
2312
2313 for (p = argv + 1; *p != NULL; ++p)
2314 {
2315 if (strcmp (*p, "-E") == 0)
2316 {
2317 ++p;
2318 if (*p == NULL)
2319 {
2320 /* FIXME: This doesn't use stderr, but then the rest of the
2321 file doesn't either. */
2322 callback->printf_filtered (callback, "Missing argument to `-E'.\n");
2323 return 0;
2324 }
2325 target_little_endian = strcmp (*p, "big") != 0;
2326 endian_set = 1;
2327 }
2328 else if (isdigit (**p))
2329 parse_and_set_memory_size (*p);
2330 }
2331
2332 if (abfd != NULL && ! endian_set)
2333 target_little_endian = ! bfd_big_endian (abfd);
2334
2335 if (abfd)
2336 init_dsp (abfd);
2337
2338 for (i = 4; (i -= 2) >= 0; )
2339 mem_word.s[i >> 1] = i;
2340 global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
2341
2342 for (i = 4; --i >= 0; )
2343 mem_word.c[i] = i;
2344 endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
2345
2346 /* fudge our descriptor for now */
2347 return (SIM_DESC) 1;
2348 }
2349
2350 static void
2351 parse_and_set_memory_size (str)
2352 char *str;
2353 {
2354 int n;
2355
2356 n = strtol (str, NULL, 10);
2357 if (n > 0 && n <= 24)
2358 sim_memory_size = n;
2359 else
2360 callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
2361 }
2362
2363 void
2364 sim_close (sd, quitting)
2365 SIM_DESC sd;
2366 int quitting;
2367 {
2368 /* nothing to do */
2369 }
2370
2371 SIM_RC
2372 sim_load (sd, prog, abfd, from_tty)
2373 SIM_DESC sd;
2374 char *prog;
2375 bfd *abfd;
2376 int from_tty;
2377 {
2378 extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
2379 bfd *prog_bfd;
2380
2381 prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
2382 sim_kind == SIM_OPEN_DEBUG,
2383 0, sim_write);
2384 if (prog_bfd == NULL)
2385 return SIM_RC_FAIL;
2386 if (abfd == NULL)
2387 bfd_close (prog_bfd);
2388 return SIM_RC_OK;
2389 }
2390
2391 SIM_RC
2392 sim_create_inferior (sd, prog_bfd, argv, env)
2393 SIM_DESC sd;
2394 struct bfd *prog_bfd;
2395 char **argv;
2396 char **env;
2397 {
2398 /* Clear the registers. */
2399 memset (&saved_state, 0,
2400 (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
2401
2402 /* Set the PC. */
2403 if (prog_bfd != NULL)
2404 saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2405
2406 /* Record the program's arguments. */
2407 prog_argv = argv;
2408
2409 return SIM_RC_OK;
2410 }
2411
2412 void
2413 sim_do_command (sd, cmd)
2414 SIM_DESC sd;
2415 char *cmd;
2416 {
2417 char *sms_cmd = "set-memory-size";
2418 int cmdsize;
2419
2420 if (cmd == NULL || *cmd == '\0')
2421 {
2422 cmd = "help";
2423 }
2424
2425 cmdsize = strlen (sms_cmd);
2426 if (strncmp (cmd, sms_cmd, cmdsize) == 0
2427 && strchr (" \t", cmd[cmdsize]) != NULL)
2428 {
2429 parse_and_set_memory_size (cmd + cmdsize + 1);
2430 }
2431 else if (strcmp (cmd, "help") == 0)
2432 {
2433 (callback->printf_filtered) (callback,
2434 "List of SH simulator commands:\n\n");
2435 (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
2436 (callback->printf_filtered) (callback, "\n");
2437 }
2438 else
2439 {
2440 (callback->printf_filtered) (callback, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);
2441 }
2442 }
2443
2444 void
2445 sim_set_callbacks (p)
2446 host_callback *p;
2447 {
2448 callback = p;
2449 }
GDB Binutils - Deliverables
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