1 /* Simulator for the Hitachi SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
31 #include "remote-sim.h"
33 /* This file is local - if newlib changes, then so should this. */
39 #include <float.h> /* Needed for _isnan() */
44 #define SIGBUS SIGSEGV
48 #define SIGQUIT SIGTERM
55 extern unsigned char sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
57 int sim_write (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
);
59 #define O_RECOMPILE 85
61 #define DISASSEMBLER_TABLE
63 /* Define the rate at which the simulator should poll the host
65 #define POLL_QUIT_INTERVAL 0x60000
75 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
76 which are located in fregs, i.e. strictly speaking, these are
77 out-of-bounds accesses of sregs.i . This wart of the code could be
78 fixed by making fregs part of sregs, and including pc too - to avoid
79 alignment repercussions - but this would cause very onerous union /
80 structure nesting, which would only be managable with anonymous
81 unions and structs. */
90 int fpul
; /* A1 for sh-dsp - but only for movs etc. */
91 int fpscr
; /* dsr for sh-dsp */
105 /* Control registers; on the SH4, ldc / stc is privileged, except when
126 unsigned char *insn_end
;
138 int end_of_registers
;
141 #define PROFILE_FREQ 1
142 #define PROFILE_SHIFT 2
144 unsigned short *profile_hist
;
145 unsigned char *memory
;
146 int xyram_select
, xram_start
, yram_start
;
149 unsigned char *xmem_offset
;
150 unsigned char *ymem_offset
;
156 saved_state_type saved_state
;
158 struct loop_bounds
{ unsigned char *start
, *end
; };
160 /* These variables are at file scope so that functions other than
161 sim_resume can use the fetch/store macros */
163 static int target_little_endian
;
164 static int global_endianw
, endianb
;
165 static int target_dsp
;
166 static int host_little_endian
;
167 static char **prog_argv
;
170 static int maskw
= 0;
173 static SIM_OPEN_KIND sim_kind
;
177 /* Short hand definitions of the registers */
179 #define SBIT(x) ((x)&sbit)
180 #define R0 saved_state.asregs.regs[0]
181 #define Rn saved_state.asregs.regs[n]
182 #define Rm saved_state.asregs.regs[m]
183 #define UR0 (unsigned int)(saved_state.asregs.regs[0])
184 #define UR (unsigned int)R
185 #define UR (unsigned int)R
186 #define SR0 saved_state.asregs.regs[0]
187 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
188 #define GBR saved_state.asregs.cregs.named.gbr
189 #define VBR saved_state.asregs.cregs.named.vbr
190 #define SSR saved_state.asregs.cregs.named.ssr
191 #define SPC saved_state.asregs.cregs.named.spc
192 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
193 #define MACH saved_state.asregs.sregs.named.mach
194 #define MACL saved_state.asregs.sregs.named.macl
195 #define PR saved_state.asregs.sregs.named.pr
196 #define FPUL saved_state.asregs.sregs.named.fpul
202 /* Alternate bank of registers r0-r7 */
204 /* Note: code controling SR handles flips between BANK0 and BANK1 */
205 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
206 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
211 #define SR_MASK_DMY (1 << 11)
212 #define SR_MASK_DMX (1 << 10)
213 #define SR_MASK_M (1 << 9)
214 #define SR_MASK_Q (1 << 8)
215 #define SR_MASK_I (0xf << 4)
216 #define SR_MASK_S (1 << 1)
217 #define SR_MASK_T (1 << 0)
219 #define SR_MASK_BL (1 << 28)
220 #define SR_MASK_RB (1 << 29)
221 #define SR_MASK_MD (1 << 30)
222 #define SR_MASK_RC 0x0fff0000
223 #define SR_RC_INCREMENT -0x00010000
225 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
226 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
227 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
228 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
230 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
231 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
232 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
233 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
234 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
235 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
237 /* Note: don't use this for privileged bits */
238 #define SET_SR_BIT(EXP, BIT) \
241 saved_state.asregs.cregs.named.sr |= (BIT); \
243 saved_state.asregs.cregs.named.sr &= ~(BIT); \
246 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
247 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
248 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
249 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
251 /* stc currently relies on being able to read SR without modifications. */
252 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
254 #define SET_SR(x) set_sr (x)
257 (saved_state.asregs.cregs.named.sr \
258 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
260 /* Manipulate FPSCR */
262 #define FPSCR_MASK_FR (1 << 21)
263 #define FPSCR_MASK_SZ (1 << 20)
264 #define FPSCR_MASK_PR (1 << 19)
266 #define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
267 #define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
268 #define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
270 /* Count the number of arguments in an argv. */
272 count_argc (char **argv
)
279 for (i
= 0; argv
[i
] != NULL
; ++i
)
288 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
289 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
290 /* swap the floating point register banks */
291 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
292 /* Ignore bit change if simulating sh-dsp. */
295 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
296 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
297 saved_state
.asregs
.fregs
[1] = tmpf
;
301 /* sts relies on being able to read fpscr directly. */
302 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
303 #define SET_FPSCR(x) \
308 #define DSR (saved_state.asregs.sregs.named.fpscr)
316 #define RAISE_EXCEPTION(x) \
317 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
319 /* This function exists mainly for the purpose of setting a breakpoint to
320 catch simulated bus errors when running the simulator under GDB. */
332 raise_exception (SIGBUS
);
335 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
336 forbidden_addr_bits, data, retval) \
338 if (addr & forbidden_addr_bits) \
343 else if ((addr & saved_state.asregs.xyram_select) \
344 == saved_state.asregs.xram_start) \
345 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
346 else if ((addr & saved_state.asregs.xyram_select) \
347 == saved_state.asregs.yram_start) \
348 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
349 else if ((unsigned) addr >> 24 == 0xf0 \
350 && bits_written == 32 && (data & 1) == 0) \
351 /* This invalidates (if not associative) or might invalidate \
352 (if associative) an instruction cache line. This is used for \
353 trampolines. Since we don't simulate the cache, this is a no-op \
354 as far as the simulator is concerned. */ \
358 if (bits_written == 8 && addr > 0x5000000) \
359 IOMEM (addr, 1, data); \
360 /* We can't do anything useful with the other stuff, so fail. */ \
366 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
367 being implemented by ../common/sim_resume.c and the below should
368 make a call to sim_engine_halt */
370 #define BUSERROR(addr, mask) ((addr) & (mask))
372 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
377 addr_func (addr, data); \
383 #define READ_BUSERROR(addr, mask, addr_func) \
387 return addr_func (addr); \
391 /* Define this to enable register lifetime checking.
392 The compiler generates "add #0,rn" insns to mark registers as invalid,
393 the simulator uses this info to call fail if it finds a ref to an invalid
394 register before a def
401 #define CREF(x) if(!valid[x]) fail();
402 #define CDEF(x) valid[x] = 1;
403 #define UNDEF(x) valid[x] = 0;
410 static void parse_and_set_memory_size
PARAMS ((char *str
));
411 static int IOMEM
PARAMS ((int addr
, int write
, int value
));
412 static struct loop_bounds get_loop_bounds
PARAMS((int, int, unsigned char *,
413 unsigned char *, int, int));
414 static void process_wlat_addr
PARAMS((int, int));
415 static void process_wwat_addr
PARAMS((int, int));
416 static void process_wbat_addr
PARAMS((int, int));
417 static int process_rlat_addr
PARAMS((int));
418 static int process_rwat_addr
PARAMS((int));
419 static int process_rbat_addr
PARAMS((int));
420 static void INLINE wlat_fast
PARAMS ((unsigned char *, int, int, int));
421 static void INLINE wwat_fast
PARAMS ((unsigned char *, int, int, int, int));
422 static void INLINE wbat_fast
PARAMS ((unsigned char *, int, int, int));
423 static int INLINE rlat_fast
PARAMS ((unsigned char *, int, int));
424 static int INLINE rwat_fast
PARAMS ((unsigned char *, int, int, int));
425 static int INLINE rbat_fast
PARAMS ((unsigned char *, int, int));
427 static host_callback
*callback
;
431 /* Floating point registers */
433 #define DR(n) (get_dr (n))
439 if (host_little_endian
)
446 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
447 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
451 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
454 #define SET_DR(n, EXP) set_dr ((n), (EXP))
461 if (host_little_endian
)
469 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
470 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
473 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
476 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
477 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
479 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
480 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
482 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
483 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
484 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
486 #define RS saved_state.asregs.cregs.named.rs
487 #define RE saved_state.asregs.cregs.named.re
488 #define MOD (saved_state.asregs.cregs.named.mod)
491 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
492 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
494 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
495 #define DSP_GRD(n) DSP_R ((n) + 8)
496 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
501 #define Y0 DSP_R (10)
502 #define Y1 DSP_R (11)
503 #define M0 DSP_R (12)
504 #define A1G DSP_R (13)
505 #define M1 DSP_R (14)
506 #define A0G DSP_R (15)
507 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
508 #define MOD_ME DSP_GRD (17)
509 #define MOD_DELTA DSP_GRD (18)
511 #define FP_OP(n, OP, m) \
515 if (((n) & 1) || ((m) & 1)) \
516 RAISE_EXCEPTION (SIGILL); \
518 SET_DR(n, (DR(n) OP DR(m))); \
521 SET_FR(n, (FR(n) OP FR(m))); \
524 #define FP_UNARY(n, OP) \
529 RAISE_EXCEPTION (SIGILL); \
531 SET_DR(n, (OP (DR(n)))); \
534 SET_FR(n, (OP (FR(n)))); \
537 #define FP_CMP(n, OP, m) \
541 if (((n) & 1) || ((m) & 1)) \
542 RAISE_EXCEPTION (SIGILL); \
544 SET_SR_T (DR(n) OP DR(m)); \
547 SET_SR_T (FR(n) OP FR(m)); \
554 /* do we need to swap banks */
555 int old_gpr
= SR_MD
&& SR_RB
;
556 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
557 if (old_gpr
!= new_gpr
)
560 for (i
= 0; i
< 8; i
++)
562 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
563 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
564 saved_state
.asregs
.regs
[i
] = tmp
;
567 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
572 wlat_fast (memory
, x
, value
, maskl
)
573 unsigned char *memory
;
576 unsigned int *p
= (unsigned int *)(memory
+ x
);
577 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
582 wwat_fast (memory
, x
, value
, maskw
, endianw
)
583 unsigned char *memory
;
586 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
587 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
592 wbat_fast (memory
, x
, value
, maskb
)
593 unsigned char *memory
;
595 unsigned char *p
= memory
+ (x
^ endianb
);
596 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
604 rlat_fast (memory
, x
, maskl
)
605 unsigned char *memory
;
607 unsigned int *p
= (unsigned int *)(memory
+ x
);
608 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
614 rwat_fast (memory
, x
, maskw
, endianw
)
615 unsigned char *memory
;
616 int x
, maskw
, endianw
;
618 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
619 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
625 riat_fast (insn_ptr
, endianw
)
626 unsigned char *insn_ptr
;
628 unsigned short *p
= (unsigned short *)((size_t) insn_ptr
^ endianw
);
634 rbat_fast (memory
, x
, maskb
)
635 unsigned char *memory
;
637 unsigned char *p
= memory
+ (x
^ endianb
);
638 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
643 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
644 #define RLAT(x) (rlat_fast (memory, x, maskl))
645 #define RBAT(x) (rbat_fast (memory, x, maskb))
646 #define RIAT(p) (riat_fast ((p), endianw))
647 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
648 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
649 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
651 #define RUWAT(x) (RWAT(x) & 0xffff)
652 #define RSWAT(x) ((short)(RWAT(x)))
653 #define RSBAT(x) (SEXT(RBAT(x)))
655 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
657 do_rdat (memory
, x
, n
, maskl
)
667 f0
= rlat_fast (memory
, x
+ 0, maskl
);
668 f1
= rlat_fast (memory
, x
+ 4, maskl
);
669 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
670 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
674 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
676 do_wdat (memory
, x
, n
, maskl
)
686 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
687 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
688 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
689 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
694 process_wlat_addr (addr
, value
)
700 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
705 process_wwat_addr (addr
, value
)
711 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
716 process_wbat_addr (addr
, value
)
722 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
727 process_rlat_addr (addr
)
732 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
737 process_rwat_addr (addr
)
742 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
747 process_rbat_addr (addr
)
752 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
756 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
757 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
758 #define SEXTW(y) ((int)((short)y))
760 #define SEXT32(x) ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
762 #define SEXT32(x) ((int)(x))
764 #define SIGN32(x) (SEXT32 (x) >> 31)
766 /* convert pointer from target to host value. */
767 #define PT2H(x) ((x) + memory)
768 /* convert pointer from host to target value. */
769 #define PH2T(x) ((x) - memory)
771 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
773 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
775 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); goto top;
777 #define CHECK_INSN_PTR(p) \
779 if (saved_state.asregs.exception || PH2T (p) & maskw) \
780 saved_state.asregs.insn_end = 0; \
781 else if (p < loop.end) \
782 saved_state.asregs.insn_end = loop.end; \
784 saved_state.asregs.insn_end = mem_end; \
797 do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
799 #define L(x) thislock = x;
800 #define TL(x) if ((x) == prevlock) stalls++;
801 #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
805 #if defined(__GO32__) || defined(_WIN32)
806 int sim_memory_size
= 19;
808 int sim_memory_size
= 24;
811 static int sim_profile_size
= 17;
817 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
818 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
819 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
820 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
821 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
822 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
824 #define SCI_RDRF 0x40 /* Recieve data register full */
825 #define SCI_TDRE 0x80 /* Transmit data register empty */
828 IOMEM (addr
, write
, value
)
860 return time ((long *) 0);
869 static FILE *profile_file
;
871 static unsigned INLINE
876 n
= (n
<< 24 | (n
& 0xff00) << 8
877 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
881 static unsigned short INLINE
886 n
= n
<< 8 | (n
& 0xff00) >> 8;
896 union { char b
[4]; int n
; } u
;
898 fwrite (u
.b
, 4, 1, profile_file
);
906 union { char b
[4]; int n
; } u
;
908 fwrite (u
.b
, 2, 1, profile_file
);
911 /* Turn a pointer in a register into a pointer into real memory. */
917 return (char *) (x
+ saved_state
.asregs
.memory
);
924 unsigned char *memory
= saved_state
.asregs
.memory
;
926 int endian
= endianb
;
931 for (end
= str
; memory
[end
^ endian
]; end
++) ;
942 if (! endianb
|| ! len
)
944 start
= (int *) ptr (str
& ~3);
945 end
= (int *) ptr (str
+ len
);
949 *start
= (old
<< 24 | (old
& 0xff00) << 8
950 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
956 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
959 trap (i
, regs
, memory
, maskl
, maskw
, endianw
)
962 unsigned char *memory
;
967 printf ("%c", regs
[0]);
970 raise_exception (SIGQUIT
);
972 case 3: /* FIXME: for backwards compat, should be removed */
982 #if !defined(__GO32__) && !defined(_WIN32)
986 /* This would work only if endianness matched between host and target.
987 Besides, it's quite dangerous. */
990 regs
[0] = execve (ptr (regs
[5]), (char **)ptr (regs
[6]), (char **)ptr (regs
[7]));
993 regs
[0] = execve (ptr (regs
[5]),(char **) ptr (regs
[6]), 0);
998 regs
[0] = (BUSERROR (regs
[5], maskl
)
1000 : pipe ((int *) ptr (regs
[5])));
1005 regs
[0] = wait (ptr (regs
[5]));
1007 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1010 strnswap (regs
[6], regs
[7]);
1012 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1013 strnswap (regs
[6], regs
[7]);
1016 strnswap (regs
[6], regs
[7]);
1018 regs
[0] = (int)callback
->write_stdout (callback
, ptr(regs
[6]), regs
[7]);
1020 regs
[0] = (int)callback
->write (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1021 strnswap (regs
[6], regs
[7]);
1024 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
1027 regs
[0] = callback
->close (callback
,regs
[5]);
1031 int len
= strswaplen (regs
[5]);
1032 strnswap (regs
[5], len
);
1033 regs
[0] = callback
->open (callback
,ptr (regs
[5]), regs
[6]);
1034 strnswap (regs
[5], len
);
1038 /* EXIT - caller can look in r5 to work out the reason */
1039 raise_exception (SIGQUIT
);
1043 case SYS_stat
: /* added at hmsi */
1044 /* stat system call */
1046 struct stat host_stat
;
1048 int len
= strswaplen (regs
[5]);
1050 strnswap (regs
[5], len
);
1051 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
1052 strnswap (regs
[5], len
);
1056 WWAT (buf
, host_stat
.st_dev
);
1058 WWAT (buf
, host_stat
.st_ino
);
1060 WLAT (buf
, host_stat
.st_mode
);
1062 WWAT (buf
, host_stat
.st_nlink
);
1064 WWAT (buf
, host_stat
.st_uid
);
1066 WWAT (buf
, host_stat
.st_gid
);
1068 WWAT (buf
, host_stat
.st_rdev
);
1070 WLAT (buf
, host_stat
.st_size
);
1072 WLAT (buf
, host_stat
.st_atime
);
1076 WLAT (buf
, host_stat
.st_mtime
);
1080 WLAT (buf
, host_stat
.st_ctime
);
1094 int len
= strswaplen (regs
[5]);
1096 strnswap (regs
[5], len
);
1097 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1098 strnswap (regs
[5], len
);
1104 int len
= strswaplen (regs
[5]);
1106 strnswap (regs
[5], len
);
1107 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1108 strnswap (regs
[5], len
);
1113 /* Cast the second argument to void *, to avoid type mismatch
1114 if a prototype is present. */
1115 int len
= strswaplen (regs
[5]);
1117 strnswap (regs
[5], len
);
1118 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1119 strnswap (regs
[5], len
);
1123 regs
[0] = count_argc (prog_argv
);
1126 if (regs
[5] < count_argc (prog_argv
))
1127 regs
[0] = strlen (prog_argv
[regs
[5]]);
1132 if (regs
[5] < count_argc (prog_argv
))
1134 /* Include the termination byte. */
1135 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1136 regs
[0] = sim_write (0, regs
[6], prog_argv
[regs
[5]], i
);
1142 regs
[0] = get_now ();
1148 regs
[1] = callback
->get_errno (callback
);
1155 raise_exception (SIGTRAP
);
1162 control_c (sig
, code
, scp
, addr
)
1168 raise_exception (SIGINT
);
1172 div1 (R
, iRn2
, iRn1
/*, T*/)
1179 unsigned char old_q
, tmp1
;
1182 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1184 R
[iRn1
] |= (unsigned long) T
;
1194 tmp1
= (R
[iRn1
] > tmp0
);
1201 SET_SR_Q ((unsigned char) (tmp1
== 0));
1208 tmp1
= (R
[iRn1
] < tmp0
);
1212 SET_SR_Q ((unsigned char) (tmp1
== 0));
1227 tmp1
= (R
[iRn1
] < tmp0
);
1234 SET_SR_Q ((unsigned char) (tmp1
== 0));
1241 tmp1
= (R
[iRn1
] > tmp0
);
1245 SET_SR_Q ((unsigned char) (tmp1
== 0));
1266 unsigned long RnL
, RnH
;
1267 unsigned long RmL
, RmH
;
1268 unsigned long temp0
, temp1
, temp2
, temp3
;
1269 unsigned long Res2
, Res1
, Res0
;
1272 RnH
= (rn
>> 16) & 0xffff;
1274 RmH
= (rm
>> 16) & 0xffff;
1280 Res1
= temp1
+ temp2
;
1283 temp1
= (Res1
<< 16) & 0xffff0000;
1284 Res0
= temp0
+ temp1
;
1287 Res2
+= ((Res1
>> 16) & 0xffff) + temp3
;
1291 if (rn
& 0x80000000)
1293 if (rm
& 0x80000000)
1302 macw (regs
, memory
, n
, m
, endianw
)
1304 unsigned char *memory
;
1309 long prod
, macl
, sum
;
1311 tempm
=RSWAT(regs
[m
]); regs
[m
]+=2;
1312 tempn
=RSWAT(regs
[n
]); regs
[n
]+=2;
1315 prod
= (long)(short) tempm
* (long)(short) tempn
;
1319 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1321 /* MACH's lsb is a sticky overflow bit. */
1323 /* Store the smallest negative number in MACL if prod is
1324 negative, and the largest positive number otherwise. */
1325 sum
= 0x7fffffff + (prod
< 0);
1331 /* Add to MACH the sign extended product, and carry from low sum. */
1332 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1333 /* Sign extend at 10:th bit in MACH. */
1334 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1339 static struct loop_bounds
1340 get_loop_bounds (rs
, re
, memory
, mem_end
, maskw
, endianw
)
1342 unsigned char *memory
, *mem_end
;
1345 struct loop_bounds loop
;
1351 loop
.start
= PT2H (RE
- 4);
1352 SKIP_INSN (loop
.start
);
1353 loop
.end
= loop
.start
;
1355 SKIP_INSN (loop
.end
);
1357 SKIP_INSN (loop
.end
);
1358 SKIP_INSN (loop
.end
);
1362 loop
.start
= PT2H (RS
);
1363 loop
.end
= PT2H (RE
- 4);
1364 SKIP_INSN (loop
.end
);
1365 SKIP_INSN (loop
.end
);
1366 SKIP_INSN (loop
.end
);
1367 SKIP_INSN (loop
.end
);
1369 if (loop
.end
>= mem_end
)
1370 loop
.end
= PT2H (0);
1373 loop
.end
= PT2H (0);
1383 /* Set the memory size to the power of two provided. */
1390 saved_state
.asregs
.msize
= 1 << power
;
1392 sim_memory_size
= power
;
1394 if (saved_state
.asregs
.memory
)
1396 free (saved_state
.asregs
.memory
);
1399 saved_state
.asregs
.memory
=
1400 (unsigned char *) calloc (64, saved_state
.asregs
.msize
/ 64);
1402 if (!saved_state
.asregs
.memory
)
1405 "Not enough VM for simulation of %d bytes of RAM\n",
1406 saved_state
.asregs
.msize
);
1408 saved_state
.asregs
.msize
= 1;
1409 saved_state
.asregs
.memory
= (unsigned char *) calloc (1, 1);
1417 int was_dsp
= target_dsp
;
1418 unsigned long mach
= bfd_get_mach (abfd
);
1420 if (mach
== bfd_mach_sh_dsp
|| mach
== bfd_mach_sh3_dsp
)
1422 int ram_area_size
, xram_start
, yram_start
;
1426 if (mach
== bfd_mach_sh_dsp
)
1428 /* SH7410 (orig. sh-sdp):
1429 4KB each for X & Y memory;
1430 On-chip X RAM 0x0800f000-0x0800ffff
1431 On-chip Y RAM 0x0801f000-0x0801ffff */
1432 xram_start
= 0x0800f000;
1433 ram_area_size
= 0x1000;
1435 if (mach
== bfd_mach_sh3_dsp
)
1438 8KB each for X & Y memory;
1439 On-chip X RAM 0x1000e000-0x1000ffff
1440 On-chip Y RAM 0x1001e000-0x1001ffff */
1441 xram_start
= 0x1000e000;
1442 ram_area_size
= 0x2000;
1444 yram_start
= xram_start
+ 0x10000;
1445 new_select
= ~(ram_area_size
- 1);
1446 if (saved_state
.asregs
.xyram_select
!= new_select
)
1448 saved_state
.asregs
.xyram_select
= new_select
;
1449 free (saved_state
.asregs
.xmem
);
1450 free (saved_state
.asregs
.ymem
);
1451 saved_state
.asregs
.xmem
= (unsigned char *) calloc (1, ram_area_size
);
1452 saved_state
.asregs
.ymem
= (unsigned char *) calloc (1, ram_area_size
);
1454 /* Disable use of X / Y mmeory if not allocated. */
1455 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1457 saved_state
.asregs
.xyram_select
= 0;
1458 if (saved_state
.asregs
.xmem
)
1459 free (saved_state
.asregs
.xmem
);
1460 if (saved_state
.asregs
.ymem
)
1461 free (saved_state
.asregs
.ymem
);
1464 saved_state
.asregs
.xram_start
= xram_start
;
1465 saved_state
.asregs
.yram_start
= yram_start
;
1466 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1467 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1472 if (saved_state
.asregs
.xyram_select
)
1474 saved_state
.asregs
.xyram_select
= 0;
1475 free (saved_state
.asregs
.xmem
);
1476 free (saved_state
.asregs
.ymem
);
1480 if (! saved_state
.asregs
.xyram_select
)
1482 saved_state
.asregs
.xram_start
= 1;
1483 saved_state
.asregs
.yram_start
= 1;
1486 if (target_dsp
!= was_dsp
)
1490 for (i
= sizeof sh_dsp_table
- 1; i
>= 0; i
--)
1492 tmp
= sh_jump_table
[0xf000 + i
];
1493 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1494 sh_dsp_table
[i
] = tmp
;
1502 host_little_endian
= 0;
1503 *(char*)&host_little_endian
= 1;
1504 host_little_endian
&= 1;
1506 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1508 sim_size (sim_memory_size
);
1511 if (saved_state
.asregs
.profile
&& !profile_file
)
1513 profile_file
= fopen ("gmon.out", "wb");
1514 /* Seek to where to put the call arc data */
1515 nsamples
= (1 << sim_profile_size
);
1517 fseek (profile_file
, nsamples
* 2 + 12, 0);
1521 fprintf (stderr
, "Can't open gmon.out\n");
1525 saved_state
.asregs
.profile_hist
=
1526 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1539 p
= saved_state
.asregs
.profile_hist
;
1541 maxpc
= (1 << sim_profile_size
);
1543 fseek (profile_file
, 0L, 0);
1544 swapout (minpc
<< PROFILE_SHIFT
);
1545 swapout (maxpc
<< PROFILE_SHIFT
);
1546 swapout (nsamples
* 2 + 12);
1547 for (i
= 0; i
< nsamples
; i
++)
1548 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1562 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1568 raise_exception (SIGINT
);
1573 sim_resume (sd
, step
, siggnal
)
1577 register unsigned char *insn_ptr
;
1578 unsigned char *mem_end
;
1579 struct loop_bounds loop
;
1580 register int cycles
= 0;
1581 register int stalls
= 0;
1582 register int memstalls
= 0;
1583 register int insts
= 0;
1584 register int prevlock
;
1585 register int thislock
;
1586 register unsigned int doprofile
;
1587 register int pollcount
= 0;
1588 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1589 endianb is used less often. */
1590 register int endianw
= global_endianw
;
1592 int tick_start
= get_now ();
1594 void (*prev_fpe
) ();
1596 register unsigned char *jump_table
= sh_jump_table
;
1598 register int *R
= &(saved_state
.asregs
.regs
[0]);
1604 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1605 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1606 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1607 register unsigned char *memory
;
1608 register unsigned int sbit
= ((unsigned int) 1 << 31);
1610 prev
= signal (SIGINT
, control_c
);
1611 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1614 saved_state
.asregs
.exception
= 0;
1616 memory
= saved_state
.asregs
.memory
;
1617 mem_end
= memory
+ saved_state
.asregs
.msize
;
1619 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1620 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1621 CHECK_INSN_PTR (insn_ptr
);
1624 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1626 /*T = GET_SR () & SR_MASK_T;*/
1627 prevlock
= saved_state
.asregs
.prevlock
;
1628 thislock
= saved_state
.asregs
.thislock
;
1629 doprofile
= saved_state
.asregs
.profile
;
1631 /* If profiling not enabled, disable it by asking for
1632 profiles infrequently. */
1637 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1639 if (saved_state
.asregs
.exception
)
1640 /* This can happen if we've already been single-stepping and
1641 encountered a loop end. */
1642 saved_state
.asregs
.insn_end
= insn_ptr
;
1645 saved_state
.asregs
.exception
= SIGTRAP
;
1646 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1650 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1652 register unsigned int iword
= RIAT (insn_ptr
);
1653 register unsigned int ult
;
1654 register unsigned char *nip
= insn_ptr
+ 2;
1666 if (--pollcount
< 0)
1668 pollcount
= POLL_QUIT_INTERVAL
;
1669 if ((*callback
->poll_quit
) != NULL
1670 && (*callback
->poll_quit
) (callback
))
1677 prevlock
= thislock
;
1681 if (cycles
>= doprofile
)
1684 saved_state
.asregs
.cycles
+= doprofile
;
1685 cycles
-= doprofile
;
1686 if (saved_state
.asregs
.profile_hist
)
1688 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1691 int i
= saved_state
.asregs
.profile_hist
[n
];
1693 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1700 if (saved_state
.asregs
.insn_end
== loop
.end
)
1702 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1704 insn_ptr
= loop
.start
;
1707 saved_state
.asregs
.insn_end
= mem_end
;
1708 loop
.end
= PT2H (0);
1713 if (saved_state
.asregs
.exception
== SIGILL
1714 || saved_state
.asregs
.exception
== SIGBUS
)
1718 /* Check for SIGBUS due to insn fetch. */
1719 else if (! saved_state
.asregs
.exception
)
1720 saved_state
.asregs
.exception
== SIGBUS
;
1722 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1723 saved_state
.asregs
.cycles
+= cycles
;
1724 saved_state
.asregs
.stalls
+= stalls
;
1725 saved_state
.asregs
.memstalls
+= memstalls
;
1726 saved_state
.asregs
.insts
+= insts
;
1727 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1729 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1732 saved_state
.asregs
.prevlock
= prevlock
;
1733 saved_state
.asregs
.thislock
= thislock
;
1740 signal (SIGFPE
, prev_fpe
);
1741 signal (SIGINT
, prev
);
1745 sim_write (sd
, addr
, buffer
, size
)
1748 unsigned char *buffer
;
1755 for (i
= 0; i
< size
; i
++)
1757 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1763 sim_read (sd
, addr
, buffer
, size
)
1766 unsigned char *buffer
;
1773 for (i
= 0; i
< size
; i
++)
1775 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1781 sim_store_register (sd
, rn
, memory
, length
)
1784 unsigned char *memory
;
1790 val
= swap (* (int *)memory
);
1793 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
1794 case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
1795 saved_state
.asregs
.regs
[rn
] = val
;
1798 saved_state
.asregs
.pc
= val
;
1857 else case 35: case 36: case 37: case 38: case 39:
1858 SET_FI (rn
- 25, val
);
1866 /* The rn_bank idiosyncracies are not due to hardware differences, but to
1867 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
1874 else case 45: case 46: case 47: case 48: case 49: case 50:
1876 Rn_BANK (rn
- 43) = val
;
1878 saved_state
.asregs
.regs
[rn
- 43] = val
;
1880 case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1881 if (target_dsp
|| ! SR_MD
|| ! SR_RB
)
1882 SET_Rn_BANK (rn
- 51, val
);
1884 saved_state
.asregs
.regs
[rn
- 51] = val
;
1893 sim_fetch_register (sd
, rn
, memory
, length
)
1896 unsigned char *memory
;
1904 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
1905 case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
1906 val
= saved_state
.asregs
.regs
[rn
];
1909 val
= saved_state
.asregs
.pc
;
1936 val
= target_dsp
? SEXT (A0G
) : FI (0);
1939 val
= target_dsp
? A0
: FI (1);
1942 val
= target_dsp
? SEXT (A1G
) : FI (2);
1945 val
= target_dsp
? A1
: FI (3);
1948 val
= target_dsp
? M0
: FI (4);
1951 val
= target_dsp
? M1
: FI (5);
1954 val
= target_dsp
? X0
: FI (6);
1957 val
= target_dsp
? X1
: FI (7);
1960 val
= target_dsp
? Y0
: FI (8);
1963 val
= target_dsp
? Y1
: FI (9);
1965 case 35: case 36: case 37: case 38: case 39:
1969 val
= target_dsp
? MOD
: FI (15);
1977 /* The rn_bank idiosyncracies are not due to hardware differences, but to
1978 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
1985 else case 45: case 46: case 47: case 48: case 49: case 50:
1986 val
= (SR_MD
&& SR_RB
1988 : saved_state
.asregs
.regs
[rn
- 43]);
1990 case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1991 val
= (target_dsp
|| ! SR_MD
|| ! SR_RB
1993 : saved_state
.asregs
.regs
[rn
- 51]);
1998 * (int *) memory
= swap (val
);
2010 sim_stop_reason (sd
, reason
, sigrc
)
2012 enum sim_stop
*reason
;
2015 /* The SH simulator uses SIGQUIT to indicate that the program has
2016 exited, so we must check for it here and translate it to exit. */
2017 if (saved_state
.asregs
.exception
== SIGQUIT
)
2019 *reason
= sim_exited
;
2020 *sigrc
= saved_state
.asregs
.regs
[5];
2024 *reason
= sim_stopped
;
2025 *sigrc
= saved_state
.asregs
.exception
;
2030 sim_info (sd
, verbose
)
2034 double timetaken
= (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2035 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2037 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
2038 saved_state
.asregs
.insts
);
2039 callback
->printf_filtered (callback
, "# cycles %10d\n",
2040 saved_state
.asregs
.cycles
);
2041 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
2042 saved_state
.asregs
.stalls
);
2043 callback
->printf_filtered (callback
, "# misaligned load/store %10d\n",
2044 saved_state
.asregs
.memstalls
);
2045 callback
->printf_filtered (callback
, "# real time taken %10.4f\n",
2047 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
2049 callback
->printf_filtered (callback
, "# profiling size %10d\n",
2051 callback
->printf_filtered (callback
, "# profiling frequency %10d\n",
2052 saved_state
.asregs
.profile
);
2053 callback
->printf_filtered (callback
, "# profile maxpc %10x\n",
2054 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2058 callback
->printf_filtered (callback
, "# cycles/second %10d\n",
2059 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2060 callback
->printf_filtered (callback
, "# simulation ratio %10.4f\n",
2061 virttime
/ timetaken
);
2069 saved_state
.asregs
.profile
= n
;
2073 sim_set_profile_size (n
)
2076 sim_profile_size
= n
;
2080 sim_open (kind
, cb
, abfd
, argv
)
2101 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2103 if (strcmp (*p
, "-E") == 0)
2108 /* FIXME: This doesn't use stderr, but then the rest of the
2109 file doesn't either. */
2110 callback
->printf_filtered (callback
, "Missing argument to `-E'.\n");
2113 target_little_endian
= strcmp (*p
, "big") != 0;
2116 else if (isdigit (**p
))
2117 parse_and_set_memory_size (*p
);
2120 if (abfd
!= NULL
&& ! endian_set
)
2121 target_little_endian
= ! bfd_big_endian (abfd
);
2126 for (i
= 4; (i
-= 2) >= 0; )
2127 mem_word
.s
[i
>> 1] = i
;
2128 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2130 for (i
= 4; --i
>= 0; )
2132 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2134 /* fudge our descriptor for now */
2135 return (SIM_DESC
) 1;
2139 parse_and_set_memory_size (str
)
2144 n
= strtol (str
, NULL
, 10);
2145 if (n
> 0 && n
<= 24)
2146 sim_memory_size
= n
;
2148 callback
->printf_filtered (callback
, "Bad memory size %d; must be 1 to 24, inclusive\n", n
);
2152 sim_close (sd
, quitting
)
2160 sim_load (sd
, prog
, abfd
, from_tty
)
2166 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
2169 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
2170 sim_kind
== SIM_OPEN_DEBUG
,
2172 if (prog_bfd
== NULL
)
2175 bfd_close (prog_bfd
);
2180 sim_create_inferior (sd
, prog_bfd
, argv
, env
)
2182 struct _bfd
*prog_bfd
;
2186 /* Clear the registers. */
2187 memset (&saved_state
, 0,
2188 (char*)&saved_state
.asregs
.end_of_registers
- (char*)&saved_state
);
2191 if (prog_bfd
!= NULL
)
2192 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2194 /* Record the program's arguments. */
2201 sim_do_command (sd
, cmd
)
2205 char *sms_cmd
= "set-memory-size";
2208 if (cmd
== NULL
|| *cmd
== '\0')
2213 cmdsize
= strlen (sms_cmd
);
2214 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2216 parse_and_set_memory_size (cmd
+ cmdsize
+ 1);
2218 else if (strcmp (cmd
, "help") == 0)
2220 (callback
->printf_filtered
) (callback
, "List of SH simulator commands:\n\n");
2221 (callback
->printf_filtered
) (callback
, "set-memory-size <n> -- Set the number of address bits to use\n");
2222 (callback
->printf_filtered
) (callback
, "\n");
2226 (callback
->printf_filtered
) (callback
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);
2231 sim_set_callbacks (p
)