sim/sh/interp.c

   1 /* Simulator for the Hitachi SH architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 #include <signal.h>
  22 #include "sysdep.h"
  23 #include "bfd.h"
  24 #include "remote-sim.h"
  25
  26 /* This file is local - if newlib changes, then so should this.  */
  27 #include "syscall.h"
  28
  29 /* start-sanitize-sh3e */
  30 #include <math.h>
  31 /* end-sanitize-sh3e */
  32
  33 #ifndef SIGBUS
  34 #define SIGBUS SIGSEGV
  35 #endif
  36
  37 #ifndef SIGQUIT
  38 #define SIGQUIT SIGTERM
  39 #endif
  40
  41 #define O_RECOMPILE 85
  42 #define DEFINE_TABLE
  43 #define DISASSEMBLER_TABLE
  44
  45
  46
  47 #define SBIT(x) ((x)&sbit)
  48 #define R0      saved_state.asregs.regs[0]
  49 #define Rn      saved_state.asregs.regs[n]
  50 #define Rm      saved_state.asregs.regs[m]
  51 #define UR0     (unsigned int)(saved_state.asregs.regs[0])
  52 #define UR      (unsigned int)R
  53 #define UR      (unsigned int)R
  54 #define SR0     saved_state.asregs.regs[0]
  55 #define GBR     saved_state.asregs.gbr
  56 #define VBR     saved_state.asregs.vbr
  57 #define MACH    saved_state.asregs.mach
  58 #define MACL    saved_state.asregs.macl
  59 #define M       saved_state.asregs.sr.bits.m
  60 #define Q       saved_state.asregs.sr.bits.q
  61 #define S       saved_state.asregs.sr.bits.s
  62 /* start-sanitize-sh3e */
  63 #define FPSCR   saved_state.asregs.fpscr
  64 #define FPUL    saved_state.asregs.fpul
  65 /* end-sanitize-sh3e */
  66
  67 #define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
  68 #define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
  69
  70 #define PC pc
  71 #define C cycles
  72
  73 int
  74 fail ()
  75 {
  76   abort ();
  77 }
  78
  79 #define BUSERROR(addr, mask) \
  80   if (addr & ~mask)  { saved_state.asregs.exception = SIGBUS;}
  81
  82 /* Define this to enable register lifetime checking.
  83    The compiler generates "add #0,rn" insns to mark registers as invalid,
  84    the simulator uses this info to call fail if it finds a ref to an invalid
  85    register before a def
  86
  87    #define PARANOID
  88 */
  89
  90 #ifdef PARANOID
  91 int valid[16];
  92 #define CREF(x)  if(!valid[x]) fail();
  93 #define CDEF(x)  valid[x] = 1;
  94 #define UNDEF(x) valid[x] = 0;
  95 #else
  96 #define CREF(x)
  97 #define CDEF(x)
  98 #define UNDEF(x)
  99 #endif
 100
 101 static void parse_and_set_memory_size PARAMS ((char *str));
 102
 103 static int IOMEM PARAMS ((int addr, int write, int value));
 104
 105 /* These variables are at file scope so that functions other than
 106    sim_resume can use the fetch/store macros */
 107
 108 static int  little_endian;
 109
 110 #if 1
 111 static int maskl = ~0;
 112 static int maskw = ~0;
 113 #endif
 114 typedef union
 115 {
 116
 117   struct
 118   {
 119
 120     int regs[16];
 121     int pc;
 122     int pr;
 123
 124     int gbr;
 125     int vbr;
 126     int mach;
 127     int macl;
 128
 129     union
 130       {
 131         struct
 132           {
 133             unsigned int d0:22;
 134             unsigned int m:1;
 135             unsigned int q:1;
 136             unsigned int i:4;
 137             unsigned int d1:2;
 138             unsigned int s:1;
 139             unsigned int t:1;
 140           }
 141         bits;
 142         int word;
 143       }
 144     sr;
 145     int ticks;
 146     int stalls;
 147     int cycles;
 148     int insts;
 149
 150
 151     int prevlock;
 152     int thislock;
 153 /* start-sanitize-sh3e */
 154     float fregs[16];
 155     float fpscr;
 156     int fpul;
 157 /* end-sanitize-sh3e */
 158     int exception;
 159     int msize;
 160 #define PROFILE_FREQ 1
 161 #define PROFILE_SHIFT 2
 162     int profile;
 163     unsigned short *profile_hist;
 164     unsigned char *memory;
 165   }
 166   asregs;
 167   int asints[28];
 168 } saved_state_type;
 169 saved_state_type saved_state;
 170
 171 static void INLINE
 172 wlat_little (memory, x, value, maskl)
 173      unsigned char *memory;
 174 {
 175   int v = value;
 176   unsigned char *p = memory + ((x) & maskl);
 177   BUSERROR(x, maskl);
 178   p[3] = v >> 24;
 179   p[2] = v >> 16;
 180   p[1] = v >> 8;
 181   p[0] = v;
 182 }
 183
 184 static void INLINE
 185 wwat_little (memory, x, value, maskw)
 186      unsigned char *memory;
 187 {
 188   int v = value;
 189   unsigned char *p = memory + ((x) & maskw);
 190   BUSERROR(x, maskw);
 191
 192   p[1] = v >> 8;
 193   p[0] = v;
 194 }
 195
 196
 197 static void INLINE
 198 wbat_any (memory, x, value, maskb)
 199      unsigned char *memory;
 200 {
 201   unsigned char *p = memory + (x & maskb);
 202   if (x > 0x5000000)
 203     IOMEM (x, 1, value);
 204   BUSERROR(x, maskb);
 205
 206   p[0] = value;
 207 }
 208
 209
 210
 211 static void INLINE
 212 wlat_big (memory, x, value, maskl)
 213      unsigned char *memory;
 214 {
 215   int v = value;
 216   unsigned char *p = memory + ((x) & maskl);
 217   BUSERROR(x, maskl);
 218
 219   p[0] = v >> 24;
 220   p[1] = v >> 16;
 221   p[2] = v >> 8;
 222   p[3] = v;
 223 }
 224
 225 static void INLINE
 226 wwat_big (memory, x, value, maskw)
 227      unsigned char *memory;
 228 {
 229   int v = value;
 230   unsigned char *p = memory + ((x) & maskw);
 231   BUSERROR(x, maskw);
 232
 233   p[0] = v >> 8;
 234   p[1] = v;
 235 }
 236
 237
 238 static void INLINE
 239 wbat_big (memory, x, value, maskb)
 240      unsigned char *memory;
 241 {
 242   unsigned char *p = memory + (x & maskb);
 243   BUSERROR(x, maskb);
 244
 245   if (x > 0x5000000)
 246     IOMEM (x, 1, value);
 247   p[0] = value;
 248 }
 249
 250
 251
 252 /* Read functions */
 253 static int INLINE
 254 rlat_little (memory, x, maskl)
 255      unsigned char *memory;
 256 {
 257   unsigned char *p = memory + ((x) & maskl);
 258   BUSERROR(x, maskl);
 259
 260   return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
 261
 262 }
 263
 264 static int INLINE
 265 rwat_little (memory, x, maskw)
 266      unsigned char *memory;
 267 {
 268   unsigned char *p = memory + ((x) & maskw);
 269   BUSERROR(x, maskw);
 270
 271   return (p[1] << 8) | p[0];
 272 }
 273
 274 static int INLINE
 275 rbat_any (memory, x, maskb)
 276      unsigned char *memory;
 277 {
 278   unsigned char *p = memory + ((x) & maskb);
 279   BUSERROR(x, maskb);
 280
 281   return p[0];
 282 }
 283
 284 static int INLINE
 285 rlat_big (memory, x, maskl)
 286      unsigned char *memory;
 287 {
 288   unsigned char *p = memory + ((x) & maskl);
 289   BUSERROR(x, maskl);
 290
 291   return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
 292
 293 }
 294
 295 static int INLINE
 296 rwat_big (memory, x, maskw)
 297      unsigned char *memory;
 298 {
 299   unsigned char *p = memory + ((x) & maskw);
 300   BUSERROR(x, maskw);
 301
 302   return (p[0] << 8) | p[1];
 303 }
 304
 305
 306 #define RWAT(x)         (little_endian ? rwat_little(memory, x, maskw): rwat_big(memory, x, maskw))
 307 #define RLAT(x)         (little_endian ? rlat_little(memory, x, maskl): rlat_big(memory, x, maskl))
 308 #define RBAT(x)         (rbat_any (memory, x, maskb))
 309 #define WWAT(x,v)       (little_endian ? wwat_little(memory, x, v, maskw): wwat_big(memory, x, v, maskw))
 310 #define WLAT(x,v)       (little_endian ? wlat_little(memory, x, v, maskl): wlat_big(memory, x, v, maskl))
 311 #define WBAT(x,v)       (wbat_any (memory, x, v, maskb))
 312
 313 #define RUWAT(x)  (RWAT(x) & 0xffff)
 314 #define RSWAT(x)  ((short)(RWAT(x)))
 315 #define RSBAT(x)  (SEXT(RBAT(x)))
 316
 317 #define SEXT(x)         (((x&0xff) ^ (~0x7f))+0x80)
 318 #define SEXTW(y)        ((int)((short)y))
 319
 320 #define SL(TEMPPC)      iword= RUWAT(TEMPPC); goto top;
 321
 322
 323 int empty[16];
 324
 325 #define L(x)   thislock = x;
 326 #define TL(x)  if ((x) == prevlock) stalls++;
 327 #define TB(x,y)  if ((x) == prevlock || (y)==prevlock) stalls++;
 328
 329 #if defined(__GO32__) || defined(WIN32)
 330 int sim_memory_size = 19;
 331 #else
 332 int sim_memory_size = 24;
 333 #endif
 334
 335 static int sim_profile_size = 17;
 336 static int nsamples;
 337
 338 #undef TB
 339 #define TB(x,y)
 340
 341 #define SMR1 (0x05FFFEC8)       /* Channel 1  serial mode register */
 342 #define BRR1 (0x05FFFEC9)       /* Channel 1  bit rate register */
 343 #define SCR1 (0x05FFFECA)       /* Channel 1  serial control register */
 344 #define TDR1 (0x05FFFECB)       /* Channel 1  transmit data register */
 345 #define SSR1 (0x05FFFECC)       /* Channel 1  serial status register */
 346 #define RDR1 (0x05FFFECD)       /* Channel 1  receive data register */
 347
 348 #define SCI_RDRF         0x40   /* Recieve data register full */
 349 #define SCI_TDRE        0x80    /* Transmit data register empty */
 350
 351 static int
 352 IOMEM (addr, write, value)
 353      int addr;
 354      int write;
 355      int value;
 356 {
 357   static int io;
 358   static char ssr1;
 359   int x;
 360   static char lastchar;
 361
 362   if (write)
 363     {
 364       switch (addr)
 365         {
 366         case TDR1:
 367           if (value != '\r')
 368             {
 369               putchar (value);
 370               fflush (stdout);
 371             }
 372           break;
 373         }
 374     }
 375   else
 376     {
 377       switch (addr)
 378         {
 379         case RDR1:
 380           return getchar ();
 381         }
 382     }
 383 }
 384
 385
 386
 387 static int
 388 get_now ()
 389 {
 390   return time ((long *) 0);
 391 }
 392
 393 static int
 394 now_persec ()
 395 {
 396   return 1;
 397 }
 398
 399
 400
 401 static FILE *profile_file;
 402
 403 static void
 404 swap (memory, n)
 405      unsigned char *memory;
 406      int n;
 407 {
 408   WLAT (0, n);
 409 }
 410 static void
 411 swap16 (memory, n)
 412      unsigned char *memory;
 413      int n;
 414 {
 415   WWAT (0, n);
 416 }
 417
 418 static void
 419 swapout (n)
 420      int n;
 421 {
 422   if (profile_file)
 423     {
 424       char b[4];
 425       swap (b, n);
 426       fwrite (b, 4, 1, profile_file);
 427     }
 428 }
 429
 430 static void
 431 swapout16 (n)
 432      int n;
 433 {
 434   char b[4];
 435   swap16 (b, n);
 436   fwrite (b, 2, 1, profile_file);
 437 }
 438
 439
 440 /* Turn a pointer in a register into a pointer into real memory. */
 441
 442 static char *
 443 ptr (x)
 444      int x;
 445 {
 446   return (char *) (x + saved_state.asregs.memory);
 447 }
 448
 449
 450 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
 451 static void
 452 trap (i, regs, memory, maskl, maskw, little_endian)
 453      int i;
 454      int *regs;
 455      unsigned char *memory;
 456 {
 457   switch (i)
 458     {
 459     case 1:
 460       printf ("%c", regs[0]);
 461       break;
 462     case 2:
 463       saved_state.asregs.exception = SIGQUIT;
 464       break;
 465     case 3:                     /* FIXME: for backwards compat, should be removed */
 466     case 34:
 467       {
 468         extern int errno;
 469         int perrno = errno;
 470         errno = 0;
 471
 472         switch (regs[4])
 473           {
 474
 475 #if !defined(__GO32__) && !defined(WIN32)
 476           case SYS_fork:
 477             regs[0] = fork ();
 478             break;
 479           case SYS_execve:
 480             regs[0] = execve (ptr (regs[5]), ptr (regs[6]), ptr (regs[7]));
 481             break;
 482           case SYS_execv:
 483             regs[0] = execve (ptr (regs[5]), ptr (regs[6]), 0);
 484             break;
 485           case SYS_pipe:
 486             {
 487               char *buf;
 488               int host_fd[2];
 489
 490               buf = ptr (regs[5]);
 491
 492               regs[0] = pipe (host_fd);
 493
 494               WLAT (buf, host_fd[0]);
 495               buf += 4;
 496               WLAT (buf, host_fd[1]);
 497             }
 498             break;
 499
 500           case SYS_wait:
 501             regs[0] = wait (ptr (regs[5]));
 502             break;
 503 #endif
 504
 505           case SYS_read:
 506             regs[0] = read (regs[5], ptr (regs[6]), regs[7]);
 507             break;
 508           case SYS_write:
 509             regs[0] = write (regs[5], ptr (regs[6]), regs[7]);
 510             break;
 511           case SYS_lseek:
 512             regs[0] = lseek (regs[5], regs[6], regs[7]);
 513             break;
 514           case SYS_close:
 515             regs[0] = close (regs[5]);
 516             break;
 517           case SYS_open:
 518             regs[0] = open (ptr (regs[5]), regs[6]);
 519             break;
 520           case SYS_exit:
 521             /* EXIT - caller can look in r5 to work out the
 522                reason */
 523             saved_state.asregs.exception = SIGQUIT;
 524             break;
 525
 526           case SYS_stat:        /* added at hmsi */
 527             /* stat system call */
 528             {
 529               struct stat host_stat;
 530               char *buf;
 531
 532               regs[0] = stat (ptr (regs[5]), &host_stat);
 533
 534               buf = ptr (regs[6]);
 535
 536               WWAT (buf, host_stat.st_dev);
 537               buf += 2;
 538               WWAT (buf, host_stat.st_ino);
 539               buf += 2;
 540               WLAT (buf, host_stat.st_mode);
 541               buf += 4;
 542               WWAT (buf, host_stat.st_nlink);
 543               buf += 2;
 544               WWAT (buf, host_stat.st_uid);
 545               buf += 2;
 546               WWAT (buf, host_stat.st_gid);
 547               buf += 2;
 548               WWAT (buf, host_stat.st_rdev);
 549               buf += 2;
 550               WLAT (buf, host_stat.st_size);
 551               buf += 4;
 552               WLAT (buf, host_stat.st_atime);
 553               buf += 4;
 554               WLAT (buf, 0);
 555               buf += 4;
 556               WLAT (buf, host_stat.st_mtime);
 557               buf += 4;
 558               WLAT (buf, 0);
 559               buf += 4;
 560               WLAT (buf, host_stat.st_ctime);
 561               buf += 4;
 562               WLAT (buf, 0);
 563               buf += 4;
 564               WLAT (buf, 0);
 565               buf += 4;
 566               WLAT (buf, 0);
 567               buf += 4;
 568             }
 569             break;
 570
 571           case SYS_chown:
 572             regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
 573             break;
 574           case SYS_chmod:
 575             regs[0] = chmod (ptr (regs[5]), regs[6]);
 576             break;
 577           case SYS_utime:
 578             regs[0] = utime (ptr (regs[5]), ptr (regs[6]));
 579             break;
 580           default:
 581             abort ();
 582           }
 583         regs[1] = errno;
 584         errno = perrno;
 585       }
 586       break;
 587
 588     case 0xc3:
 589     case 255:
 590       saved_state.asregs.exception = SIGTRAP;
 591       break;
 592     }
 593
 594 }
 595 void
 596 control_c (sig, code, scp, addr)
 597      int sig;
 598      int code;
 599      char *scp;
 600      char *addr;
 601 {
 602   saved_state.asregs.exception = SIGINT;
 603 }
 604
 605
 606 static int
 607 div1 (R, iRn2, iRn1, T)
 608      int *R;
 609      int iRn1;
 610      int iRn2;
 611      int T;
 612 {
 613   unsigned long tmp0;
 614   unsigned char old_q, tmp1;
 615
 616   old_q = Q;
 617   Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0);
 618   R[iRn1] <<= 1;
 619   R[iRn1] |= (unsigned long) T;
 620
 621   switch (old_q)
 622     {
 623     case 0:
 624       switch (M)
 625         {
 626         case 0:
 627           tmp0 = R[iRn1];
 628           R[iRn1] -= R[iRn2];
 629           tmp1 = (R[iRn1] > tmp0);
 630           switch (Q)
 631             {
 632             case 0:
 633               Q = tmp1;
 634               break;
 635             case 1:
 636               Q = (unsigned char) (tmp1 == 0);
 637               break;
 638             }
 639           break;
 640         case 1:
 641           tmp0 = R[iRn1];
 642           R[iRn1] += R[iRn2];
 643           tmp1 = (R[iRn1] < tmp0);
 644           switch (Q)
 645             {
 646             case 0:
 647               Q = (unsigned char) (tmp1 == 0);
 648               break;
 649             case 1:
 650               Q = tmp1;
 651               break;
 652             }
 653           break;
 654         }
 655       break;
 656     case 1:
 657       switch (M)
 658         {
 659         case 0:
 660           tmp0 = R[iRn1];
 661           R[iRn1] += R[iRn2];
 662           tmp1 = (R[iRn1] < tmp0);
 663           switch (Q)
 664             {
 665             case 0:
 666               Q = tmp1;
 667               break;
 668             case 1:
 669               Q = (unsigned char) (tmp1 == 0);
 670               break;
 671             }
 672           break;
 673         case 1:
 674           tmp0 = R[iRn1];
 675           R[iRn1] -= R[iRn2];
 676           tmp1 = (R[iRn1] > tmp0);
 677           switch (Q)
 678             {
 679             case 0:
 680               Q = (unsigned char) (tmp1 == 0);
 681               break;
 682             case 1:
 683               Q = tmp1;
 684               break;
 685             }
 686           break;
 687         }
 688       break;
 689     }
 690   T = (Q == M);
 691   return T;
 692 }
 693
 694
 695 static void
 696 dmul (sign, rm, rn)
 697      int sign;
 698      unsigned int rm;
 699      unsigned int rn;
 700 {
 701   unsigned long RnL, RnH;
 702   unsigned long RmL, RmH;
 703   unsigned long temp0, temp1, temp2, temp3;
 704   unsigned long Res2, Res1, Res0;
 705
 706   RnL = rn & 0xffff;
 707   RnH = (rn >> 16) & 0xffff;
 708   RmL = rm & 0xffff;
 709   RmH = (rm >> 16) & 0xffff;
 710   temp0 = RmL * RnL;
 711   temp1 = RmH * RnL;
 712   temp2 = RmL * RnH;
 713   temp3 = RmH * RnH;
 714   Res2 = 0;
 715   Res1 = temp1 + temp2;
 716   if (Res1 < temp1)
 717     Res2 += 0x00010000;
 718   temp1 = (Res1 << 16) & 0xffff0000;
 719   Res0 = temp0 + temp1;
 720   if (Res0 < temp0)
 721     Res2 += 1;
 722   Res2 += ((Res1 >> 16) & 0xffff) + temp3;
 723
 724   if (sign)
 725     {
 726       if (rn & 0x80000000)
 727         Res2 -= rm;
 728       if (rm & 0x80000000)
 729         Res2 -= rn;
 730     }
 731
 732   MACH = Res2;
 733   MACL = Res0;
 734 }
 735
 736 static void
 737 macw (regs, memory, n, m)
 738      int *regs;
 739      unsigned char *memory;
 740      int m, n;
 741 {
 742   long tempm, tempn;
 743   long prod, macl, sum;
 744
 745   tempm=RSWAT(regs[m]); regs[m]+=2;
 746   tempn=RSWAT(regs[n]); regs[n]+=2;
 747
 748   macl = MACL;
 749   prod = (long)(short) tempm * (long)(short) tempn;
 750   sum = prod + macl;
 751   if (S)
 752     {
 753       if ((~(prod ^ macl) & (sum ^ prod)) < 0)
 754         {
 755           /* MACH's lsb is a sticky overflow bit.  */
 756           MACH |= 1;
 757           /* Store the smallest negative number in MACL if prod is
 758              negative, and the largest positive number otherwise.  */
 759           sum = 0x7fffffff + (prod < 0);
 760         }
 761     }
 762   else
 763     {
 764       long mach;
 765       /* Add to MACH the sign extended product, and carry from low sum.  */
 766       mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
 767       /* Sign extend at 10:th bit in MACH.  */
 768       MACH = (mach & 0x1ff) | -(mach & 0x200);
 769     }
 770   MACL = sum;
 771 }
 772
 773 /* Set the memory size to the power of two provided. */
 774
 775 void
 776 sim_size (power)
 777      int power;
 778
 779 {
 780   saved_state.asregs.msize = 1 << power;
 781
 782   sim_memory_size = power;
 783
 784
 785   if (saved_state.asregs.memory)
 786     {
 787       free (saved_state.asregs.memory);
 788     }
 789
 790   saved_state.asregs.memory =
 791     (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
 792
 793   if (!saved_state.asregs.memory)
 794     {
 795       fprintf (stderr,
 796                "Not enough VM for simulation of %d bytes of RAM\n",
 797                saved_state.asregs.msize);
 798
 799       saved_state.asregs.msize = 1;
 800       saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
 801     }
 802 }
 803
 804
 805 int target_byte_order;
 806
 807 static void
 808 set_static_little_endian(x)
 809 int x;
 810 {
 811   little_endian = x;
 812 }
 813
 814 static
 815 void
 816 init_pointers ()
 817 {
 818   register int little_endian = target_byte_order == 1234;
 819   set_static_little_endian (little_endian);
 820   if (saved_state.asregs.msize != 1 << sim_memory_size)
 821     {
 822       sim_size (sim_memory_size);
 823     }
 824
 825   if (saved_state.asregs.profile && !profile_file)
 826     {
 827       profile_file = fopen ("gmon.out", "wb");
 828       /* Seek to where to put the call arc data */
 829       nsamples = (1 << sim_profile_size);
 830
 831       fseek (profile_file, nsamples * 2 + 12, 0);
 832
 833       if (!profile_file)
 834         {
 835           fprintf (stderr, "Can't open gmon.out\n");
 836         }
 837       else
 838         {
 839           saved_state.asregs.profile_hist =
 840             (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
 841         }
 842     }
 843 }
 844
 845 static void
 846 dump_profile ()
 847 {
 848   unsigned int minpc;
 849   unsigned int maxpc;
 850   unsigned short *p;
 851
 852   int thisshift;
 853
 854   unsigned short *first;
 855
 856   int i;
 857   p = saved_state.asregs.profile_hist;
 858   minpc = 0;
 859   maxpc = (1 << sim_profile_size);
 860
 861   fseek (profile_file, 0L, 0);
 862   swapout (minpc << PROFILE_SHIFT);
 863   swapout (maxpc << PROFILE_SHIFT);
 864   swapout (nsamples * 2 + 12);
 865   for (i = 0; i < nsamples; i++)
 866     swapout16 (saved_state.asregs.profile_hist[i]);
 867
 868 }
 869
 870 static int
 871 gotcall (from, to)
 872      int from;
 873      int to;
 874 {
 875   swapout (from);
 876   swapout (to);
 877   swapout (1);
 878 }
 879
 880 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
 881
 882
 883 void
 884 sim_resume (step, siggnal)
 885      int step, siggnal;
 886 {
 887   register unsigned int pc;
 888   register int cycles = 0;
 889   register int stalls = 0;
 890   register int insts = 0;
 891   register int prevlock;
 892   register int thislock;
 893   register unsigned int doprofile;
 894 #if defined(__GO32__) || defined(WIN32)
 895   register int pollcount = 0;
 896 #endif
 897   register int little_endian = target_byte_order == 1234;
 898
 899
 900   int tick_start = get_now ();
 901   void (*prev) ();
 902   extern unsigned char sh_jump_table0[];
 903
 904   register unsigned char *jump_table = sh_jump_table0;
 905
 906   register int *R = &(saved_state.asregs.regs[0]);
 907 /* start-sanitize-sh3e */
 908   register float *F = &(saved_state.asregs.fregs[0]);
 909 /* end-sanitize-sh3e */
 910   register int T;
 911   register int PR;
 912
 913   register int maskb = ((saved_state.asregs.msize - 1) & ~0);
 914   register int maskw = ((saved_state.asregs.msize - 1) & ~1);
 915   register int maskl = ((saved_state.asregs.msize - 1) & ~3);
 916   register unsigned char *memory;
 917   register unsigned int sbit = ((unsigned int) 1 << 31);
 918
 919   prev = signal (SIGINT, control_c);
 920
 921   init_pointers ();
 922
 923   memory = saved_state.asregs.memory;
 924
 925   if (step)
 926     {
 927       saved_state.asregs.exception = SIGTRAP;
 928     }
 929   else
 930     {
 931       saved_state.asregs.exception = 0;
 932     }
 933
 934   pc = saved_state.asregs.pc;
 935   PR = saved_state.asregs.pr;
 936   T = saved_state.asregs.sr.bits.t;
 937   prevlock = saved_state.asregs.prevlock;
 938   thislock = saved_state.asregs.thislock;
 939   doprofile = saved_state.asregs.profile;
 940
 941   /* If profiling not enabled, disable it by asking for
 942      profiles infrequently. */
 943   if (doprofile == 0)
 944     doprofile = ~0;
 945
 946   do
 947     {
 948       register unsigned int iword = RUWAT (pc);
 949       register unsigned int ult;
 950 #ifndef ACE_FAST
 951       insts++;
 952 #endif
 953     top:
 954
 955 #include "code.c"
 956
 957
 958       pc += 2;
 959
 960 #ifdef __GO32__
 961       pollcount++;
 962       if (pollcount > 1000)
 963         {
 964           pollcount = 0;
 965           if (kbhit()) {
 966             int k = getkey();
 967             if (k == 1)
 968               saved_state.asregs.exception = SIGINT;
 969
 970           }
 971         }
 972 #endif
 973 #if defined (WIN32)
 974       pollcount++;
 975       if (pollcount > 1000)
 976         {
 977           pollcount = 0;
 978           if (win32pollquit())
 979             {
 980               control_c();
 981             }
 982         }
 983 #endif
 984
 985 #ifndef ACE_FAST
 986       prevlock = thislock;
 987       thislock = 30;
 988       cycles++;
 989
 990       if (cycles >= doprofile)
 991         {
 992
 993           saved_state.asregs.cycles += doprofile;
 994           cycles -= doprofile;
 995           if (saved_state.asregs.profile_hist)
 996             {
 997               int n = pc >> PROFILE_SHIFT;
 998               if (n < nsamples)
 999                 {
1000                   int i = saved_state.asregs.profile_hist[n];
1001                   if (i < 65000)
1002                     saved_state.asregs.profile_hist[n] = i + 1;
1003                 }
1004
1005             }
1006         }
1007 #endif
1008     }
1009   while (!saved_state.asregs.exception);
1010
1011   if (saved_state.asregs.exception == SIGILL
1012       || saved_state.asregs.exception == SIGBUS)
1013     {
1014       pc -= 2;
1015     }
1016
1017   saved_state.asregs.ticks += get_now () - tick_start;
1018   saved_state.asregs.cycles += cycles;
1019   saved_state.asregs.stalls += stalls;
1020   saved_state.asregs.insts += insts;
1021   saved_state.asregs.pc = pc;
1022   saved_state.asregs.sr.bits.t = T;
1023   saved_state.asregs.pr = PR;
1024
1025   saved_state.asregs.prevlock = prevlock;
1026   saved_state.asregs.thislock = thislock;
1027
1028
1029   if (profile_file)
1030     {
1031       dump_profile ();
1032     }
1033
1034   signal (SIGINT, prev);
1035 }
1036
1037
1038
1039
1040 int
1041 sim_write (addr, buffer, size)
1042      SIM_ADDR addr;
1043      unsigned char *buffer;
1044      int size;
1045 {
1046   int i;
1047   init_pointers ();
1048
1049   for (i = 0; i < size; i++)
1050     {
1051       saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i];
1052     }
1053   return size;
1054 }
1055
1056 int
1057 sim_read (addr, buffer, size)
1058      SIM_ADDR addr;
1059      unsigned char *buffer;
1060      int size;
1061 {
1062   int i;
1063
1064   init_pointers ();
1065
1066   for (i = 0; i < size; i++)
1067     {
1068       buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)];
1069     }
1070   return size;
1071 }
1072
1073
1074 void
1075 sim_store_register (rn, memory)
1076      int rn;
1077      unsigned char *memory;
1078 {
1079   init_pointers();
1080   saved_state.asregs.regs[rn]=RLAT(0);
1081 }
1082
1083 void
1084 sim_fetch_register (rn, memory)
1085      int rn;
1086      unsigned char *memory;
1087 {
1088   init_pointers();
1089   WLAT (0, saved_state.asregs.regs[rn]);
1090 }
1091
1092
1093 int
1094 sim_trace ()
1095 {
1096   return 0;
1097 }
1098
1099 void
1100 sim_stop_reason (reason, sigrc)
1101      enum sim_stop *reason;
1102      int *sigrc;
1103 {
1104   *reason = sim_stopped;
1105   *sigrc = saved_state.asregs.exception;
1106 }
1107
1108
1109 void
1110 sim_info (verbose)
1111      int verbose;
1112 {
1113   double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
1114   double virttime = saved_state.asregs.cycles / 36.0e6;
1115
1116   printf_filtered ("\n\n# instructions executed  %10d\n", saved_state.asregs.insts);
1117   printf_filtered ("# cycles                 %10d\n", saved_state.asregs.cycles);
1118   printf_filtered ("# pipeline stalls        %10d\n", saved_state.asregs.stalls);
1119   printf_filtered ("# real time taken        %10.4f\n", timetaken);
1120   printf_filtered ("# virtual time taken     %10.4f\n", virttime);
1121   printf_filtered ("# profiling size         %10d\n", sim_profile_size);
1122   printf_filtered ("# profiling frequency    %10d\n", saved_state.asregs.profile);
1123   printf_filtered ("# profile maxpc          %10x\n", (1 << sim_profile_size) << PROFILE_SHIFT);
1124
1125   if (timetaken != 0)
1126     {
1127       printf_filtered ("# cycles/second          %10d\n", (int) (saved_state.asregs.cycles / timetaken));
1128       printf_filtered ("# simulation ratio       %10.4f\n", virttime / timetaken);
1129     }
1130 }
1131
1132
1133 void
1134 sim_set_profile (n)
1135      int n;
1136 {
1137   saved_state.asregs.profile = n;
1138 }
1139
1140 void
1141 sim_set_profile_size (n)
1142      int n;
1143 {
1144   sim_profile_size = n;
1145 }
1146
1147
1148 void
1149 sim_open (args)
1150      char *args;
1151 {
1152   int n;
1153
1154   if (args != NULL)
1155     {
1156       parse_and_set_memory_size (args);
1157     }
1158 }
1159
1160 static void
1161 parse_and_set_memory_size (str)
1162      char *str;
1163 {
1164   int n;
1165
1166   n = strtol (str, NULL, 10);
1167   if (n > 0 && n <= 24)
1168     sim_memory_size = n;
1169   else
1170     printf_filtered ("Bad memory size %d; must be 1 to 24, inclusive\n", n);
1171 }
1172
1173 void
1174 sim_close (quitting)
1175      int quitting;
1176 {
1177   /* nothing to do */
1178 }
1179
1180 int
1181 sim_load (prog, from_tty)
1182      char *prog;
1183      int from_tty;
1184 {
1185   /* Return nonzero so GDB will handle it.  */
1186   return 1;
1187 }
1188
1189 void
1190 sim_create_inferior (start_address, argv, env)
1191      SIM_ADDR start_address;
1192      char **argv;
1193      char **env;
1194 {
1195   saved_state.asregs.pc = start_address;
1196 }
1197
1198 void
1199 sim_kill ()
1200 {
1201   /* nothing to do */
1202 }
1203
1204 void
1205 sim_do_command (cmd)
1206      char *cmd;
1207 {
1208   int n;
1209   char *sms_cmd = "set-memory-size";
1210
1211   if (strncmp (cmd, sms_cmd, strlen (sms_cmd)) == 0
1212       && strchr ("      ", cmd[strlen(sms_cmd)]))
1213     parse_and_set_memory_size (cmd + strlen(sms_cmd) + 1);
1214
1215   else if (strcmp (cmd, "help") == 0)
1216     {
1217         printf_filtered ("List of SH simulator commands:\n\n");
1218         printf_filtered ("set-memory-size <n> -- Set the number of address bits to use\n");
1219         printf_filtered ("\n");
1220     }
1221   else
1222     fprintf (stderr, "Error: \"%s\" is not a valid SH simulator command.\n",
1223              cmd);
1224 }