1 /* Simulator for the Hitachi SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
30 #include "gdb/callback.h"
31 #include "gdb/remote-sim.h"
32 #include "gdb/sim-sh.h"
34 /* This file is local - if newlib changes, then so should this. */
40 #include <float.h> /* Needed for _isnan() */
45 #define SIGBUS SIGSEGV
49 #define SIGQUIT SIGTERM
56 extern unsigned char sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
58 int sim_write (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
);
60 #define O_RECOMPILE 85
62 #define DISASSEMBLER_TABLE
64 /* Define the rate at which the simulator should poll the host
66 #define POLL_QUIT_INTERVAL 0x60000
76 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
77 which are located in fregs, i.e. strictly speaking, these are
78 out-of-bounds accesses of sregs.i . This wart of the code could be
79 fixed by making fregs part of sregs, and including pc too - to avoid
80 alignment repercussions - but this would cause very onerous union /
81 structure nesting, which would only be managable with anonymous
82 unions and structs. */
91 int fpul
; /* A1 for sh-dsp - but only for movs etc. */
92 int fpscr
; /* dsr for sh-dsp */
106 /* Control registers; on the SH4, ldc / stc is privileged, except when
127 unsigned char *insn_end
;
139 int end_of_registers
;
142 #define PROFILE_FREQ 1
143 #define PROFILE_SHIFT 2
145 unsigned short *profile_hist
;
146 unsigned char *memory
;
147 int xyram_select
, xram_start
, yram_start
;
150 unsigned char *xmem_offset
;
151 unsigned char *ymem_offset
;
157 saved_state_type saved_state
;
159 struct loop_bounds
{ unsigned char *start
, *end
; };
161 /* These variables are at file scope so that functions other than
162 sim_resume can use the fetch/store macros */
164 static int target_little_endian
;
165 static int global_endianw
, endianb
;
166 static int target_dsp
;
167 static int host_little_endian
;
168 static char **prog_argv
;
171 static int maskw
= 0;
172 static int maskl
= 0;
175 static SIM_OPEN_KIND sim_kind
;
179 /* Short hand definitions of the registers */
181 #define SBIT(x) ((x)&sbit)
182 #define R0 saved_state.asregs.regs[0]
183 #define Rn saved_state.asregs.regs[n]
184 #define Rm saved_state.asregs.regs[m]
185 #define UR0 (unsigned int)(saved_state.asregs.regs[0])
186 #define UR (unsigned int)R
187 #define UR (unsigned int)R
188 #define SR0 saved_state.asregs.regs[0]
189 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
190 #define GBR saved_state.asregs.cregs.named.gbr
191 #define VBR saved_state.asregs.cregs.named.vbr
192 #define SSR saved_state.asregs.cregs.named.ssr
193 #define SPC saved_state.asregs.cregs.named.spc
194 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
195 #define MACH saved_state.asregs.sregs.named.mach
196 #define MACL saved_state.asregs.sregs.named.macl
197 #define PR saved_state.asregs.sregs.named.pr
198 #define FPUL saved_state.asregs.sregs.named.fpul
204 /* Alternate bank of registers r0-r7 */
206 /* Note: code controling SR handles flips between BANK0 and BANK1 */
207 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
208 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
213 #define SR_MASK_DMY (1 << 11)
214 #define SR_MASK_DMX (1 << 10)
215 #define SR_MASK_M (1 << 9)
216 #define SR_MASK_Q (1 << 8)
217 #define SR_MASK_I (0xf << 4)
218 #define SR_MASK_S (1 << 1)
219 #define SR_MASK_T (1 << 0)
221 #define SR_MASK_BL (1 << 28)
222 #define SR_MASK_RB (1 << 29)
223 #define SR_MASK_MD (1 << 30)
224 #define SR_MASK_RC 0x0fff0000
225 #define SR_RC_INCREMENT -0x00010000
227 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
228 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
229 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
230 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
232 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
233 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
234 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
235 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
236 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
237 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
239 /* Note: don't use this for privileged bits */
240 #define SET_SR_BIT(EXP, BIT) \
243 saved_state.asregs.cregs.named.sr |= (BIT); \
245 saved_state.asregs.cregs.named.sr &= ~(BIT); \
248 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
249 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
250 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
251 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
253 /* stc currently relies on being able to read SR without modifications. */
254 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
256 #define SET_SR(x) set_sr (x)
259 (saved_state.asregs.cregs.named.sr \
260 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
262 /* Manipulate FPSCR */
264 #define FPSCR_MASK_FR (1 << 21)
265 #define FPSCR_MASK_SZ (1 << 20)
266 #define FPSCR_MASK_PR (1 << 19)
268 #define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
269 #define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
270 #define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
272 /* Count the number of arguments in an argv. */
274 count_argc (char **argv
)
281 for (i
= 0; argv
[i
] != NULL
; ++i
)
290 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
291 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
292 /* swap the floating point register banks */
293 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
294 /* Ignore bit change if simulating sh-dsp. */
297 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
298 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
299 saved_state
.asregs
.fregs
[1] = tmpf
;
303 /* sts relies on being able to read fpscr directly. */
304 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
305 #define SET_FPSCR(x) \
310 #define DSR (saved_state.asregs.sregs.named.fpscr)
318 #define RAISE_EXCEPTION(x) \
319 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
321 /* This function exists mainly for the purpose of setting a breakpoint to
322 catch simulated bus errors when running the simulator under GDB. */
334 raise_exception (SIGBUS
);
337 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
338 forbidden_addr_bits, data, retval) \
340 if (addr & forbidden_addr_bits) \
345 else if ((addr & saved_state.asregs.xyram_select) \
346 == saved_state.asregs.xram_start) \
347 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
348 else if ((addr & saved_state.asregs.xyram_select) \
349 == saved_state.asregs.yram_start) \
350 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
351 else if ((unsigned) addr >> 24 == 0xf0 \
352 && bits_written == 32 && (data & 1) == 0) \
353 /* This invalidates (if not associative) or might invalidate \
354 (if associative) an instruction cache line. This is used for \
355 trampolines. Since we don't simulate the cache, this is a no-op \
356 as far as the simulator is concerned. */ \
360 if (bits_written == 8 && addr > 0x5000000) \
361 IOMEM (addr, 1, data); \
362 /* We can't do anything useful with the other stuff, so fail. */ \
368 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
369 being implemented by ../common/sim_resume.c and the below should
370 make a call to sim_engine_halt */
372 #define BUSERROR(addr, mask) ((addr) & (mask))
374 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
379 addr_func (addr, data); \
385 #define READ_BUSERROR(addr, mask, addr_func) \
389 return addr_func (addr); \
393 /* Define this to enable register lifetime checking.
394 The compiler generates "add #0,rn" insns to mark registers as invalid,
395 the simulator uses this info to call fail if it finds a ref to an invalid
396 register before a def
403 #define CREF(x) if(!valid[x]) fail();
404 #define CDEF(x) valid[x] = 1;
405 #define UNDEF(x) valid[x] = 0;
412 static void parse_and_set_memory_size
PARAMS ((char *str
));
413 static int IOMEM
PARAMS ((int addr
, int write
, int value
));
414 static struct loop_bounds get_loop_bounds
PARAMS((int, int, unsigned char *,
415 unsigned char *, int, int));
416 static void process_wlat_addr
PARAMS((int, int));
417 static void process_wwat_addr
PARAMS((int, int));
418 static void process_wbat_addr
PARAMS((int, int));
419 static int process_rlat_addr
PARAMS((int));
420 static int process_rwat_addr
PARAMS((int));
421 static int process_rbat_addr
PARAMS((int));
422 static void INLINE wlat_fast
PARAMS ((unsigned char *, int, int, int));
423 static void INLINE wwat_fast
PARAMS ((unsigned char *, int, int, int, int));
424 static void INLINE wbat_fast
PARAMS ((unsigned char *, int, int, int));
425 static int INLINE rlat_fast
PARAMS ((unsigned char *, int, int));
426 static int INLINE rwat_fast
PARAMS ((unsigned char *, int, int, int));
427 static int INLINE rbat_fast
PARAMS ((unsigned char *, int, int));
429 static host_callback
*callback
;
433 /* Floating point registers */
435 #define DR(n) (get_dr (n))
441 if (host_little_endian
)
448 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
449 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
453 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
456 #define SET_DR(n, EXP) set_dr ((n), (EXP))
463 if (host_little_endian
)
471 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
472 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
475 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
478 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
479 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
481 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
482 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
484 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
485 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
486 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
488 #define RS saved_state.asregs.cregs.named.rs
489 #define RE saved_state.asregs.cregs.named.re
490 #define MOD (saved_state.asregs.cregs.named.mod)
493 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
494 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
496 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
497 #define DSP_GRD(n) DSP_R ((n) + 8)
498 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
503 #define Y0 DSP_R (10)
504 #define Y1 DSP_R (11)
505 #define M0 DSP_R (12)
506 #define A1G DSP_R (13)
507 #define M1 DSP_R (14)
508 #define A0G DSP_R (15)
509 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
510 #define MOD_ME DSP_GRD (17)
511 #define MOD_DELTA DSP_GRD (18)
513 #define FP_OP(n, OP, m) \
517 if (((n) & 1) || ((m) & 1)) \
518 RAISE_EXCEPTION (SIGILL); \
520 SET_DR(n, (DR(n) OP DR(m))); \
523 SET_FR(n, (FR(n) OP FR(m))); \
526 #define FP_UNARY(n, OP) \
531 RAISE_EXCEPTION (SIGILL); \
533 SET_DR(n, (OP (DR(n)))); \
536 SET_FR(n, (OP (FR(n)))); \
539 #define FP_CMP(n, OP, m) \
543 if (((n) & 1) || ((m) & 1)) \
544 RAISE_EXCEPTION (SIGILL); \
546 SET_SR_T (DR(n) OP DR(m)); \
549 SET_SR_T (FR(n) OP FR(m)); \
556 /* do we need to swap banks */
557 int old_gpr
= SR_MD
&& SR_RB
;
558 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
559 if (old_gpr
!= new_gpr
)
562 for (i
= 0; i
< 8; i
++)
564 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
565 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
566 saved_state
.asregs
.regs
[i
] = tmp
;
569 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
574 wlat_fast (memory
, x
, value
, maskl
)
575 unsigned char *memory
;
578 unsigned int *p
= (unsigned int *)(memory
+ x
);
579 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
584 wwat_fast (memory
, x
, value
, maskw
, endianw
)
585 unsigned char *memory
;
588 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
589 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
594 wbat_fast (memory
, x
, value
, maskb
)
595 unsigned char *memory
;
597 unsigned char *p
= memory
+ (x
^ endianb
);
598 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
606 rlat_fast (memory
, x
, maskl
)
607 unsigned char *memory
;
609 unsigned int *p
= (unsigned int *)(memory
+ x
);
610 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
616 rwat_fast (memory
, x
, maskw
, endianw
)
617 unsigned char *memory
;
618 int x
, maskw
, endianw
;
620 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
621 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
627 riat_fast (insn_ptr
, endianw
)
628 unsigned char *insn_ptr
;
630 unsigned short *p
= (unsigned short *)((size_t) insn_ptr
^ endianw
);
636 rbat_fast (memory
, x
, maskb
)
637 unsigned char *memory
;
639 unsigned char *p
= memory
+ (x
^ endianb
);
640 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
645 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
646 #define RLAT(x) (rlat_fast (memory, x, maskl))
647 #define RBAT(x) (rbat_fast (memory, x, maskb))
648 #define RIAT(p) (riat_fast ((p), endianw))
649 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
650 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
651 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
653 #define RUWAT(x) (RWAT(x) & 0xffff)
654 #define RSWAT(x) ((short)(RWAT(x)))
655 #define RSLAT(x) ((long)(RLAT(x)))
656 #define RSBAT(x) (SEXT(RBAT(x)))
658 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
660 do_rdat (memory
, x
, n
, maskl
)
670 f0
= rlat_fast (memory
, x
+ 0, maskl
);
671 f1
= rlat_fast (memory
, x
+ 4, maskl
);
672 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
673 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
677 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
679 do_wdat (memory
, x
, n
, maskl
)
689 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
690 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
691 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
692 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
697 process_wlat_addr (addr
, value
)
703 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
708 process_wwat_addr (addr
, value
)
714 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
719 process_wbat_addr (addr
, value
)
725 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
730 process_rlat_addr (addr
)
735 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
740 process_rwat_addr (addr
)
745 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
750 process_rbat_addr (addr
)
755 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
759 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
760 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
761 #define SEXTW(y) ((int)((short)y))
763 #define SEXT32(x) ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
765 #define SEXT32(x) ((int)(x))
767 #define SIGN32(x) (SEXT32 (x) >> 31)
769 /* convert pointer from target to host value. */
770 #define PT2H(x) ((x) + memory)
771 /* convert pointer from host to target value. */
772 #define PH2T(x) ((x) - memory)
774 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
776 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
778 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); goto top;
780 #define CHECK_INSN_PTR(p) \
782 if (saved_state.asregs.exception || PH2T (p) & maskw) \
783 saved_state.asregs.insn_end = 0; \
784 else if (p < loop.end) \
785 saved_state.asregs.insn_end = loop.end; \
787 saved_state.asregs.insn_end = mem_end; \
800 do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
802 #define L(x) thislock = x;
803 #define TL(x) if ((x) == prevlock) stalls++;
804 #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
808 #if defined(__GO32__) || defined(_WIN32)
809 int sim_memory_size
= 19;
811 int sim_memory_size
= 24;
814 static int sim_profile_size
= 17;
820 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
821 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
822 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
823 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
824 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
825 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
827 #define SCI_RDRF 0x40 /* Recieve data register full */
828 #define SCI_TDRE 0x80 /* Transmit data register empty */
831 IOMEM (addr
, write
, value
)
863 return time ((long *) 0);
872 static FILE *profile_file
;
874 static unsigned INLINE
879 n
= (n
<< 24 | (n
& 0xff00) << 8
880 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
884 static unsigned short INLINE
889 n
= n
<< 8 | (n
& 0xff00) >> 8;
899 union { char b
[4]; int n
; } u
;
901 fwrite (u
.b
, 4, 1, profile_file
);
909 union { char b
[4]; int n
; } u
;
911 fwrite (u
.b
, 2, 1, profile_file
);
914 /* Turn a pointer in a register into a pointer into real memory. */
920 return (char *) (x
+ saved_state
.asregs
.memory
);
927 unsigned char *memory
= saved_state
.asregs
.memory
;
929 int endian
= endianb
;
934 for (end
= str
; memory
[end
^ endian
]; end
++) ;
945 if (! endianb
|| ! len
)
947 start
= (int *) ptr (str
& ~3);
948 end
= (int *) ptr (str
+ len
);
952 *start
= (old
<< 24 | (old
& 0xff00) << 8
953 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
959 /* Simulate a monitor trap, put the result into r0 and errno into r1
960 return offset by which to adjust pc. */
963 trap (i
, regs
, insn_ptr
, memory
, maskl
, maskw
, endianw
)
966 unsigned char *insn_ptr
;
967 unsigned char *memory
;
972 printf ("%c", regs
[0]);
975 raise_exception (SIGQUIT
);
977 case 3: /* FIXME: for backwards compat, should be removed */
980 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
982 WLAT (countp
, RLAT (countp
) + 1);
994 #if !defined(__GO32__) && !defined(_WIN32)
998 /* This would work only if endianness matched between host and target.
999 Besides, it's quite dangerous. */
1002 regs
[0] = execve (ptr (regs
[5]), (char **)ptr (regs
[6]), (char **)ptr (regs
[7]));
1005 regs
[0] = execve (ptr (regs
[5]),(char **) ptr (regs
[6]), 0);
1010 regs
[0] = (BUSERROR (regs
[5], maskl
)
1012 : pipe ((int *) ptr (regs
[5])));
1017 regs
[0] = wait (ptr (regs
[5]));
1019 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1022 strnswap (regs
[6], regs
[7]);
1024 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1025 strnswap (regs
[6], regs
[7]);
1028 strnswap (regs
[6], regs
[7]);
1030 regs
[0] = (int)callback
->write_stdout (callback
, ptr(regs
[6]), regs
[7]);
1032 regs
[0] = (int)callback
->write (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1033 strnswap (regs
[6], regs
[7]);
1036 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
1039 regs
[0] = callback
->close (callback
,regs
[5]);
1043 int len
= strswaplen (regs
[5]);
1044 strnswap (regs
[5], len
);
1045 regs
[0] = callback
->open (callback
,ptr (regs
[5]), regs
[6]);
1046 strnswap (regs
[5], len
);
1050 /* EXIT - caller can look in r5 to work out the reason */
1051 raise_exception (SIGQUIT
);
1055 case SYS_stat
: /* added at hmsi */
1056 /* stat system call */
1058 struct stat host_stat
;
1060 int len
= strswaplen (regs
[5]);
1062 strnswap (regs
[5], len
);
1063 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
1064 strnswap (regs
[5], len
);
1068 WWAT (buf
, host_stat
.st_dev
);
1070 WWAT (buf
, host_stat
.st_ino
);
1072 WLAT (buf
, host_stat
.st_mode
);
1074 WWAT (buf
, host_stat
.st_nlink
);
1076 WWAT (buf
, host_stat
.st_uid
);
1078 WWAT (buf
, host_stat
.st_gid
);
1080 WWAT (buf
, host_stat
.st_rdev
);
1082 WLAT (buf
, host_stat
.st_size
);
1084 WLAT (buf
, host_stat
.st_atime
);
1088 WLAT (buf
, host_stat
.st_mtime
);
1092 WLAT (buf
, host_stat
.st_ctime
);
1106 int len
= strswaplen (regs
[5]);
1108 strnswap (regs
[5], len
);
1109 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1110 strnswap (regs
[5], len
);
1116 int len
= strswaplen (regs
[5]);
1118 strnswap (regs
[5], len
);
1119 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1120 strnswap (regs
[5], len
);
1125 /* Cast the second argument to void *, to avoid type mismatch
1126 if a prototype is present. */
1127 int len
= strswaplen (regs
[5]);
1129 strnswap (regs
[5], len
);
1130 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1131 strnswap (regs
[5], len
);
1135 regs
[0] = count_argc (prog_argv
);
1138 if (regs
[5] < count_argc (prog_argv
))
1139 regs
[0] = strlen (prog_argv
[regs
[5]]);
1144 if (regs
[5] < count_argc (prog_argv
))
1146 /* Include the termination byte. */
1147 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1148 regs
[0] = sim_write (0, regs
[6], prog_argv
[regs
[5]], i
);
1154 regs
[0] = get_now ();
1157 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1161 int len
= strswaplen (regs
[5]);
1162 strnswap (regs
[5], len
);
1163 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1164 strnswap (regs
[5], len
);
1171 regs
[1] = callback
->get_errno (callback
);
1178 raise_exception (SIGTRAP
);
1187 control_c (sig
, code
, scp
, addr
)
1193 raise_exception (SIGINT
);
1197 div1 (R
, iRn2
, iRn1
/*, T*/)
1204 unsigned char old_q
, tmp1
;
1207 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1209 R
[iRn1
] |= (unsigned long) T
;
1219 tmp1
= (R
[iRn1
] > tmp0
);
1226 SET_SR_Q ((unsigned char) (tmp1
== 0));
1233 tmp1
= (R
[iRn1
] < tmp0
);
1237 SET_SR_Q ((unsigned char) (tmp1
== 0));
1252 tmp1
= (R
[iRn1
] < tmp0
);
1259 SET_SR_Q ((unsigned char) (tmp1
== 0));
1266 tmp1
= (R
[iRn1
] > tmp0
);
1270 SET_SR_Q ((unsigned char) (tmp1
== 0));
1291 unsigned long RnL
, RnH
;
1292 unsigned long RmL
, RmH
;
1293 unsigned long temp0
, temp1
, temp2
, temp3
;
1294 unsigned long Res2
, Res1
, Res0
;
1297 RnH
= (rn
>> 16) & 0xffff;
1299 RmH
= (rm
>> 16) & 0xffff;
1305 Res1
= temp1
+ temp2
;
1308 temp1
= (Res1
<< 16) & 0xffff0000;
1309 Res0
= temp0
+ temp1
;
1312 Res2
+= ((Res1
>> 16) & 0xffff) + temp3
;
1316 if (rn
& 0x80000000)
1318 if (rm
& 0x80000000)
1327 macw (regs
, memory
, n
, m
, endianw
)
1329 unsigned char *memory
;
1334 long prod
, macl
, sum
;
1336 tempm
=RSWAT(regs
[m
]); regs
[m
]+=2;
1337 tempn
=RSWAT(regs
[n
]); regs
[n
]+=2;
1340 prod
= (long)(short) tempm
* (long)(short) tempn
;
1344 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1346 /* MACH's lsb is a sticky overflow bit. */
1348 /* Store the smallest negative number in MACL if prod is
1349 negative, and the largest positive number otherwise. */
1350 sum
= 0x7fffffff + (prod
< 0);
1356 /* Add to MACH the sign extended product, and carry from low sum. */
1357 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1358 /* Sign extend at 10:th bit in MACH. */
1359 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1365 macl (regs
, memory
, n
, m
)
1367 unsigned char *memory
;
1371 long prod
, macl
, mach
, sum
;
1372 long long ans
,ansl
,ansh
,t
;
1373 unsigned long long high
,low
,combine
;
1376 long m
[2]; /* mach and macl*/
1377 long long m64
; /* 64 bit MAC */
1380 tempm
= RSLAT(regs
[m
]);
1383 tempn
= RSLAT(regs
[n
]);
1392 ans
= (long long)tempm
* (long long)tempn
; /* Multiply 32bit * 32bit */
1394 mac64
.m64
+= ans
; /* Accumulate 64bit + 64 bit */
1399 if (S
) /* Store only 48 bits of the result */
1401 if (mach
< 0) /* Result is negative */
1403 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1404 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1407 mach
= mach
& 0x00007fff; /* Postive Result */
1415 fsca_s (int in
, double (*f
) (double))
1417 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1418 double result
= (*f
) (rad
);
1419 double error
, upper
, lower
, frac
;
1422 /* Search the value with the maximum error that is still within the
1423 architectural spec. */
1424 error
= ldexp (1., -21);
1425 /* compensate for calculation inaccuracy by reducing error. */
1426 error
= error
- ldexp (1., -50);
1427 upper
= result
+ error
;
1428 frac
= frexp (upper
, &exp
);
1429 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1430 lower
= result
- error
;
1431 frac
= frexp (lower
, &exp
);
1432 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1433 return abs (upper
- result
) >= abs (lower
- result
) ? upper
: lower
;
1439 double result
= 1. / sqrt (in
);
1441 double frac
, upper
, lower
, error
, eps
;
1444 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1445 /* Search the value with the maximum error that is still within the
1446 architectural spec. */
1447 frac
= frexp (result
, &exp
);
1448 frac
= ldexp (frac
, 24);
1449 error
= 4.; /* 1 << 24-1-21 */
1450 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1451 eps
= ldexp (1., -29);
1452 upper
= floor (frac
+ error
- eps
);
1453 if (upper
> 16777216.)
1454 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1455 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1456 if (lower
> 8388608.)
1457 lower
= ceil (frac
- error
+ eps
);
1458 upper
= ldexp (upper
, exp
- 24);
1459 lower
= ldexp (lower
, exp
- 24);
1460 return upper
- result
>= result
- lower
? upper
: lower
;
1463 static struct loop_bounds
1464 get_loop_bounds (rs
, re
, memory
, mem_end
, maskw
, endianw
)
1466 unsigned char *memory
, *mem_end
;
1469 struct loop_bounds loop
;
1475 loop
.start
= PT2H (RE
- 4);
1476 SKIP_INSN (loop
.start
);
1477 loop
.end
= loop
.start
;
1479 SKIP_INSN (loop
.end
);
1481 SKIP_INSN (loop
.end
);
1482 SKIP_INSN (loop
.end
);
1486 loop
.start
= PT2H (RS
);
1487 loop
.end
= PT2H (RE
- 4);
1488 SKIP_INSN (loop
.end
);
1489 SKIP_INSN (loop
.end
);
1490 SKIP_INSN (loop
.end
);
1491 SKIP_INSN (loop
.end
);
1493 if (loop
.end
>= mem_end
)
1494 loop
.end
= PT2H (0);
1497 loop
.end
= PT2H (0);
1507 /* Set the memory size to the power of two provided. */
1514 saved_state
.asregs
.msize
= 1 << power
;
1516 sim_memory_size
= power
;
1518 if (saved_state
.asregs
.memory
)
1520 free (saved_state
.asregs
.memory
);
1523 saved_state
.asregs
.memory
=
1524 (unsigned char *) calloc (64, saved_state
.asregs
.msize
/ 64);
1526 if (!saved_state
.asregs
.memory
)
1529 "Not enough VM for simulation of %d bytes of RAM\n",
1530 saved_state
.asregs
.msize
);
1532 saved_state
.asregs
.msize
= 1;
1533 saved_state
.asregs
.memory
= (unsigned char *) calloc (1, 1);
1541 int was_dsp
= target_dsp
;
1542 unsigned long mach
= bfd_get_mach (abfd
);
1544 if (mach
== bfd_mach_sh_dsp
|| mach
== bfd_mach_sh3_dsp
)
1546 int ram_area_size
, xram_start
, yram_start
;
1550 if (mach
== bfd_mach_sh_dsp
)
1552 /* SH7410 (orig. sh-sdp):
1553 4KB each for X & Y memory;
1554 On-chip X RAM 0x0800f000-0x0800ffff
1555 On-chip Y RAM 0x0801f000-0x0801ffff */
1556 xram_start
= 0x0800f000;
1557 ram_area_size
= 0x1000;
1559 if (mach
== bfd_mach_sh3_dsp
)
1562 8KB each for X & Y memory;
1563 On-chip X RAM 0x1000e000-0x1000ffff
1564 On-chip Y RAM 0x1001e000-0x1001ffff */
1565 xram_start
= 0x1000e000;
1566 ram_area_size
= 0x2000;
1568 yram_start
= xram_start
+ 0x10000;
1569 new_select
= ~(ram_area_size
- 1);
1570 if (saved_state
.asregs
.xyram_select
!= new_select
)
1572 saved_state
.asregs
.xyram_select
= new_select
;
1573 free (saved_state
.asregs
.xmem
);
1574 free (saved_state
.asregs
.ymem
);
1575 saved_state
.asregs
.xmem
= (unsigned char *) calloc (1, ram_area_size
);
1576 saved_state
.asregs
.ymem
= (unsigned char *) calloc (1, ram_area_size
);
1578 /* Disable use of X / Y mmeory if not allocated. */
1579 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1581 saved_state
.asregs
.xyram_select
= 0;
1582 if (saved_state
.asregs
.xmem
)
1583 free (saved_state
.asregs
.xmem
);
1584 if (saved_state
.asregs
.ymem
)
1585 free (saved_state
.asregs
.ymem
);
1588 saved_state
.asregs
.xram_start
= xram_start
;
1589 saved_state
.asregs
.yram_start
= yram_start
;
1590 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1591 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1596 if (saved_state
.asregs
.xyram_select
)
1598 saved_state
.asregs
.xyram_select
= 0;
1599 free (saved_state
.asregs
.xmem
);
1600 free (saved_state
.asregs
.ymem
);
1604 if (! saved_state
.asregs
.xyram_select
)
1606 saved_state
.asregs
.xram_start
= 1;
1607 saved_state
.asregs
.yram_start
= 1;
1610 if (target_dsp
!= was_dsp
)
1614 for (i
= sizeof sh_dsp_table
- 1; i
>= 0; i
--)
1616 tmp
= sh_jump_table
[0xf000 + i
];
1617 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1618 sh_dsp_table
[i
] = tmp
;
1626 host_little_endian
= 0;
1627 *(char*)&host_little_endian
= 1;
1628 host_little_endian
&= 1;
1630 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1632 sim_size (sim_memory_size
);
1635 if (saved_state
.asregs
.profile
&& !profile_file
)
1637 profile_file
= fopen ("gmon.out", "wb");
1638 /* Seek to where to put the call arc data */
1639 nsamples
= (1 << sim_profile_size
);
1641 fseek (profile_file
, nsamples
* 2 + 12, 0);
1645 fprintf (stderr
, "Can't open gmon.out\n");
1649 saved_state
.asregs
.profile_hist
=
1650 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1663 p
= saved_state
.asregs
.profile_hist
;
1665 maxpc
= (1 << sim_profile_size
);
1667 fseek (profile_file
, 0L, 0);
1668 swapout (minpc
<< PROFILE_SHIFT
);
1669 swapout (maxpc
<< PROFILE_SHIFT
);
1670 swapout (nsamples
* 2 + 12);
1671 for (i
= 0; i
< nsamples
; i
++)
1672 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1686 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1692 raise_exception (SIGINT
);
1697 sim_resume (sd
, step
, siggnal
)
1701 register unsigned char *insn_ptr
;
1702 unsigned char *mem_end
;
1703 struct loop_bounds loop
;
1704 register int cycles
= 0;
1705 register int stalls
= 0;
1706 register int memstalls
= 0;
1707 register int insts
= 0;
1708 register int prevlock
;
1709 register int thislock
;
1710 register unsigned int doprofile
;
1711 register int pollcount
= 0;
1712 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1713 endianb is used less often. */
1714 register int endianw
= global_endianw
;
1716 int tick_start
= get_now ();
1718 void (*prev_fpe
) ();
1720 register unsigned char *jump_table
= sh_jump_table
;
1722 register int *R
= &(saved_state
.asregs
.regs
[0]);
1728 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1729 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1730 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1731 register unsigned char *memory
;
1732 register unsigned int sbit
= ((unsigned int) 1 << 31);
1734 prev
= signal (SIGINT
, control_c
);
1735 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1738 saved_state
.asregs
.exception
= 0;
1740 memory
= saved_state
.asregs
.memory
;
1741 mem_end
= memory
+ saved_state
.asregs
.msize
;
1743 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1744 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1745 CHECK_INSN_PTR (insn_ptr
);
1748 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1750 /*T = GET_SR () & SR_MASK_T;*/
1751 prevlock
= saved_state
.asregs
.prevlock
;
1752 thislock
= saved_state
.asregs
.thislock
;
1753 doprofile
= saved_state
.asregs
.profile
;
1755 /* If profiling not enabled, disable it by asking for
1756 profiles infrequently. */
1761 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1763 if (saved_state
.asregs
.exception
)
1764 /* This can happen if we've already been single-stepping and
1765 encountered a loop end. */
1766 saved_state
.asregs
.insn_end
= insn_ptr
;
1769 saved_state
.asregs
.exception
= SIGTRAP
;
1770 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1774 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1776 register unsigned int iword
= RIAT (insn_ptr
);
1777 register unsigned int ult
;
1778 register unsigned char *nip
= insn_ptr
+ 2;
1790 if (--pollcount
< 0)
1792 pollcount
= POLL_QUIT_INTERVAL
;
1793 if ((*callback
->poll_quit
) != NULL
1794 && (*callback
->poll_quit
) (callback
))
1801 prevlock
= thislock
;
1805 if (cycles
>= doprofile
)
1808 saved_state
.asregs
.cycles
+= doprofile
;
1809 cycles
-= doprofile
;
1810 if (saved_state
.asregs
.profile_hist
)
1812 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1815 int i
= saved_state
.asregs
.profile_hist
[n
];
1817 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1824 if (saved_state
.asregs
.insn_end
== loop
.end
)
1826 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1828 insn_ptr
= loop
.start
;
1831 saved_state
.asregs
.insn_end
= mem_end
;
1832 loop
.end
= PT2H (0);
1837 if (saved_state
.asregs
.exception
== SIGILL
1838 || saved_state
.asregs
.exception
== SIGBUS
)
1842 /* Check for SIGBUS due to insn fetch. */
1843 else if (! saved_state
.asregs
.exception
)
1844 saved_state
.asregs
.exception
= SIGBUS
;
1846 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1847 saved_state
.asregs
.cycles
+= cycles
;
1848 saved_state
.asregs
.stalls
+= stalls
;
1849 saved_state
.asregs
.memstalls
+= memstalls
;
1850 saved_state
.asregs
.insts
+= insts
;
1851 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1853 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1856 saved_state
.asregs
.prevlock
= prevlock
;
1857 saved_state
.asregs
.thislock
= thislock
;
1864 signal (SIGFPE
, prev_fpe
);
1865 signal (SIGINT
, prev
);
1869 sim_write (sd
, addr
, buffer
, size
)
1872 unsigned char *buffer
;
1879 for (i
= 0; i
< size
; i
++)
1881 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1887 sim_read (sd
, addr
, buffer
, size
)
1890 unsigned char *buffer
;
1897 for (i
= 0; i
< size
; i
++)
1899 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1905 sim_store_register (sd
, rn
, memory
, length
)
1908 unsigned char *memory
;
1914 val
= swap (* (int *)memory
);
1917 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
1918 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
1919 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
1920 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
1921 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
1922 case SIM_SH_R15_REGNUM
:
1923 saved_state
.asregs
.regs
[rn
] = val
;
1925 case SIM_SH_PC_REGNUM
:
1926 saved_state
.asregs
.pc
= val
;
1928 case SIM_SH_PR_REGNUM
:
1931 case SIM_SH_GBR_REGNUM
:
1934 case SIM_SH_VBR_REGNUM
:
1937 case SIM_SH_MACH_REGNUM
:
1940 case SIM_SH_MACL_REGNUM
:
1943 case SIM_SH_SR_REGNUM
:
1946 case SIM_SH_FPUL_REGNUM
:
1949 case SIM_SH_FPSCR_REGNUM
:
1952 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
1953 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
1954 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
1955 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
1956 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
1957 case SIM_SH_FR15_REGNUM
:
1958 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
1960 case SIM_SH_DSR_REGNUM
:
1963 case SIM_SH_A0G_REGNUM
:
1966 case SIM_SH_A0_REGNUM
:
1969 case SIM_SH_A1G_REGNUM
:
1972 case SIM_SH_A1_REGNUM
:
1975 case SIM_SH_M0_REGNUM
:
1978 case SIM_SH_M1_REGNUM
:
1981 case SIM_SH_X0_REGNUM
:
1984 case SIM_SH_X1_REGNUM
:
1987 case SIM_SH_Y0_REGNUM
:
1990 case SIM_SH_Y1_REGNUM
:
1993 case SIM_SH_MOD_REGNUM
:
1996 case SIM_SH_RS_REGNUM
:
1999 case SIM_SH_RE_REGNUM
:
2002 case SIM_SH_SSR_REGNUM
:
2005 case SIM_SH_SPC_REGNUM
:
2008 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2009 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2010 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2011 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2012 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2013 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2015 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2017 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2019 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2020 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2021 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2022 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2024 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2026 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2028 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2029 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2030 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2031 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2032 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2041 sim_fetch_register (sd
, rn
, memory
, length
)
2044 unsigned char *memory
;
2052 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2053 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2054 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2055 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2056 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2057 case SIM_SH_R15_REGNUM
:
2058 val
= saved_state
.asregs
.regs
[rn
];
2060 case SIM_SH_PC_REGNUM
:
2061 val
= saved_state
.asregs
.pc
;
2063 case SIM_SH_PR_REGNUM
:
2066 case SIM_SH_GBR_REGNUM
:
2069 case SIM_SH_VBR_REGNUM
:
2072 case SIM_SH_MACH_REGNUM
:
2075 case SIM_SH_MACL_REGNUM
:
2078 case SIM_SH_SR_REGNUM
:
2081 case SIM_SH_FPUL_REGNUM
:
2084 case SIM_SH_FPSCR_REGNUM
:
2087 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2088 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2089 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2090 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2091 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2092 case SIM_SH_FR15_REGNUM
:
2093 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2095 case SIM_SH_DSR_REGNUM
:
2098 case SIM_SH_A0G_REGNUM
:
2101 case SIM_SH_A0_REGNUM
:
2104 case SIM_SH_A1G_REGNUM
:
2107 case SIM_SH_A1_REGNUM
:
2110 case SIM_SH_M0_REGNUM
:
2113 case SIM_SH_M1_REGNUM
:
2116 case SIM_SH_X0_REGNUM
:
2119 case SIM_SH_X1_REGNUM
:
2122 case SIM_SH_Y0_REGNUM
:
2125 case SIM_SH_Y1_REGNUM
:
2128 case SIM_SH_MOD_REGNUM
:
2131 case SIM_SH_RS_REGNUM
:
2134 case SIM_SH_RE_REGNUM
:
2137 case SIM_SH_SSR_REGNUM
:
2140 case SIM_SH_SPC_REGNUM
:
2143 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2144 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2145 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2146 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2147 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2148 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2149 val
= (SR_MD
&& SR_RB
2150 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2151 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2153 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2154 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2155 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2156 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2157 val
= (! SR_MD
|| ! SR_RB
2158 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2159 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2161 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2162 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2163 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2164 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2165 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2170 * (int *) memory
= swap (val
);
2182 sim_stop_reason (sd
, reason
, sigrc
)
2184 enum sim_stop
*reason
;
2187 /* The SH simulator uses SIGQUIT to indicate that the program has
2188 exited, so we must check for it here and translate it to exit. */
2189 if (saved_state
.asregs
.exception
== SIGQUIT
)
2191 *reason
= sim_exited
;
2192 *sigrc
= saved_state
.asregs
.regs
[5];
2196 *reason
= sim_stopped
;
2197 *sigrc
= saved_state
.asregs
.exception
;
2202 sim_info (sd
, verbose
)
2206 double timetaken
= (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2207 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2209 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
2210 saved_state
.asregs
.insts
);
2211 callback
->printf_filtered (callback
, "# cycles %10d\n",
2212 saved_state
.asregs
.cycles
);
2213 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
2214 saved_state
.asregs
.stalls
);
2215 callback
->printf_filtered (callback
, "# misaligned load/store %10d\n",
2216 saved_state
.asregs
.memstalls
);
2217 callback
->printf_filtered (callback
, "# real time taken %10.4f\n",
2219 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
2221 callback
->printf_filtered (callback
, "# profiling size %10d\n",
2223 callback
->printf_filtered (callback
, "# profiling frequency %10d\n",
2224 saved_state
.asregs
.profile
);
2225 callback
->printf_filtered (callback
, "# profile maxpc %10x\n",
2226 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2230 callback
->printf_filtered (callback
, "# cycles/second %10d\n",
2231 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2232 callback
->printf_filtered (callback
, "# simulation ratio %10.4f\n",
2233 virttime
/ timetaken
);
2241 saved_state
.asregs
.profile
= n
;
2245 sim_set_profile_size (n
)
2248 sim_profile_size
= n
;
2252 sim_open (kind
, cb
, abfd
, argv
)
2273 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2275 if (strcmp (*p
, "-E") == 0)
2280 /* FIXME: This doesn't use stderr, but then the rest of the
2281 file doesn't either. */
2282 callback
->printf_filtered (callback
, "Missing argument to `-E'.\n");
2285 target_little_endian
= strcmp (*p
, "big") != 0;
2288 else if (isdigit (**p
))
2289 parse_and_set_memory_size (*p
);
2292 if (abfd
!= NULL
&& ! endian_set
)
2293 target_little_endian
= ! bfd_big_endian (abfd
);
2298 for (i
= 4; (i
-= 2) >= 0; )
2299 mem_word
.s
[i
>> 1] = i
;
2300 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2302 for (i
= 4; --i
>= 0; )
2304 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2306 /* fudge our descriptor for now */
2307 return (SIM_DESC
) 1;
2311 parse_and_set_memory_size (str
)
2316 n
= strtol (str
, NULL
, 10);
2317 if (n
> 0 && n
<= 24)
2318 sim_memory_size
= n
;
2320 callback
->printf_filtered (callback
, "Bad memory size %d; must be 1 to 24, inclusive\n", n
);
2324 sim_close (sd
, quitting
)
2332 sim_load (sd
, prog
, abfd
, from_tty
)
2338 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
2341 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
2342 sim_kind
== SIM_OPEN_DEBUG
,
2344 if (prog_bfd
== NULL
)
2347 bfd_close (prog_bfd
);
2352 sim_create_inferior (sd
, prog_bfd
, argv
, env
)
2354 struct bfd
*prog_bfd
;
2358 /* Clear the registers. */
2359 memset (&saved_state
, 0,
2360 (char*)&saved_state
.asregs
.end_of_registers
- (char*)&saved_state
);
2363 if (prog_bfd
!= NULL
)
2364 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2366 /* Record the program's arguments. */
2373 sim_do_command (sd
, cmd
)
2377 char *sms_cmd
= "set-memory-size";
2380 if (cmd
== NULL
|| *cmd
== '\0')
2385 cmdsize
= strlen (sms_cmd
);
2386 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2388 parse_and_set_memory_size (cmd
+ cmdsize
+ 1);
2390 else if (strcmp (cmd
, "help") == 0)
2392 (callback
->printf_filtered
) (callback
, "List of SH simulator commands:\n\n");
2393 (callback
->printf_filtered
) (callback
, "set-memory-size <n> -- Set the number of address bits to use\n");
2394 (callback
->printf_filtered
) (callback
, "\n");
2398 (callback
->printf_filtered
) (callback
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);
2403 sim_set_callbacks (p
)