sim/sh/sim-main.h

   1 /* Moxie Simulator definition.
   2    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, the GNU debugger.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef SIM_MAIN_H
  20 #define SIM_MAIN_H
  21
  22 #include "sim-basics.h"
  23
  24 typedef struct _sim_cpu SIM_CPU;
  25
  26 #include "sim-base.h"
  27
  28 typedef struct
  29 {
  30   int regs[20];
  31 } regstacktype;
  32
  33 typedef union
  34 {
  35
  36   struct
  37   {
  38     int regs[16];
  39     int pc;
  40
  41     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  42        which are located in fregs, i.e. strictly speaking, these are
  43        out-of-bounds accesses of sregs.i .  This wart of the code could be
  44        fixed by making fregs part of sregs, and including pc too - to avoid
  45        alignment repercussions - but this would cause very onerous union /
  46        structure nesting, which would only be managable with anonymous
  47        unions and structs.  */
  48     union
  49       {
  50         struct
  51           {
  52             int mach;
  53             int macl;
  54             int pr;
  55             int dummy3, dummy4;
  56             int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
  57             int fpscr; /* dsr for sh-dsp */
  58           } named;
  59         int i[7];
  60       } sregs;
  61
  62     /* sh3e / sh-dsp */
  63     union fregs_u
  64       {
  65         float f[16];
  66         double d[8];
  67         int i[16];
  68       }
  69     fregs[2];
  70
  71     /* Control registers; on the SH4, ldc / stc is privileged, except when
  72        accessing gbr.  */
  73     union
  74       {
  75         struct
  76           {
  77             int sr;
  78             int gbr;
  79             int vbr;
  80             int ssr;
  81             int spc;
  82             int mod;
  83             /* sh-dsp */
  84             int rs;
  85             int re;
  86             /* sh3 */
  87             int bank[8];
  88             int dbr;            /* debug base register */
  89             int sgr;            /* saved gr15 */
  90             int ldst;           /* load/store flag (boolean) */
  91             int tbr;
  92             int ibcr;           /* sh2a bank control register */
  93             int ibnr;           /* sh2a bank number register */
  94           } named;
  95         int i[16];
  96       } cregs;
  97
  98     unsigned char *insn_end;
  99
 100     int ticks;
 101     int stalls;
 102     int memstalls;
 103     int cycles;
 104     int insts;
 105
 106     int prevlock;
 107     int thislock;
 108     int exception;
 109
 110     int end_of_registers;
 111
 112     int msize;
 113 #define PROFILE_FREQ 1
 114 #define PROFILE_SHIFT 2
 115     int profile;
 116     unsigned short *profile_hist;
 117     unsigned char *memory;
 118     int xyram_select, xram_start, yram_start;
 119     unsigned char *xmem;
 120     unsigned char *ymem;
 121     unsigned char *xmem_offset;
 122     unsigned char *ymem_offset;
 123     unsigned long bfd_mach;
 124     regstacktype *regstack;
 125   } asregs;
 126   int asints[40];
 127 } saved_state_type;
 128
 129 /* TODO: Move into sim_cpu.  */
 130 extern saved_state_type saved_state;
 131
 132 struct _sim_cpu {
 133
 134   sim_cpu_base base;
 135 };
 136
 137 struct sim_state {
 138
 139   sim_cpu *cpu[MAX_NR_PROCESSORS];
 140
 141   sim_state_base base;
 142 };
 143
 144 #endif