sim/sh64/sim-if.c

   1 /* Main simulator entry points specific to the SH5.
   2    Copyright (C) 2000-2016 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "libiberty.h"
  22 #include "bfd.h"
  23 #include "sim-main.h"
  24 #ifdef HAVE_STDLIB_H
  25 #include <stdlib.h>
  26 #endif
  27 #include "sim-options.h"
  28 #include "dis-asm.h"
  29
  30 static void free_state (SIM_DESC);
  31
  32 /* Since we don't build the cgen-opcode table, we use a wrapper around
  33    the existing disassembler from libopcodes. */
  34 static CGEN_DISASSEMBLER sh64_disassemble_insn;
  35 \f
  36 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  37
  38 static void
  39 free_state (SIM_DESC sd)
  40 {
  41   if (STATE_MODULES (sd) != NULL)
  42     sim_module_uninstall (sd);
  43   sim_cpu_free_all (sd);
  44   sim_state_free (sd);
  45 }
  46
  47 /* Create an instance of the simulator.  */
  48
  49 SIM_DESC
  50 sim_open (kind, callback, abfd, argv)
  51      SIM_OPEN_KIND kind;
  52      host_callback *callback;
  53      struct bfd *abfd;
  54      char **argv;
  55 {
  56   char c;
  57   int i;
  58   SIM_DESC sd = sim_state_alloc (kind, callback);
  59
  60   /* The cpu data is kept in a separately allocated chunk of memory.  */
  61   if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
  62     {
  63       free_state (sd);
  64       return 0;
  65     }
  66
  67 #if 0 /* FIXME: pc is in mach-specific struct */
  68   /* FIXME: watchpoints code shouldn't need this */
  69   {
  70     SIM_CPU *current_cpu = STATE_CPU (sd, 0);
  71     STATE_WATCHPOINTS (sd)->pc = &(PC);
  72     STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
  73   }
  74 #endif
  75
  76   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
  77     {
  78       free_state (sd);
  79       return 0;
  80     }
  81
  82   /* getopt will print the error message so we just have to exit if this fails.
  83      FIXME: Hmmm...  in the case of gdb we need getopt to call
  84      print_filtered.  */
  85   if (sim_parse_args (sd, argv) != SIM_RC_OK)
  86     {
  87       free_state (sd);
  88       return 0;
  89     }
  90
  91   /* Allocate core managed memory if none specified by user.
  92      Use address 4 here in case the user wanted address 0 unmapped.  */
  93   if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
  94     sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE);
  95
  96   /* Add a small memory region way up in the address space to handle
  97      writes to invalidate an instruction cache line.  This is used for
  98      trampolines.  Since we don't simulate the cache, this memory just
  99      avoids bus errors.  64K ought to do. */
 100   sim_do_command (sd," memory region 0xf0000000,0x10000");
 101
 102   /* check for/establish the reference program image */
 103   if (sim_analyze_program (sd,
 104                            (STATE_PROG_ARGV (sd) != NULL
 105                             ? *STATE_PROG_ARGV (sd)
 106                             : NULL),
 107                            abfd) != SIM_RC_OK)
 108     {
 109       free_state (sd);
 110       return 0;
 111     }
 112
 113   /* Establish any remaining configuration options.  */
 114   if (sim_config (sd) != SIM_RC_OK)
 115     {
 116       free_state (sd);
 117       return 0;
 118     }
 119
 120   if (sim_post_argv_init (sd) != SIM_RC_OK)
 121     {
 122       free_state (sd);
 123       return 0;
 124     }
 125
 126   /* Open a copy of the cpu descriptor table.  */
 127   {
 128     CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
 129                                               CGEN_ENDIAN_BIG);
 130
 131     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 132       {
 133         SIM_CPU *cpu = STATE_CPU (sd, i);
 134         CPU_CPU_DESC (cpu) = cd;
 135         CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn;
 136       }
 137   }
 138
 139   /* Clear idesc table pointers for good measure. */
 140   sh64_idesc_media = sh64_idesc_compact = NULL;
 141
 142   /* Initialize various cgen things not done by common framework.
 143      Must be done after sh_cgen_cpu_open.  */
 144   cgen_init (sd);
 145
 146   return sd;
 147 }
 148 \f
 149 SIM_RC
 150 sim_create_inferior (sd, abfd, argv, envp)
 151      SIM_DESC sd;
 152      struct bfd *abfd;
 153      char **argv;
 154      char **envp;
 155 {
 156   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
 157   SIM_ADDR addr;
 158
 159   if (abfd != NULL)
 160     addr = bfd_get_start_address (abfd);
 161   else
 162     addr = 0;
 163   sim_pc_set (current_cpu, addr);
 164
 165   /* Standalone mode (i.e. `run`) will take care of the argv for us in
 166      sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
 167      with `gdb`), we need to handle it because the user can change the
 168      argv on the fly via gdb's 'run'.  */
 169   if (STATE_PROG_ARGV (sd) != argv)
 170     {
 171       freeargv (STATE_PROG_ARGV (sd));
 172       STATE_PROG_ARGV (sd) = dupargv (argv);
 173     }
 174
 175   return SIM_RC_OK;
 176 }
 177 \f
 178 /* Disassemble an instruction.  */
 179
 180 static void
 181 sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
 182                        const ARGBUF *abuf, IADDR pc, char *buf)
 183 {
 184   struct disassemble_info disasm_info;
 185   SFILE sfile;
 186   SIM_DESC sd = CPU_STATE (cpu);
 187
 188   sfile.buffer = sfile.current = buf;
 189   INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
 190                          (fprintf_ftype) sim_disasm_sprintf);
 191
 192   disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd));
 193   disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd));
 194   disasm_info.endian =
 195     (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
 196      : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
 197      : BFD_ENDIAN_UNKNOWN);
 198   disasm_info.read_memory_func = sim_disasm_read_memory;
 199   disasm_info.memory_error_func = sim_disasm_perror_memory;
 200   disasm_info.application_data = (PTR) cpu;
 201
 202   if (sh64_h_ism_get (cpu) == ISM_MEDIA)
 203     print_insn_sh64x_media (pc, &disasm_info);
 204   else
 205     print_insn_sh (pc, &disasm_info);
 206 }