Tweak last entry.
[deliverable/binutils-gdb.git] / sim / testsuite / ChangeLog
1 Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com>
2
3 * config/default.exp (CC,SIM): Delete.
4 start-sanitize-sky
5 * sim/sky/sky-defs.tcl (LDSCRIPT,SIM): Delete.
6 (run_trc_test): Use sim_compile, sim_run. Only delete temp files
7 if testcase passed.
8 (run_brn_test): Ditto.
9 * sim/sky/sky.exp: Add runtest_file_p support. Don't print
10 unsupported message if not sky.
11 * sim/sky/sky_sce.exp: Likewise.
12 end-sanitize-sky
13
14 * lib/sim-defs.exp (sim_run): Fix handling of output redirection.
15 New arg prog_opts. All callers updated.
16
17 Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com>
18
19 * Makefile.in: Made "check" the target of two
20 dependencies (test1, test2) so that test2 get a chance to
21 run even when test1 failed if "make -k check" is used.
22
23 Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com>
24
25 * lib/sim-defs.exp (sim_version): Simplify.
26 (sim_run): Implement.
27 (run_sim_test): Use sim_run.
28 (sim_compile): New proc.
29
30 Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com>
31
32 start-sanitize-sky
33 * configure.in (testdir): Don't use old sky test directory.
34 * configure: Regenerated
35 * sky/Makefile.in: swallow stderr on buggy tests
36 end-sanitize-sky
37 * config/default.exp: Added C compiler settings.
38
39 Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com>
40
41 * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
42
43 Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
44
45 * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
46 try all machs.
47
48 * sim/m32r/addx.cgs: Test (-1)+(-1)+1.
49
50 Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
51
52 * sim/m32r/mv[ft]achi.cgs: Fix expected result
53 (sign extension of top 8 bits).
54 start-sanitize-m32rx
55 * sim/m32r/mv[ft]achi-a.cgs: Ditto.
56 end-sanitize-m32rx
57
58 start-sanitize-m32rx
59 Tue Apr 14 14:06:34 1998 Doug Evans <devans@canuck.cygnus.com>
60
61 * sim/m32r/maclh1.cgs: Fix testcase.
62 * sim/m32r/maclh1-2.cgs: New testcase.
63
64 Tue Mar 3 19:09:09 1998 Doug Evans <devans@canuck.cygnus.com>
65
66 * sim/m32r/sat.cgs: Change sath to sat.
67
68 end-sanitize-m32rx
69 Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
70
71 * Makefile.in (RUNTEST): Fix path to runtest.
72
73 start-sanitize-sky
74 Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com>
75
76 * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf
77 target.
78 * configure: Regenerate.
79 end-sanitize-sky
80
81 Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
82
83 * sim/m32r/unlock.cgs: Fixed test.
84 * sim/m32r/mvfc.cgs: Fixed test.
85 * sim/m32r/remu.cgs: Fixed test.
86
87 * sim/m32r/bnc24.cgs: Test long BNC instruction.
88 * sim/m32r/bnc8.cgs: Test short BNC instruction.
89 * sim/m32r/ld-plus.cgs: Test LD instruction.
90 * sim/m32r/macwhi.cgs: Test MACWHI instruction.
91 * sim/m32r/macwlo.cgs: Test MACWLO instruction.
92 * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
93 * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
94 * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
95 * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
96 * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
97 * sim/m32r/addv.cgs: Test ADDV instruction.
98 * sim/m32r/addv3.cgs: Test ADDV3 instruction.
99 * sim/m32r/addx.cgs: Test ADDX instruction.
100 * sim/m32r/lock.cgs: Test LOCK instruction.
101 * sim/m32r/neg.cgs: Test NEG instruction.
102 * sim/m32r/not.cgs: Test NOT instruction.
103 * sim/m32r/unlock.cgs: Test UNLOCK instruction.
104 start-sanitize-m32rx
105 * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction.
106 * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO instruction.
107 * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction.
108 * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction.
109 end-sanitize-m32rx
110 Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
111
112 * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
113 address into a general register.
114
115 * sim/m32r/or3.cgs: Test OR3 instruction.
116 * sim/m32r/rach.cgs: Test RACH instruction.
117 * sim/m32r/rem.cgs: Test REM instruction.
118 * sim/m32r/sub.cgs: Test SUB instruction.
119 * sim/m32r/mv.cgs: Test MV instruction.
120 * sim/m32r/mul.cgs: Test MUL instruction.
121 * sim/m32r/bl24.cgs: Test long BL instruction.
122 * sim/m32r/bl8.cgs: Test short BL instruction.
123 * sim/m32r/blez.cgs: Test BLEZ instruction.
124 * sim/m32r/bltz.cgs: Test BLTZ instruction.
125 * sim/m32r/bne.cgs: Test BNE instruction.
126 * sim/m32r/bnez.cgs: Test BNEZ instruction.
127 * sim/m32r/bra24.cgs: Test long BRA instruction.
128 * sim/m32r/bra8.cgs: Test short BRA instruction.
129 * sim/m32r/jl.cgs: Test JL instruction.
130 * sim/m32r/or.cgs: Test OR instruction.
131 * sim/m32r/jmp.cgs: Test JMP instruction.
132 * sim/m32r/and.cgs: Test AND instruction.
133 * sim/m32r/and3.cgs: Test AND3 instruction.
134 * sim/m32r/beq.cgs: Test BEQ instruction.
135 * sim/m32r/beqz.cgs: Test BEQZ instruction.
136 * sim/m32r/bgez.cgs: Test BGEZ instruction.
137 * sim/m32r/bgtz.cgs: Test BGTZ instruction.
138 * sim/m32r/cmp.cgs: Test CMP instruction.
139 * sim/m32r/cmpi.cgs: Test CMPI instruction.
140 * sim/m32r/cmpu.cgs: Test CMPU instruction.
141 * sim/m32r/cmpui.cgs: Test CMPUI instruction.
142 * sim/m32r/div.cgs: Test DIV instruction.
143 * sim/m32r/divu.cgs: Test DIVU instruction.
144 * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
145 * sim/m32r/sll.cgs: Test SLL instruction.
146 * sim/m32r/sll3.cgs: Test SLL3 instruction.
147 * sim/m32r/slli.cgs: Test SLLI instruction.
148 * sim/m32r/sra.cgs: Test SRA instruction.
149 * sim/m32r/sra3.cgs: Test SRA3 instruction.
150 * sim/m32r/srai.cgs: Test SRAI instruction.
151 * sim/m32r/srl.cgs: Test SRL instruction.
152 * sim/m32r/srl3.cgs: Test SRL3 instruction.
153 * sim/m32r/srli.cgs: Test SRLI instruction.
154 * sim/m32r/xor3.cgs: Test XOR3 instruction.
155 * sim/m32r/xor.cgs: Test XOR instruction.
156 start-sanitize-m32rx
157 * sim/m32r/jnc.cgs: Test JNC instruction.
158 * sim/m32r/jc.cgs: Test JC instruction.
159 * sim/m32r/cmpz.cgs: Test CMPZ instruction.
160 * sim/m32r/bcl24.cgs: Test long version of BCL instruction
161 * sim/m32r/bcl8.cgs: Test short BCL instruction.
162 * sim/m32r/bncl24.cgs: Test long BNCL instruction.
163 * sim/m32r/bncl8.cgs: Test short BNCL instruction.
164 * sim/m32r/divh.cgs: Test DIVH instruction.
165 * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
166 end-sanitize-m32rx
167 Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
168
169 * config/default.exp: New file.
170 * lib/sim-defs.exp: New file.
171 * sim/m32r/*: m32r dejagnu simulator testsuite.
172
173 * Makefile.in (build_alias): Define.
174 (arch): Define.
175 (RUNTEST_FOR_TARGET): Delete.
176 (RUNTEST): Fix.
177 (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
178 (check): Depend on site.exp. Run dejagnu.
179 (site.exp): New target.
180 (cgen): New target.
181 * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
182 (arch): Define from target_cpu.
183 * configure: Regenerate.
184
185 Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
186
187 * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
188 (gen_mask): Ditto.
189
190 * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
191 (calc): Add support for 8 bit version of macros.
192 (main): Add tests for 8 bit versions of macros.
193 (check_sext): Check SEXT of zero clears bits.
194
195 * common/bits-gen.c (main): Generate tests for 8 bit versions of
196 macros.
197
198 Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
199
200 * common/Make-common.in: New file, provide generic rules for
201 running checks.
202
203 Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
204
205 * configure.in (configdirs): Test for the target directory instead
206 of matching on a target.
207
208 start-sanitize-r5900
209 Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com>
210
211 * configure.in (configdirs): Configure mips64vr5900el
212 directory.
213 * configure: Regenerate.
214
215 end-sanitize-r5900
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