sim/testsuite/ChangeLog

   1 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
   2
   3         * sim/m32r/or3.cgs: Test OR3 instruction.
   4         * sim/m32r/rach.cgs: Test RACH instruction.
   5         * sim/m32r/rem.cgs: Test REM instruction.
   6         * sim/m32r/sub.cgs: Test SUB instruction.
   7         * sim/m32r/mv.cgs: Test MV instruction.
   8         * sim/m32r/mul.cgs: Test MUL instruction.
   9         * sim/m32r/bl24.cgs: Test long BL instruction.
  10         * sim/m32r/bl8.cgs: Test short BL instruction.
  11         * sim/m32r/blez.cgs: Test BLEZ instruction.
  12         * sim/m32r/bltz.cgs: Test BLTZ instruction.
  13         * sim/m32r/bne.cgs: Test BNE instruction.
  14         * sim/m32r/bnez.cgs: Test BNEZ instruction.
  15         * sim/m32r/bra24.cgs: Test long BRA instruction.
  16         * sim/m32r/bra8.cgs: Test short BRA instruction.
  17         * sim/m32r/jl.cgs: Test JL instruction.
  18         * sim/m32r/or.cgs: Test OR instruction.
  19         * sim/m32r/jmp.cgs: Test JMP instruction.
  20         * sim/m32r/and.cgs: Test AND instruction.
  21         * sim/m32r/and3.cgs: Test AND3 instruction.
  22         * sim/m32r/beq.cgs: Test BEQ instruction.
  23         * sim/m32r/beqz.cgs: Test BEQZ instruction.
  24         * sim/m32r/bgez.cgs: Test BGEZ instruction.
  25         * sim/m32r/bgtz.cgs: Test BGTZ instruction.
  26         * sim/m32r/cmp.cgs: Test CMP instruction.
  27         * sim/m32r/cmpi.cgs: Test CMPI instruction.
  28         * sim/m32r/cmpu.cgs: Test CMPU instruction.
  29         * sim/m32r/cmpui.cgs: Test CMPUI instruction.
  30         * sim/m32r/div.cgs: Test DIV instruction.
  31         * sim/m32r/divu.cgs: Test DIVU instruction.
  32         * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
  33         * sim/m32r/sll.cgs: Test SLL instruction.
  34         * sim/m32r/sll3.cgs: Test SLL3 instruction.
  35         * sim/m32r/slli.cgs: Test SLLI instruction.
  36         * sim/m32r/sra.cgs: Test SRA instruction.
  37         * sim/m32r/sra3.cgs: Test SRA3 instruction.
  38         * sim/m32r/srai.cgs: Test SRAI instruction.
  39         * sim/m32r/srl.cgs: Test SRL instruction.
  40         * sim/m32r/srl3.cgs: Test SRL3 instruction.
  41         * sim/m32r/srli.cgs: Test SRLI instruction.
  42         * sim/m32r/xor3.cgs: Test XOR3 instruction.
  43         * sim/m32r/xor.cgs: Test XOR instruction.
  44 start-sanitize-m342rx
  45         * sim/m32r/jnc.cgs: Test JNC instruction.
  46         * sim/m32r/jc.cgs: Test JC instruction.
  47         * sim/m32r/cmpz.cgs: Test CMPZ instruction.
  48         * sim/m32r/bcl24.cgs: Test long version of BCL instruction
  49         * sim/m32r/bcl8.cgs: Test short BCL instruction.
  50         * sim/m32r/bncl24.cgs: Test long BNCL instruction.
  51         * sim/m32r/bncl8.cgs: Test short BNCL instruction.
  52         * sim/m32r/divh.cgs: Test DIVH instruction.
  53         * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
  54 end-sanitize-m342rx
  55 Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
  56
  57         * config/default.exp: New file.
  58         * lib/sim-defs.exp: New file.
  59         * sim/m32r/*: m32r dejagnu simulator testsuite.
  60
  61         * Makefile.in (build_alias): Define.
  62         (arch): Define.
  63         (RUNTEST_FOR_TARGET): Delete.
  64         (RUNTEST): Fix.
  65         (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
  66         (check): Depend on site.exp.  Run dejagnu.
  67         (site.exp): New target.
  68         (cgen): New target.
  69         * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
  70         (arch): Define from target_cpu.
  71         * configure: Regenerate.
  72
  73 Wed Sep 17 10:21:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  74
  75         * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
  76         (gen_mask): Ditto.
  77
  78         * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
  79         (calc): Add support for 8 bit version of macros.
  80         (main): Add tests for 8 bit versions of macros.
  81         (check_sext): Check SEXT of zero clears bits.
  82
  83         * common/bits-gen.c (main): Generate tests for 8 bit versions of
  84         macros.
  85
  86 Thu Sep 11 13:04:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  87
  88         * common/Make-common.in: New file, provide generic rules for
  89         running checks.
  90
  91 Mon Sep  1 16:43:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  92
  93         * configure.in (configdirs): Test for the target directory instead
  94         of matching on a target.
  95
  96 start-sanitize-r5900
  97 Tue Jul 15 13:43:20 1997  Andrew Cagney  <cagney@sendai.cygnus.com>
  98
  99         * configure.in (configdirs): Configure mips64vr5900el
 100         directory.
 101         * configure: Regenerate.
 102
 103 end-sanitize-r5900