sim/testsuite/ChangeLog

   1 start-sanitize-m32rx
   2 Tue Apr 14 14:06:34 1998  Doug Evans  <devans@canuck.cygnus.com>
   3
   4         * sim/m32r/maclh1.cgs: Fix testcase.
   5         * sim/m32r/maclh1-2.cgs: New testcase.
   6
   7 Tue Mar  3 19:09:09 1998  Doug Evans  <devans@canuck.cygnus.com>
   8
   9         * sim/m32r/sat.cgs: Change sath to sat.
  10
  11 end-sanitize-m32rx
  12 Wed Feb 25 11:01:17 1998  Doug Evans  <devans@canuck.cygnus.com>
  13
  14         * Makefile.in (RUNTEST): Fix path to runtest.
  15
  16 start-sanitize-sky
  17 Tue Feb 24 19:47:56 1998  Frank Ch. Eigler  <fche@cygnus.com>
  18
  19         * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf
  20         target.
  21         * configure: Regenerate.
  22 end-sanitize-sky
  23
  24 Fri Feb 20 11:00:02 1998  Nick Clifton  <nickc@cygnus.com>
  25
  26         * sim/m32r/unlock.cgs: Fixed test.
  27         * sim/m32r/mvfc.cgs: Fixed test.
  28         * sim/m32r/remu.cgs: Fixed test.
  29
  30         * sim/m32r/bnc24.cgs: Test long BNC instruction.
  31         * sim/m32r/bnc8.cgs: Test short BNC instruction.
  32         * sim/m32r/ld-plus.cgs: Test LD instruction.
  33         * sim/m32r/macwhi.cgs: Test MACWHI instruction.
  34         * sim/m32r/macwlo.cgs: Test MACWLO instruction.
  35         * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
  36         * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
  37         * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
  38         * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
  39         * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
  40         * sim/m32r/addv.cgs: Test ADDV instruction.
  41         * sim/m32r/addv3.cgs: Test ADDV3 instruction.
  42         * sim/m32r/addx.cgs: Test ADDX instruction.
  43         * sim/m32r/lock.cgs: Test LOCK instruction.
  44         * sim/m32r/neg.cgs: Test NEG instruction.
  45         * sim/m32r/not.cgs: Test NOT instruction.
  46         * sim/m32r/unlock.cgs: Test UNLOCK instruction.
  47 start-sanitize-m32rx
  48         * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction.
  49         * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO.cgs instruction.
  50         * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction.
  51         * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction.
  52 end-sanitize-m32rx
  53 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
  54
  55         * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
  56         address into a general register.
  57
  58         * sim/m32r/or3.cgs: Test OR3 instruction.
  59         * sim/m32r/rach.cgs: Test RACH instruction.
  60         * sim/m32r/rem.cgs: Test REM instruction.
  61         * sim/m32r/sub.cgs: Test SUB instruction.
  62         * sim/m32r/mv.cgs: Test MV instruction.
  63         * sim/m32r/mul.cgs: Test MUL instruction.
  64         * sim/m32r/bl24.cgs: Test long BL instruction.
  65         * sim/m32r/bl8.cgs: Test short BL instruction.
  66         * sim/m32r/blez.cgs: Test BLEZ instruction.
  67         * sim/m32r/bltz.cgs: Test BLTZ instruction.
  68         * sim/m32r/bne.cgs: Test BNE instruction.
  69         * sim/m32r/bnez.cgs: Test BNEZ instruction.
  70         * sim/m32r/bra24.cgs: Test long BRA instruction.
  71         * sim/m32r/bra8.cgs: Test short BRA instruction.
  72         * sim/m32r/jl.cgs: Test JL instruction.
  73         * sim/m32r/or.cgs: Test OR instruction.
  74         * sim/m32r/jmp.cgs: Test JMP instruction.
  75         * sim/m32r/and.cgs: Test AND instruction.
  76         * sim/m32r/and3.cgs: Test AND3 instruction.
  77         * sim/m32r/beq.cgs: Test BEQ instruction.
  78         * sim/m32r/beqz.cgs: Test BEQZ instruction.
  79         * sim/m32r/bgez.cgs: Test BGEZ instruction.
  80         * sim/m32r/bgtz.cgs: Test BGTZ instruction.
  81         * sim/m32r/cmp.cgs: Test CMP instruction.
  82         * sim/m32r/cmpi.cgs: Test CMPI instruction.
  83         * sim/m32r/cmpu.cgs: Test CMPU instruction.
  84         * sim/m32r/cmpui.cgs: Test CMPUI instruction.
  85         * sim/m32r/div.cgs: Test DIV instruction.
  86         * sim/m32r/divu.cgs: Test DIVU instruction.
  87         * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
  88         * sim/m32r/sll.cgs: Test SLL instruction.
  89         * sim/m32r/sll3.cgs: Test SLL3 instruction.
  90         * sim/m32r/slli.cgs: Test SLLI instruction.
  91         * sim/m32r/sra.cgs: Test SRA instruction.
  92         * sim/m32r/sra3.cgs: Test SRA3 instruction.
  93         * sim/m32r/srai.cgs: Test SRAI instruction.
  94         * sim/m32r/srl.cgs: Test SRL instruction.
  95         * sim/m32r/srl3.cgs: Test SRL3 instruction.
  96         * sim/m32r/srli.cgs: Test SRLI instruction.
  97         * sim/m32r/xor3.cgs: Test XOR3 instruction.
  98         * sim/m32r/xor.cgs: Test XOR instruction.
  99 start-sanitize-m32rx
 100         * sim/m32r/jnc.cgs: Test JNC instruction.
 101         * sim/m32r/jc.cgs: Test JC instruction.
 102         * sim/m32r/cmpz.cgs: Test CMPZ instruction.
 103         * sim/m32r/bcl24.cgs: Test long version of BCL instruction
 104         * sim/m32r/bcl8.cgs: Test short BCL instruction.
 105         * sim/m32r/bncl24.cgs: Test long BNCL instruction.
 106         * sim/m32r/bncl8.cgs: Test short BNCL instruction.
 107         * sim/m32r/divh.cgs: Test DIVH instruction.
 108         * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
 109 end-sanitize-m32rx
 110 Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
 111
 112         * config/default.exp: New file.
 113         * lib/sim-defs.exp: New file.
 114         * sim/m32r/*: m32r dejagnu simulator testsuite.
 115
 116         * Makefile.in (build_alias): Define.
 117         (arch): Define.
 118         (RUNTEST_FOR_TARGET): Delete.
 119         (RUNTEST): Fix.
 120         (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
 121         (check): Depend on site.exp.  Run dejagnu.
 122         (site.exp): New target.
 123         (cgen): New target.
 124         * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
 125         (arch): Define from target_cpu.
 126         * configure: Regenerate.
 127
 128 Wed Sep 17 10:21:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 129
 130         * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
 131         (gen_mask): Ditto.
 132
 133         * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
 134         (calc): Add support for 8 bit version of macros.
 135         (main): Add tests for 8 bit versions of macros.
 136         (check_sext): Check SEXT of zero clears bits.
 137
 138         * common/bits-gen.c (main): Generate tests for 8 bit versions of
 139         macros.
 140
 141 Thu Sep 11 13:04:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 142
 143         * common/Make-common.in: New file, provide generic rules for
 144         running checks.
 145
 146 Mon Sep  1 16:43:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 147
 148         * configure.in (configdirs): Test for the target directory instead
 149         of matching on a target.
 150
 151 start-sanitize-r5900
 152 Tue Jul 15 13:43:20 1997  Andrew Cagney  <cagney@sendai.cygnus.com>
 153
 154         * configure.in (configdirs): Configure mips64vr5900el
 155         directory.
 156         * configure: Regenerate.
 157
 158 end-sanitize-r5900