1 //Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp
2 // Spec Reference: c_ldstpmod load dreg lo & hi
5 .include "testutils.inc"
24 I1 = P3; P3 = I0; I3 = SP; SP = I2;
25 loadsym p5, DATA_ADDR_1, 0x00;
28 R0.L = W [ P5 ++ P1 ];
29 R1.L = W [ P5 ++ P1 ];
30 R2.L = W [ P5 ++ P2 ];
31 R3.L = W [ P5 ++ P3 ];
32 R4.L = W [ P5 ++ P4 ];
33 R5.L = W [ P5 ++ SP ];
34 R6.L = W [ P5 ++ FP ];
35 CHECKREG r0, 0x00000203;
36 CHECKREG r1, 0x00000001;
37 CHECKREG r2, 0x00000607;
38 CHECKREG r3, 0x00000405;
39 CHECKREG r4, 0x00000A0B;
40 CHECKREG r5, 0x00000809;
41 CHECKREG r6, 0x00000E0F;
50 I1 = P3; P3 = I0; I3 = SP; SP = I2;
51 loadsym p1, DATA_ADDR_2, 0x00;
54 R0.H = W [ P1 ++ P5 ];
55 R1.H = W [ P1 ++ P2 ];
56 R2.H = W [ P1 ++ P2 ];
57 R3.H = W [ P1 ++ P3 ];
58 R4.H = W [ P1 ++ P4 ];
59 R5.H = W [ P1 ++ SP ];
60 R6.H = W [ P1 ++ FP ];
61 CHECKREG r0, 0x22230203;
62 CHECKREG r1, 0x22230001;
63 CHECKREG r2, 0x20210607;
64 CHECKREG r3, 0x26270405;
65 CHECKREG r4, 0x24250A0B;
66 CHECKREG r5, 0x2A2B0809;
67 CHECKREG r6, 0x28290E0F;
76 I1 = P3; P3 = I0; I3 = SP; SP = I2;
77 loadsym p2, DATA_ADDR_2, 0x02;
80 R0.L = W [ P2 ++ P5 ];
81 R0.H = W [ P2 ++ P1 ];
82 R1.L = W [ P2 ++ P1 ];
83 R1.H = W [ P2 ++ P3 ];
84 R2.H = W [ P2 ++ P4 ];
85 R2.L = W [ P2 ++ SP ];
86 R3.L = W [ P2 ++ FP ];
87 CHECKREG r0, 0x26272021;
88 CHECKREG r1, 0x2A2B2425;
89 CHECKREG r2, 0x28292E2F;
90 CHECKREG r3, 0x26272C2D;
91 CHECKREG r4, 0x24250A0B;
92 CHECKREG r5, 0x2A2B0809;
93 CHECKREG r6, 0x28290E0F;
102 I1 = P3; P3 = I0; I3 = SP; SP = I2;
103 loadsym i1, DATA_ADDR_3, 0x00;
106 R3.L = W [ P3 ++ P5 ];
107 R3.H = W [ P3 ++ P1 ];
108 R4.L = W [ P3 ++ P2 ];
109 R5.H = W [ P3 ++ P1 ];
110 R5.L = W [ P3 ++ P4 ];
111 R6.H = W [ P3 ++ SP ];
112 R6.L = W [ P3 ++ FP ];
113 CHECKREG r0, 0x26272021;
114 CHECKREG r1, 0x2A2B2425;
115 CHECKREG r2, 0x28292E2F;
116 CHECKREG r3, 0x40414243;
117 CHECKREG r4, 0x24254647;
118 CHECKREG r5, 0x44454A4B;
119 CHECKREG r6, 0x48494E4F;
128 I1 = P3; P3 = I0; I3 = SP; SP = I2;
129 loadsym p4, DATA_ADDR_4, 0x00;
132 R0.H = W [ P4 ++ P5 ];
133 R0.L = W [ P4 ++ P1 ];
134 R1.L = W [ P4 ++ P2 ];
135 R1.H = W [ P4 ++ P3 ];
136 R2.H = W [ P4 ++ P4 ];
137 R3.L = W [ P4 ++ SP ];
138 R3.H = W [ P4 ++ FP ];
139 CHECKREG r0, 0x62636061;
140 CHECKREG r1, 0x64656667;
141 CHECKREG r2, 0x6A6B2E2F;
142 CHECKREG r3, 0x68696A6B;
143 CHECKREG r4, 0x24254647;
144 CHECKREG r5, 0x44454A4B;
145 CHECKREG r6, 0x48494E4F;
154 I1 = P3; P3 = I0; I3 = SP; SP = I2;
155 loadsym fp, DATA_ADDR_5, 0x00;
158 R0.H = W [ FP ++ P5 ];
159 R1.L = W [ FP ++ P1 ];
160 R2.H = W [ FP ++ P2 ];
161 R3.H = W [ FP ++ P3 ];
162 R4.L = W [ FP ++ P4 ];
163 R5.H = W [ FP ++ SP ];
164 R6.L = W [ FP ++ P1 ];
165 CHECKREG r0, 0x82836061;
166 CHECKREG r1, 0x64658081;
167 CHECKREG r2, 0x86872E2F;
168 CHECKREG r3, 0x84856A6B;
169 CHECKREG r4, 0x24258A8B;
170 CHECKREG r5, 0x88894A4B;
171 CHECKREG r6, 0x48498E8F;
180 I1 = P3; P3 = I0; I3 = SP; SP = I2;
181 loadsym i3, DATA_ADDR_6, 0x00;
184 R0.L = W [ SP ++ P5 ];
185 R1.H = W [ SP ++ P1 ];
186 R2.H = W [ SP ++ P2 ];
187 R3.L = W [ SP ++ P3 ];
188 R4.H = W [ SP ++ P4 ];
189 R5.L = W [ SP ++ P5 ];
190 R6.H = W [ SP ++ FP ];
191 CHECKREG r0, 0x82830203;
192 CHECKREG r1, 0x02038081;
193 CHECKREG r2, 0x00012E2F;
194 CHECKREG r3, 0x84850607;
195 CHECKREG r4, 0x04058A8B;
196 CHECKREG r5, 0x88890A0B;
197 CHECKREG r6, 0x0A0B8E8F;
202 // Pre-load memory with known data
203 // More data is defined than will actually be used