sim/testsuite/sim/bfin/c_alu2op_conv_mix.s

   1 //Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp
   2 // Spec Reference: alu2op convert mix
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x00789abc;
  11 imm32 r1, 0x12345678;
  12 imm32 r2, 0x23456789;
  13 imm32 r3, 0x3456789a;
  14 imm32 r4, 0x856789ab;
  15 imm32 r5, 0x96789abc;
  16 imm32 r6, 0xa789abcd;
  17 imm32 r7, 0xb89abcde;
  18 R0 = R0.B (X);
  19 R1 = R1.L (X);
  20 R2 = R2.L (Z);
  21 R3 = R3.B (X);
  22 R4 = R4.B (Z);
  23 R5 = - R5;
  24 R6 = ~ R6;
  25 R7 = R7.L (X);
  26 CHECKREG r0, 0xFFFFFFBC;
  27 CHECKREG r1, 0x00005678;
  28 CHECKREG r2, 0x00006789;
  29 CHECKREG r3, 0xFFFFFF9A;
  30 CHECKREG r4, 0x000000AB;
  31 CHECKREG r5, 0x69876544;
  32 CHECKREG r6, 0x58765432;
  33 CHECKREG r7, 0xFFFFBCDE;
  34
  35 imm32 r0, 0x01230002;
  36 imm32 r1, 0x00374659;
  37 imm32 r2, 0x93456789;
  38 imm32 r3, 0xa456789a;
  39 imm32 r4, 0xb56789ab;
  40 imm32 r5, 0xc6789abc;
  41 imm32 r6, 0xd789abcd;
  42 imm32 r7, 0xe89abcde;
  43 R6 = R0.B (X);
  44 R7 = R1.L (X);
  45 R0 = R2.L (Z);
  46 R1 = R3.B (X);
  47 R2 = R4.B (Z);
  48 R3 = - R5;
  49 R4 = ~ R6;
  50 R5 = R7.L (X);
  51 CHECKREG r0, 0x00006789;
  52 CHECKREG r1, 0xFFFFFF9A;
  53 CHECKREG r2, 0x000000AB;
  54 CHECKREG r3, 0x39876544;
  55 CHECKREG r4, 0xFFFFFFFD;
  56 CHECKREG r5, 0x00004659;
  57 CHECKREG r6, 0x00000002;
  58 CHECKREG r7, 0x00004659;
  59
  60 imm32 r0, 0x51230002;
  61 imm32 r1, 0x12345678;
  62 imm32 r2, 0x91203450;
  63 imm32 r3, 0x3456789a;
  64 imm32 r4, 0x956789ab;
  65 imm32 r5, 0x86789abc;
  66 imm32 r6, 0xa789abcd;
  67 imm32 r7, 0x789abcde;
  68 R5 = R0.B (X);
  69 R6 = R1.L (X);
  70 R7 = R2.L (Z);
  71 R0 = R3.B (X);
  72 R1 = R4.B (Z);
  73 R2 = - R5;
  74 R3 = ~ R6;
  75 R4 = R7.L (X);
  76 CHECKREG r0, 0xFFFFFF9A;
  77 CHECKREG r1, 0x000000AB;
  78 CHECKREG r2, 0xFFFFFFFE;
  79 CHECKREG r3, 0xFFFFA987;
  80 CHECKREG r4, 0x00003450;
  81 CHECKREG r5, 0x00000002;
  82 CHECKREG r6, 0x00005678;
  83 CHECKREG r7, 0x00003450;
  84
  85 imm32 r0, 0x01230002;
  86 imm32 r1, 0x82345678;
  87 imm32 r2, 0x93456789;
  88 imm32 r3, 0x00000000;
  89 imm32 r4, 0xb56789ab;
  90 imm32 r5, 0xc6789abc;
  91 imm32 r6, 0xd789abcd;
  92 imm32 r7, 0xe89abcde;
  93 R4 = R0.B (X);
  94 R5 = R1.L (X);
  95 R6 = R2.L (Z);
  96 R7 = R3.B (X);
  97 R0 = R4.B (Z);
  98 R1 = - R5;
  99 R2 = ~ R6;
 100 R3 = R7.L (X);
 101 CHECKREG r0, 0x00000002;
 102 CHECKREG r1, 0xFFFFA988;
 103 CHECKREG r2, 0xFFFF9876;
 104 CHECKREG r3, 0x00000000;
 105 CHECKREG r4, 0x00000002;
 106 CHECKREG r5, 0x00005678;
 107 CHECKREG r6, 0x00006789;
 108 CHECKREG r7, 0x00000000;
 109
 110 imm32 r0, 0xadf00001;
 111 imm32 r1, 0x12345678;
 112 imm32 r2, 0x23456789;
 113 imm32 r3, 0x3456789a;
 114 imm32 r4, 0x00000000;
 115 imm32 r5, 0x96789abc;
 116 imm32 r6, 0xa789abcd;
 117 imm32 r7, 0xb89abcde;
 118 R3 = R0.B (X);
 119 R4 = R1.L (X);
 120 R5 = R2.L (Z);
 121 R6 = R3.B (X);
 122 R7 = R4.B (Z);
 123 R0 = - R5;
 124 R1 = ~ R6;
 125 R2 = R7.L (X);
 126 CHECKREG r0, 0xFFFF9877;
 127 CHECKREG r1, 0xFFFFFFFE;
 128 CHECKREG r2, 0x00000078;
 129 CHECKREG r3, 0x00000001;
 130 CHECKREG r4, 0x00005678;
 131 CHECKREG r5, 0x00006789;
 132 CHECKREG r6, 0x00000001;
 133 CHECKREG r7, 0x00000078;
 134
 135 imm32 r0, 0x01230002;
 136 imm32 r1, 0x00000000;
 137 imm32 r2, 0x93456789;
 138 imm32 r3, 0xa456789a;
 139 imm32 r4, 0xb56789ab;
 140 imm32 r5, 0x54238900;
 141 imm32 r6, 0xd789abcd;
 142 imm32 r7, 0xe89abcde;
 143 R2 = R0.B (X);
 144 R3 = R1.L (X);
 145 R4 = R2.L (Z);
 146 R5 = R3.B (X);
 147 R6 = R4.B (Z);
 148 R7 = - R5;
 149 R0 = ~ R6;
 150 R1 = R7.L (X);
 151 CHECKREG r0, 0xFFFFFFFD;
 152 CHECKREG r1, 0x00000000;
 153 CHECKREG r2, 0x00000002;
 154 CHECKREG r3, 0x00000000;
 155 CHECKREG r4, 0x00000002;
 156 CHECKREG r5, 0x00000000;
 157 CHECKREG r6, 0x00000002;
 158 CHECKREG r7, 0x00000000;
 159
 160 imm32 r0, 0x51230002;
 161 imm32 r1, 0x12345678;
 162 imm32 r2, 0x00000000;
 163 imm32 r3, 0x3456789a;
 164 imm32 r4, 0x956789ab;
 165 imm32 r5, 0x86789abc;
 166 imm32 r6, 0x00000000;
 167 imm32 r7, 0x789abcde;
 168 R1 = R0.B (X);
 169 R2 = R1.L (X);
 170 R3 = R2.L (Z);
 171 R4 = R3.B (X);
 172 R5 = R4.B (Z);
 173 R6 = - R5;
 174 R0 = ~ R6;
 175 R7 = R7.L (X);
 176 CHECKREG r0, 0x00000001;
 177 CHECKREG r1, 0x00000002;
 178 CHECKREG r2, 0x00000002;
 179 CHECKREG r3, 0x00000002;
 180 CHECKREG r4, 0x00000002;
 181 CHECKREG r5, 0x00000002;
 182 CHECKREG r6, 0xFFFFFFFE;
 183 CHECKREG r7, 0xFFFFBCDE;
 184
 185
 186 pass