sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s

   1 //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp
   2 // Spec Reference:  comp3op   pregs + pregs << 2
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         imm32 p1, 0x89ab1def;
   9         imm32 p2, 0x56781abc;
  10         imm32 p3, 0xdef01234;
  11         imm32 p4, 0x23451899;
  12         imm32 p5, 0x78911345;
  13         imm32 sp, 0x98761432;
  14         imm32 fp, 0x12341678;
  15         P1 = P1 + ( P1 << 2 );
  16         P2 = P1 + ( P2 << 2 );
  17         P3 = P1 + ( P3 << 2 );
  18         P4 = P1 + ( P4 << 2 );
  19         P5 = P1 + ( P5 << 2 );
  20         SP = P1 + ( SP << 2 );
  21         FP = P1 + FP;
  22         CHECKREG p1, 0xB05795AB;
  23         CHECKREG p2, 0x0A38009B;
  24         CHECKREG p3, 0x2C17DE7B;
  25         CHECKREG p4, 0x3D6BF80F;
  26         CHECKREG p5, 0x929BE2BF;
  27         CHECKREG sp, 0x122FE673;
  28         CHECKREG fp, 0xC28BAC23;
  29
  30         imm32 p1, 0x89abcd2f;
  31         imm32 p2, 0x56789a2c;
  32         imm32 p3, 0xdef01224;
  33         imm32 p4, 0x23456829;
  34         imm32 p5, 0x78912325;
  35         imm32 sp, 0x98765422;
  36         imm32 fp, 0x12345628;
  37         P1 = P2 + ( P1 << 2 );
  38         P2 = P2 + ( P2 << 2 );
  39         P3 = P2 + ( P3 << 2 );
  40         P4 = P2 + ( P4 << 2 );
  41         P5 = P2 + ( P5 << 2 );
  42         SP = P2 + ( SP << 2 );
  43         FP = P2 + ( FP << 2 );
  44         CHECKREG p1, 0x7D27CEE8;
  45         CHECKREG p2, 0xB05B02DC;
  46         CHECKREG p3, 0x2C1B4B6C;
  47         CHECKREG p4, 0x3D70A380;
  48         CHECKREG p5, 0x929F8F70;
  49         CHECKREG sp, 0x12345364;
  50         CHECKREG fp, 0xF92C5B7C;
  51
  52         imm32 p1, 0x89abcde3;
  53         imm32 p2, 0x56789ab3;
  54         imm32 p3, 0xdef01233;
  55         imm32 p4, 0x23456893;
  56         imm32 p5, 0x78912343;
  57         imm32 sp, 0x98765433;
  58         imm32 fp, 0x12345673;
  59         P1 = P3 + ( P1 << 2 );
  60         P2 = P3 + ( P2 << 2 );
  61         P3 = P3 + ( P3 << 2 );
  62         P4 = P3 + ( P4 << 2 );
  63         P5 = P3 + ( P5 << 2 );
  64         SP = P3 + ( SP << 2 );
  65         FP = P3 + ( FP << 2 );
  66         CHECKREG p1, 0x059F49BF;
  67         CHECKREG p2, 0x38D27CFF;
  68         CHECKREG p3, 0x5AB05AFF;
  69         CHECKREG p4, 0xE7C5FD4B;
  70         CHECKREG p5, 0x3CF4E80B;
  71         CHECKREG sp, 0xBC89ABCB;
  72         CHECKREG fp, 0xA381B4CB;
  73
  74         imm32 p1, 0x49abcdef;
  75         imm32 p2, 0x46789abc;
  76         imm32 p3, 0x4ef01234;
  77         imm32 p4, 0x43456899;
  78         imm32 p5, 0x48912345;
  79         imm32 sp, 0x48765432;
  80         imm32 fp, 0x42345678;
  81         P1 = P4 + ( P1 << 2 );
  82         P2 = P4 + ( P2 << 2 );
  83         P3 = P4 + ( P3 << 2 );
  84         P4 = P4 + ( P4 << 2 );
  85         P5 = P4 + ( P5 << 2 );
  86         SP = P4 + ( SP << 2 );
  87         FP = P4 + ( FP << 2 );
  88         CHECKREG p1, 0x69F4A055;
  89         CHECKREG p2, 0x5D27D389;
  90         CHECKREG p3, 0x7F05B169;
  91         CHECKREG p4, 0x505B0AFD;
  92         CHECKREG p5, 0x729F9811;
  93         CHECKREG sp, 0x72345BC5;
  94         CHECKREG fp, 0x592C64DD;
  95
  96         imm32 p1, 0x85abcdef;
  97         imm32 p2, 0x55789abc;
  98         imm32 p3, 0xd5f01234;
  99         imm32 p4, 0x25456899;
 100         imm32 p5, 0x75912345;
 101         imm32 sp, 0x95765432;
 102         imm32 fp, 0x15345678;
 103         P1 = P5 + ( P1 << 2 );
 104         P2 = P5 + ( P2 << 2 );
 105         P3 = P5 + ( P3 << 2 );
 106         P4 = P5 + ( P4 << 2 );
 107         P5 = P5 + ( P5 << 2 );
 108         SP = P5 + ( SP << 2 );
 109         FP = P5 + ( FP << 2 );
 110         CHECKREG p1, 0x8C405B01;
 111         CHECKREG p2, 0xCB738E35;
 112         CHECKREG p3, 0xCD516C15;
 113         CHECKREG p4, 0x0AA6C5A9;
 114         CHECKREG p5, 0x4BD5B059;
 115         CHECKREG sp, 0xA1AF0121;
 116         CHECKREG fp, 0xA0A70A39;
 117
 118         imm32 p1, 0x89a6cdef;
 119         imm32 p2, 0x56769abc;
 120         imm32 p3, 0xdef61234;
 121         imm32 p4, 0x23466899;
 122         imm32 p5, 0x78962345;
 123         imm32 sp, 0x98765432;
 124         imm32 fp, 0x12365678;
 125         P1 = SP + ( P1 << 2 );
 126         P2 = SP + ( P2 << 2 );
 127         P3 = SP + ( P3 << 2 );
 128         P4 = SP + ( P4 << 2 );
 129         P5 = SP + ( P5 << 2 );
 130         SP = SP + ( SP << 2 );
 131         FP = SP + ( FP << 2 );
 132         CHECKREG p1, 0xBF118BEE;
 133         CHECKREG p2, 0xF250BF22;
 134         CHECKREG p3, 0x144E9D02;
 135         CHECKREG p4, 0x258FF696;
 136         CHECKREG p5, 0x7ACEE146;
 137         CHECKREG sp, 0xFA4FA4FA;
 138         CHECKREG fp, 0x4328FEDA;
 139
 140         imm32 p1, 0x89ab7def;
 141         imm32 p2, 0x56787abc;
 142         imm32 p3, 0xdef07234;
 143         imm32 p4, 0x23457899;
 144         imm32 p5, 0x78917345;
 145         imm32 sp, 0x98767432;
 146         imm32 fp, 0x12345678;
 147         P1 = FP + ( P1 << 2 );
 148         P2 = FP + ( P2 << 2 );
 149         P3 = FP + ( P3 << 2 );
 150         P4 = FP + ( P4 << 2 );
 151         P5 = FP + ( P5 << 2 );
 152         SP = FP + ( SP << 2 );
 153         FP = FP + ( FP << 2 );
 154         CHECKREG p1, 0x38E24E34;
 155         CHECKREG p2, 0x6C164168;
 156         CHECKREG p3, 0x8DF61F48;
 157         CHECKREG p4, 0x9F4A38DC;
 158         CHECKREG p5, 0xF47A238C;
 159         CHECKREG sp, 0x740E2740;
 160         CHECKREG fp, 0x5B05B058;
 161
 162         imm32 p1, 0x29ab1def;
 163         imm32 p2, 0x52781abc;
 164         imm32 p3, 0xde201234;
 165         imm32 p4, 0x23421899;
 166         imm32 p5, 0x78912345;
 167         imm32 sp, 0x98761232;
 168         imm32 fp, 0x12341628;
 169         P1 = P3 + ( P1 << 2 );
 170         P2 = P4 + ( P1 << 2 );
 171         P3 = P5 + ( P1 << 2 );
 172         P4 = SP + ( P1 << 2 );
 173         P5 = FP + ( P1 << 2 );
 174         FP = P1 + ( P1 << 2 );
 175         CHECKREG p1, 0x84CC89F0;
 176         CHECKREG p2, 0x36744059;
 177         CHECKREG p3, 0x8BC34B05;
 178         CHECKREG p4, 0xABA839F2;
 179         CHECKREG p5, 0x25663DE8;
 180         CHECKREG fp, 0x97FEB1B0;
 181
 182         imm32 p1, 0x893bcd2f;
 183         imm32 p2, 0x56739a2c;
 184         imm32 p3, 0x3ef03224;
 185         imm32 p4, 0x23456329;
 186         imm32 p5, 0x78312335;
 187         imm32 sp, 0x98735423;
 188         imm32 fp, 0x12343628;
 189         P1 = P4 + ( P2 << 2 );
 190         P2 = P5 + ( P2 << 2 );
 191         P3 = SP + ( P2 << 2 );
 192         P4 = FP + ( P2 << 2 );
 193         SP = P1 + ( P2 << 2 );
 194         FP = P2 + ( P2 << 2 );
 195         CHECKREG p1, 0x7D13CBD9;
 196         CHECKREG p2, 0xD1FF8BE5;
 197         CHECKREG p3, 0xE07183B7;
 198         CHECKREG p4, 0x5A3265BC;
 199         CHECKREG sp, 0xC511FB6D;
 200         CHECKREG fp, 0x19FDBB79;
 201
 202         imm32 p1, 0x894bcde3;
 203         imm32 p2, 0x56749ab3;
 204         imm32 p3, 0x4ef04233;
 205         imm32 p4, 0x24456493;
 206         imm32 p5, 0x78412344;
 207         imm32 sp, 0x98745434;
 208         imm32 fp, 0x12344673;
 209         P1 = P5 + ( P3 << 2 );
 210         P2 = SP + ( P3 << 2 );
 211         P3 = FP + ( P3 << 2 );
 212         P5 = P1 + ( P3 << 2 );
 213         SP = P2 + ( P3 << 2 );
 214         FP = P3 + ( P3 << 2 );
 215         CHECKREG p1, 0xB4022C10;
 216         CHECKREG p2, 0xD4355D00;
 217         CHECKREG p3, 0x4DF54F3F;
 218         CHECKREG p5, 0xEBD7690C;
 219         CHECKREG sp, 0x0C0A99FC;
 220         CHECKREG fp, 0x85CA8C3B;
 221
 222         imm32 p1, 0x49abc5ef;
 223         imm32 p2, 0x46789a5c;
 224         imm32 p3, 0x4ef01235;
 225         imm32 p4, 0x53456899;
 226         imm32 p5, 0x45912345;
 227         imm32 sp, 0x48565432;
 228         imm32 fp, 0x42355678;
 229         P1 = SP + ( P4 << 2 );
 230         P2 = FP + ( P4 << 2 );
 231         P4 = P1 + ( P4 << 2 );
 232         P5 = P2 + ( P4 << 2 );
 233         SP = P3 + ( P4 << 2 );
 234         FP = P4 + ( P4 << 2 );
 235         CHECKREG p1, 0x956BF696;
 236         CHECKREG p2, 0x8F4AF8DC;
 237         CHECKREG p4, 0xE28198FA;
 238         CHECKREG p5, 0x19515CC4;
 239         CHECKREG sp, 0xD8F6761D;
 240         CHECKREG fp, 0x6C87FCE2;
 241
 242         imm32 p1, 0x85ab6def;
 243         imm32 p2, 0x657896bc;
 244         imm32 p3, 0xd6f01264;
 245         imm32 p4, 0x25656896;
 246         imm32 p5, 0x75962345;
 247         imm32 sp, 0x95766432;
 248         imm32 fp, 0x15345678;
 249         P1 = FP + ( P5 << 2 );
 250         P3 = P1 + ( P5 << 2 );
 251         P4 = P2 + ( P5 << 2 );
 252         P5 = P3 + ( P5 << 2 );
 253         SP = P4 + ( P5 << 2 );
 254         FP = P5 + ( P5 << 2 );
 255         CHECKREG p1, 0xEB8CE38C;
 256         CHECKREG p3, 0xC1E570A0;
 257         CHECKREG p4, 0x3BD123D0;
 258         CHECKREG p5, 0x983DFDB4;
 259         CHECKREG sp, 0x9CC91AA0;
 260         CHECKREG fp, 0xF935F484;
 261
 262         imm32 p1, 0x89a7cdef;
 263         imm32 p2, 0x56767abc;
 264         imm32 p3, 0xdef61734;
 265         imm32 p4, 0x73466879;
 266         imm32 p5, 0x77962347;
 267         imm32 sp, 0x98765432;
 268         imm32 fp, 0x12375678;
 269         P2 = P1 + ( SP << 2 );
 270         P3 = P2 + ( SP << 2 );
 271         P4 = P3 + ( SP << 2 );
 272         P5 = P4 + ( SP << 2 );
 273         SP = P5 + ( SP << 2 );
 274         FP = SP + ( SP << 2 );
 275         CHECKREG p2, 0xEB811EB7;
 276         CHECKREG p3, 0x4D5A6F7F;
 277         CHECKREG p4, 0xAF33C047;
 278         CHECKREG p5, 0x110D110F;
 279         CHECKREG sp, 0x72E661D7;
 280         CHECKREG fp, 0x3E7FE933;
 281
 282         imm32 p1, 0x88ab78ef;
 283         imm32 p2, 0x56887a8c;
 284         imm32 p3, 0x8ef87238;
 285         imm32 p4, 0x28458899;
 286         imm32 p5, 0x78817845;
 287         imm32 sp, 0x98787482;
 288         imm32 fp, 0x12348678;
 289         P1 = P2 + ( FP << 2 );
 290         P2 = P3 + ( FP << 2 );
 291         P3 = P4 + ( FP << 2 );
 292         P4 = P5 + ( FP << 2 );
 293         P5 = SP + ( FP << 2 );
 294         SP = FP + ( FP << 2 );
 295         CHECKREG p1, 0x9F5A946C;
 296         CHECKREG p2, 0xD7CA8C18;
 297         CHECKREG p3, 0x7117A279;
 298         CHECKREG p4, 0xC1539225;
 299         CHECKREG p5, 0xE14A8E62;
 300         CHECKREG sp, 0x5B06A058;
 301
 302         pass