1 //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp
2 // Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0)
6 .include "testutils.inc"
11 ASTAT = R0; // initialize astat
15 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0
17 R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0
19 R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0
22 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0
24 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0
26 CHECKREG r0, 0x00000000;
27 CHECKREG r1, 0x00000000;
28 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
30 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
31 CHECKREG r6, 0x00000000;
36 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0
39 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0
41 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0
43 CHECKREG r0, 0xFFFFFFFF;
44 CHECKREG r1, 0x00000000;
47 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
51 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1
54 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1
57 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0
59 CHECKREG r0, 0x7FFFFFFE;
60 CHECKREG r1, 0x80000000;
61 CHECKREG r2, 0x7FFFFFFF;
62 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
63 CHECKREG r6, (_AC0|_AC0_COPY|_V|_V_COPY|_VS);
64 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
66 // AZ, AN, AC, AV0 for R0
70 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1
73 R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1
76 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0
78 CHECKREG r0, 0x80000001;
79 CHECKREG r1, 0x7FFFFFFF;
80 CHECKREG r2, 0x80000000;
81 CHECKREG r5, (_VS|_AN);
82 CHECKREG r6, (_VS|_V_COPY|_V|_AN);
83 CHECKREG r7, (_VS|_V_COPY|_V|_AC0|_AC0_COPY);
88 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0
90 R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0
92 R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0
95 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0
97 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0
99 CHECKREG r0, 0x00000000;
100 CHECKREG r1, 0x00000000;
101 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
103 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
104 CHECKREG r6, 0x00000000;
110 imm32 r1, 0xffffffff;
111 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0
114 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0
116 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0
118 CHECKREG r0, 0x00000000;
119 CHECKREG r1, 0xFFFFFFFF;
122 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
125 imm32 r1, 0x7fffffff;
126 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1
129 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1
132 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0
134 CHECKREG r0, 0x80000000;
135 CHECKREG r1, 0x7FFFFFFE;
136 CHECKREG r2, 0x7FFFFFFF;
137 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
138 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
139 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
141 // AZ, AN, AC, AV0 for R1
144 imm32 r1, 0x80000000;
145 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1
148 R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1
151 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0
153 CHECKREG r0, 0x7FFFFFFF;
154 CHECKREG r1, 0x80000001;
155 CHECKREG r2, 0x80000000;
156 CHECKREG r5, (_VS|_AN);
157 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
158 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
161 imm32 r2, 0x00000000;
163 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0
165 R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0
167 R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0
170 R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0
172 R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0
174 CHECKREG r1, 0x00000000;
175 CHECKREG r2, 0x00000000;
176 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
178 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
179 CHECKREG r6, 0x00000000;
185 imm32 r2, 0xffffffff;
186 R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0
189 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0
191 R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0
193 CHECKREG r2, 0xFFFFFFFF;
196 CHECKREG r6, 0x00000000;
197 CHECKREG r7, (_AC0|_AC0_COPY);
200 imm32 r2, 0x7fffffff;
201 R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1
204 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1
207 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0
209 CHECKREG r0, 0x80000001;
210 CHECKREG r1, 0x7FFFFFFF;
211 CHECKREG r2, 0x7FFFFFFD;
212 CHECKREG r5, (_AC0|_AC0_COPY|_VS);
213 CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY);
214 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
216 // AZ, AN, AC, AV0 for R2
219 imm32 r2, 0x80000000;
220 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1
223 R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1
226 R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0
228 CHECKREG r0, 0x7FFFFFFE;
229 CHECKREG r1, 0x80000000;
230 CHECKREG r2, 0x80000002;
231 CHECKREG r5, (_VS|_AN);
232 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
233 CHECKREG r7, (_AC0|_AC0_COPY|_VS|_V|_V_COPY);
236 imm32 r3, 0x00000000;
238 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0
240 R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0
242 R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0
245 R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0
247 R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0
249 CHECKREG r0, 0x00000000;
250 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
251 CHECKREG r3, 0x00000000;
253 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
254 CHECKREG r6, 0x00000000;
258 imm32 r3, 0xffffffff;
259 R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0
262 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0
264 R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0
266 CHECKREG r0, 0x00000002;
267 CHECKREG r3, 0xFFFFFFFF;
269 CHECKREG r6, 0x00000000;
270 CHECKREG r7, (_AC0|_AC0_COPY);
273 imm32 r3, 0x7fffffff;
274 R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1
277 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1
280 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0
282 CHECKREG r0, 0x80000002;
283 CHECKREG r1, 0x7FFFFFFF;
284 CHECKREG r3, 0x7FFFFFFC;
285 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
286 CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY);
287 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
289 // AZ, AN, AC, AV0 for R3
292 imm32 r3, 0x80000000;
293 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1
296 R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1
299 R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0
301 CHECKREG r0, 0x7FFFFFFD;
302 CHECKREG r1, 0x80000000;
303 CHECKREG r3, 0x80000003;
304 CHECKREG r5, (_VS|_AN);
305 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
306 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
309 imm32 r4, 0x00000000;
311 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0
313 R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0
315 R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0
318 R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0
320 R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0
322 CHECKREG r1, 0x00000000;
323 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
325 CHECKREG r4, 0x00000000;
326 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
327 CHECKREG r6, 0x00000000;
331 imm32 r4, 0xffffffff;
332 R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0
335 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0
337 R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0
339 CHECKREG r1, 0x00000003;
340 CHECKREG r4, 0xFFFFFFFF;
342 CHECKREG r6, 0x00000000;
343 CHECKREG r7, (_AC0|_AC0_COPY);
346 imm32 r4, 0x7fffffff;
347 R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1
350 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1
353 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0
355 CHECKREG r1, 0x80000003;
356 CHECKREG r2, 0x7FFFFFFF;
357 CHECKREG r4, 0x7FFFFFFB;
358 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
359 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
360 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
362 // AZ, AN, AC, AV0 for R4
365 imm32 r4, 0x80000000;
366 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1
369 R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1
372 R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0
374 CHECKREG r1, 0x7FFFFFFC;
375 CHECKREG r2, 0x80000000;
376 CHECKREG r4, 0x80000004;
377 CHECKREG r5, (_VS|_AN);
378 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
379 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
382 imm32 r5, 0x00000000;
384 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0
386 R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0
388 R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0
391 R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0
393 R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0
395 CHECKREG r0, 0x00000000;
396 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
397 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
399 CHECKREG r5, 0x00000000;
400 CHECKREG r6, 0x00000000;
404 imm32 r5, 0xffffffff;
405 R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0
408 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0
410 R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0
412 CHECKREG r0, 0x00000004;
414 CHECKREG r5, 0xFFFFFFFF;
415 CHECKREG r6, 0x00000000;
416 CHECKREG r7, (_AC0|_AC0_COPY);
419 imm32 r5, 0x7fffffff;
420 R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1
423 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1
426 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0
428 CHECKREG r0, 0x80000004;
429 CHECKREG r2, 0x7FFFFFFF;
430 CHECKREG r4, (_VS|_AC0|_AC0_COPY);
431 CHECKREG r5, 0x7FFFFFFA;
432 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
433 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
435 // AZ, AN, AC, AV0 for R5
438 imm32 r5, 0x80000000;
439 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1
442 R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1
445 R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0
447 CHECKREG r0, 0x7FFFFFFB;
448 CHECKREG r2, 0x80000000;
449 CHECKREG r4, (_VS|_AN);
450 CHECKREG r5, 0x80000005;
451 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
452 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
455 imm32 r6, 0x00000000;
457 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0
459 R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0
461 R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0
464 R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0
466 R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0
468 CHECKREG r0, 0x00000000;
469 CHECKREG r1, 0x00000000;
470 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
472 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
473 CHECKREG r6, 0x00000000;
477 imm32 r6, 0xffffffff;
478 R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0
481 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0
483 R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0
485 CHECKREG r1, 0x00000005;
486 CHECKREG r4, 0x00000000;
488 CHECKREG r6, 0xFFFFFFFF;
489 CHECKREG r7, (_AC0|_AC0_COPY);
492 imm32 r6, 0x7fffffff;
493 R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1
496 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1
499 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0
501 CHECKREG r0, 0x80000005;
502 CHECKREG r1, 0x7FFFFFFF;
503 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
504 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
505 CHECKREG r6, 0x7FFFFFF9;
506 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
508 // AZ, AN, AC, AV0 for R6
511 imm32 r6, 0x80000000;
512 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1
515 R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1
518 R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0
520 CHECKREG r0, 0x7FFFFFFA;
521 CHECKREG r1, 0x80000000;
522 CHECKREG r4, (_VS|_V|_V_COPY|_AN);
523 CHECKREG r5, (_VS|_AN);
524 CHECKREG r6, 0x80000006;
525 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
528 imm32 r7, 0x00000000;
530 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0
532 R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0
534 R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0
537 R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0
539 R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0
541 CHECKREG r0, 0x00000000;
543 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
545 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
546 CHECKREG r6, 0x00000000;
547 CHECKREG r7, 0x00000000;
550 imm32 r7, 0xffffffff;
551 R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0
554 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0
556 R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0
558 CHECKREG r0, 0x00000006;
559 CHECKREG r4, (_AC0|_AC0_COPY);
561 CHECKREG r6, 0x00000000;
562 CHECKREG r7, 0xFFFFFFFF;
565 imm32 r7, 0x7fffffff;
566 R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1
569 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1
572 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0
574 CHECKREG r0, 0x80000006;
575 CHECKREG r1, 0x7FFFFFFF;
576 CHECKREG r4, (_VS|_V|_V_COPY|_AN);
577 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
578 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
579 CHECKREG r7, 0x7FFFFFF8;
581 // AZ, AN, AC, AV0 for R7
584 imm32 r7, 0x80000000;
585 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1
588 R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1
591 R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0
593 CHECKREG r0, 0x7FFFFFF9;
594 CHECKREG r1, 0x80000000;
595 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
596 CHECKREG r5, (_VS|_AN);
597 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
598 CHECKREG r7, 0x80000007;