sim: bfin: import testsuite
[deliverable/binutils-gdb.git] / sim / testsuite / sim / bfin / c_dsp32alu_max.s
1 //Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp
2 // Spec Reference: dsp32alu dregs = max ( dregs, dregs)
3 # mach: bfin
4
5 .include "testutils.inc"
6 start
7
8
9
10
11 imm32 r0, 0x85678911;
12 imm32 r1, 0x9789ab1d;
13 imm32 r2, 0xa4445b15;
14 imm32 r3, 0x46667717;
15 imm32 r4, 0xd567f91b;
16 imm32 r5, 0x6789ab1d;
17 imm32 r6, 0x74445515;
18 imm32 r7, 0x86667777;
19 R0 = MAX ( R0 , R0 );
20 R1 = MAX ( R0 , R1 );
21 R2 = MAX ( R0 , R2 );
22 R3 = MAX ( R0 , R3 );
23 R4 = MAX ( R0 , R4 );
24 R5 = MAX ( R0 , R5 );
25 R6 = MAX ( R0 , R6 );
26 R7 = MAX ( R0 , R7 );
27 CHECKREG r0, 0x85678911;
28 CHECKREG r1, 0x9789AB1D;
29 CHECKREG r2, 0xA4445B15;
30 CHECKREG r3, 0x46667717;
31 CHECKREG r4, 0xD567F91B;
32 CHECKREG r5, 0x6789AB1D;
33 CHECKREG r6, 0x74445515;
34 CHECKREG r7, 0x86667777;
35
36 imm32 r0, 0x9567892b;
37 imm32 r1, 0xa789ab2d;
38 imm32 r2, 0xb4445525;
39 imm32 r3, 0xc6667727;
40 imm32 r4, 0xd8889929;
41 imm32 r5, 0xeaaabb2b;
42 imm32 r6, 0xfcccdd2d;
43 imm32 r7, 0x0eeeffff;
44 R0 = MAX ( R1 , R0 );
45 R1 = MAX ( R1 , R1 );
46 R2 = MAX ( R1 , R2 );
47 R3 = MAX ( R1 , R3 );
48 R4 = MAX ( R1 , R4 );
49 R5 = MAX ( R1 , R5 );
50 R6 = MAX ( R1 , R6 );
51 R7 = MAX ( R1 , R7 );
52 CHECKREG r0, 0xA789AB2D;
53 CHECKREG r1, 0xA789AB2D;
54 CHECKREG r2, 0xB4445525;
55 CHECKREG r3, 0xC6667727;
56 CHECKREG r4, 0xD8889929;
57 CHECKREG r5, 0xEAAABB2B;
58 CHECKREG r6, 0xFCCCDD2D;
59 CHECKREG r7, 0x0EEEFFFF;
60
61 imm32 r0, 0x416789ab;
62 imm32 r1, 0x6289abcd;
63 imm32 r2, 0x43445555;
64 imm32 r3, 0x64667777;
65 imm32 r4, 0x456789ab;
66 imm32 r5, 0x6689abcd;
67 imm32 r6, 0x47445555;
68 imm32 r7, 0x68667777;
69 R0 = MAX ( R2 , R0 );
70 R1 = MAX ( R2 , R1 );
71 R2 = MAX ( R2 , R2 );
72 R3 = MAX ( R2 , R3 );
73 R4 = MAX ( R2 , R4 );
74 R5 = MAX ( R2 , R5 );
75 R6 = MAX ( R2 , R6 );
76 R7 = MAX ( R2 , R7 );
77 CHECKREG r0, 0x43445555;
78 CHECKREG r1, 0x6289ABCD;
79 CHECKREG r2, 0x43445555;
80 CHECKREG r3, 0x64667777;
81 CHECKREG r4, 0x456789AB;
82 CHECKREG r5, 0x6689ABCD;
83 CHECKREG r6, 0x47445555;
84 CHECKREG r7, 0x68667777;
85
86 imm32 r0, 0x9567892b;
87 imm32 r1, 0xa789ab2d;
88 imm32 r2, 0xb4445525;
89 imm32 r3, 0xc6667727;
90 imm32 r0, 0x9567892b;
91 imm32 r1, 0xa789ab2d;
92 imm32 r2, 0xb4445525;
93 imm32 r3, 0xc6667727;
94 R0 = MAX ( R3 , R0 );
95 R1 = MAX ( R3 , R1 );
96 R2 = MAX ( R3 , R2 );
97 R3 = MAX ( R3 , R3 );
98 R4 = MAX ( R3 , R4 );
99 R5 = MAX ( R3 , R5 );
100 R6 = MAX ( R3 , R6 );
101 R7 = MAX ( R3 , R7 );
102 CHECKREG r0, 0xC6667727;
103 CHECKREG r1, 0xC6667727;
104 CHECKREG r2, 0xC6667727;
105 CHECKREG r3, 0xC6667727;
106 CHECKREG r4, 0x456789AB;
107 CHECKREG r5, 0x6689ABCD;
108 CHECKREG r6, 0x47445555;
109 CHECKREG r7, 0x68667777;
110
111 imm32 r0, 0x5537891b;
112 imm32 r1, 0x6759ab2d;
113 imm32 r2, 0x74555535;
114 imm32 r3, 0x86665747;
115 imm32 r4, 0x88789565;
116 imm32 r5, 0xaa8abb5b;
117 imm32 r6, 0xcc9cdd85;
118 imm32 r7, 0xeeaeff9f;
119 R0 = MAX ( R4 , R0 );
120 R1 = MAX ( R4 , R1 );
121 R2 = MAX ( R4 , R2 );
122 R3 = MAX ( R4 , R3 );
123 R4 = MAX ( R4 , R4 );
124 R5 = MAX ( R4 , R5 );
125 R6 = MAX ( R4 , R6 );
126 R7 = MAX ( R4 , R7 );
127 CHECKREG r0, 0x5537891B;
128 CHECKREG r1, 0x6759AB2D;
129 CHECKREG r2, 0x74555535;
130 CHECKREG r3, 0x88789565;
131 CHECKREG r4, 0x88789565;
132 CHECKREG r5, 0xAA8ABB5B;
133 CHECKREG r6, 0xCC9CDD85;
134 CHECKREG r7, 0xEEAEFF9F;
135
136 imm32 r0, 0x556b89ab;
137 imm32 r1, 0x69764bcd;
138 imm32 r2, 0x79736564;
139 imm32 r3, 0x81278394;
140 imm32 r4, 0x98876439;
141 imm32 r5, 0xaaaa0bbb;
142 imm32 r6, 0xcccc1ddd;
143 imm32 r7, 0x12346fff;
144 R0 = MAX ( R5 , R0 );
145 R1 = MAX ( R5 , R1 );
146 R2 = MAX ( R5 , R2 );
147 R3 = MAX ( R5 , R3 );
148 R4 = MAX ( R5 , R4 );
149 R5 = MAX ( R5 , R5 );
150 R6 = MAX ( R5 , R6 );
151 R7 = MAX ( R5 , R7 );
152 CHECKREG r0, 0x556B89AB;
153 CHECKREG r1, 0x69764BCD;
154 CHECKREG r2, 0x79736564;
155 CHECKREG r3, 0xAAAA0BBB;
156 CHECKREG r4, 0xAAAA0BBB;
157 CHECKREG r5, 0xAAAA0BBB;
158 CHECKREG r6, 0xCCCC1DDD;
159 CHECKREG r7, 0x12346FFF;
160
161 imm32 r0, 0xe56739ab;
162 imm32 r1, 0xf7694bcd;
163 imm32 r2, 0xa3456755;
164 imm32 r3, 0x66666777;
165 imm32 r4, 0x42345699;
166 imm32 r5, 0x45678b6b;
167 imm32 r6, 0x043290d6;
168 imm32 r7, 0x1234567f;
169 R0 = MAX ( R6 , R0 );
170 R1 = MAX ( R6 , R1 );
171 R2 = MAX ( R6 , R2 );
172 R3 = MAX ( R6 , R3 );
173 R4 = MAX ( R6 , R4 );
174 R5 = MAX ( R6 , R5 );
175 R6 = MAX ( R6 , R6 );
176 R7 = MAX ( R6 , R7 );
177 CHECKREG r0, 0x043290D6;
178 CHECKREG r1, 0x043290D6;
179 CHECKREG r2, 0x043290D6;
180 CHECKREG r3, 0x66666777;
181 CHECKREG r4, 0x42345699;
182 CHECKREG r5, 0x45678B6B;
183 CHECKREG r6, 0x043290D6;
184 CHECKREG r7, 0x1234567F;
185
186 imm32 r0, 0x576789ab;
187 imm32 r1, 0xd779abcd;
188 imm32 r2, 0x23456755;
189 imm32 r3, 0x56789007;
190 imm32 r4, 0x789ab799;
191 imm32 r5, 0xaaaa0bbb;
192 imm32 r6, 0xf9ab1d7d;
193 imm32 r7, 0xabcd2ff7;
194 R0 = MAX ( R7 , R0 );
195 R1 = MAX ( R7 , R1 );
196 R2 = MAX ( R7 , R2 );
197 R3 = MAX ( R7 , R3 );
198 R4 = MAX ( R7 , R4 );
199 R5 = MAX ( R7 , R5 );
200 R6 = MAX ( R7 , R6 );
201 R7 = MAX ( R7 , R7 );
202 CHECKREG r0, 0x576789AB;
203 CHECKREG r1, 0xD779ABCD;
204 CHECKREG r2, 0x23456755;
205 CHECKREG r3, 0x56789007;
206 CHECKREG r4, 0x789AB799;
207 CHECKREG r5, 0xABCD2FF7;
208 CHECKREG r6, 0xF9AB1D7D;
209 CHECKREG r7, 0xABCD2FF7;
210 imm32 r0, 0xe56739ab;
211 imm32 r1, 0x67694bcd;
212 imm32 r2, 0xd3456755;
213 imm32 r3, 0x66666777;
214 imm32 r4, 0x12345699;
215 imm32 r5, 0x45678b6b;
216 imm32 r6, 0x043290d6;
217 imm32 r7, 0x1234567f;
218 R4 = MAX ( R4 , R7 );
219 R5 = MAX ( R5 , R5 );
220 R2 = MAX ( R6 , R3 );
221 R6 = MAX ( R0 , R4 );
222 R0 = MAX ( R1 , R6 );
223 R2 = MAX ( R2 , R1 );
224 R1 = MAX ( R3 , R0 );
225 R7 = MAX ( R7 , R4 );
226 CHECKREG r0, 0x67694BCD;
227 CHECKREG r1, 0x67694BCD;
228 CHECKREG r2, 0x67694BCD;
229 CHECKREG r3, 0x66666777;
230 CHECKREG r4, 0x12345699;
231 CHECKREG r5, 0x45678B6B;
232 CHECKREG r6, 0x12345699;
233 CHECKREG r7, 0x12345699;
234
235 imm32 r0, 0xd76789ab;
236 imm32 r1, 0x6779abcd;
237 imm32 r2, 0xe3456755;
238 imm32 r3, 0x56789007;
239 imm32 r4, 0x789ab799;
240 imm32 r5, 0xaaaa0bbb;
241 imm32 r6, 0x89ab1d7d;
242 imm32 r7, 0xabcd2ff7;
243 R3 = MAX ( R4 , R0 );
244 R5 = MAX ( R5 , R1 );
245 R2 = MAX ( R2 , R2 );
246 R7 = MAX ( R7 , R3 );
247 R4 = MAX ( R3 , R4 );
248 R0 = MAX ( R1 , R5 );
249 R1 = MAX ( R0 , R6 );
250 R6 = MAX ( R6 , R7 );
251 CHECKREG r0, 0x6779ABCD;
252 CHECKREG r1, 0x6779ABCD;
253 CHECKREG r2, 0xE3456755;
254 CHECKREG r3, 0x789AB799;
255 CHECKREG r4, 0x789AB799;
256 CHECKREG r5, 0x6779ABCD;
257 CHECKREG r6, 0x789AB799;
258 CHECKREG r7, 0x789AB799;
259
260
261 pass
This page took 0.034368 seconds and 4 git commands to generate.