1 //Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp
2 // Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int)
5 .include "testutils.inc"
13 // The result accumulated in A1 , and stored to a reg half
22 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2);
24 R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2);
26 R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2);
28 R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2);
30 CHECKREG r0, 0x80005ABD;
31 CHECKREG r1, 0xFF910EEB;
32 CHECKREG r2, 0x80008679;
33 CHECKREG r3, 0xE8CA9815;
34 CHECKREG r4, 0x80004569;
35 CHECKREG r5, 0xE3B4A529;
36 CHECKREG r6, 0x8000800D;
37 CHECKREG r7, 0xE4C27FD1;
39 // The result accumulated in A1, and stored to a reg half (MNOP)
48 R0.H = ( A1 = R1.L * R0.L ) (ISS2);
50 R2.H = ( A1 += R2.L * R3.H ) (ISS2);
52 R4.H = ( A1 -= R4.H * R5.L ) (ISS2);
54 R6.H = ( A1 -= R6.H * R7.H ) (ISS2);
56 CHECKREG r0, 0x7FFF8ABD;
57 CHECKREG r1, 0x008F5EEB;
58 CHECKREG r2, 0x80005679;
59 CHECKREG r3, 0xECCF6C33;
60 CHECKREG r4, 0x80004569;
61 CHECKREG r5, 0xE0C07F1F;
62 CHECKREG r6, 0x8000A00D;
63 CHECKREG r7, 0xEDAD6477;
65 // The result accumulated in A1 , and stored to a reg half (MNOP)
74 R0.H = A1 , A0 -= R1.L * R0.L (ISS2);
76 R2.H = A1 , A0 += R2.H * R3.L (ISS2);
78 R4.H = A1 , A0 -= R4.H * R5.H (ISS2);
80 R6.H = A1 , A0 = R6.L * R7.H (ISS2);
82 CHECKREG r0, 0x8000BABD;
83 CHECKREG r1, 0xEDAD6477;
84 CHECKREG r2, 0x8000E679;
85 CHECKREG r3, 0xEDAD6477;
86 CHECKREG r4, 0x80004569;
87 CHECKREG r5, 0xEDAD6477;
88 CHECKREG r6, 0x8000300D;
89 CHECKREG r7, 0xEDAD6477;
91 // The result accumulated in A1 , and stored to a reg half
100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2);
102 R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2);
104 R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2);
106 R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2);
108 CHECKREG r0, 0x80005ABD;
109 CHECKREG r1, 0xFF910EEB;
110 CHECKREG r2, 0x7FFF5679;
111 CHECKREG r3, 0x303725C1;
112 CHECKREG r4, 0x7FFF4569;
113 CHECKREG r5, 0x5D60D8AD;
114 CHECKREG r6, 0x7FFFA00D;
115 CHECKREG r7, 0x43823355;
117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
118 imm32 r0, 0x92005ABD;
119 imm32 r1, 0x09300000;
120 imm32 r2, 0x56749679;
121 imm32 r3, 0x30A95000;
122 imm32 r4, 0xa0009669;
123 imm32 r5, 0x01000970;
124 imm32 r6, 0xdf45609D;
125 imm32 r7, 0x12345679;
126 R0.H = ( A1 += R1.L * R0.L ) (M,ISS2);
128 R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2);
130 R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2);
132 R6.H = ( A1 = R6.H * R7.H ) (M,ISS2);
134 CHECKREG r0, 0x7FFF5ABD;
135 CHECKREG r1, 0x43823355;
136 CHECKREG r2, 0x7FFF9679;
137 CHECKREG r3, 0x57912D74;
138 CHECKREG r4, 0x7FFF9669;
139 CHECKREG r5, 0x5B1B2D74;
140 CHECKREG r6, 0x8000609D;
141 CHECKREG r7, 0xFDAC3404;