sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp
   2 // Spec Reference: dsp32mac dr_a1 iu (unsigned integer)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A1 , and stored to a reg half
  14 imm32 r0, 0x93545abd;
  15 imm32 r1, 0x7890afc7;
  16 imm32 r2, 0x52248679;
  17 imm32 r3, 0xd5069007;
  18 imm32 r4, 0xef5c4569;
  19 imm32 r5, 0xcd35500b;
  20 imm32 r6, 0xe00c500d;
  21 imm32 r7, 0xf78e950f;
  22 R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU);
  23 R1 = A1.w;
  24 R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU);
  25 R3 = A1.w;
  26 R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU);
  27 R5 = A1.w;
  28 R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU);
  29 R7 = A1.w;
  30 CHECKREG r0, 0xFFFF5ABD;
  31 CHECKREG r1, 0x3E4DBBEB;
  32 CHECKREG r2, 0xFFFF8679;
  33 CHECKREG r3, 0xAE338FC1;
  34 CHECKREG r4, 0xFFFF4569;
  35 CHECKREG r5, 0xF90A98B5;
  36 CHECKREG r6, 0xFFFF500D;
  37 CHECKREG r7, 0x2062BE0D;
  38
  39 // The result accumulated in A1, and stored to a reg half (MNOP)
  40 imm32 r0, 0xd3548abd;
  41 imm32 r1, 0x9dbcfec7;
  42 imm32 r2, 0xa9d45679;
  43 imm32 r3, 0xb09d9007;
  44 imm32 r4, 0xcfb9d569;
  45 imm32 r5, 0xd2359d0b;
  46 imm32 r6, 0xe00ca90d;
  47 imm32 r7, 0x678e709f;
  48 R0.H = ( A1 += R1.L * R0.L ) (IU);
  49 R1 = A1.w;
  50 R2.H = ( A1 -= R2.L * R3.H ) (IU);
  51 R3 = A1.w;
  52 R4.H = ( A1 = R4.H * R5.L ) (IU);
  53 R5 = A1.w;
  54 R6.H = ( A1 -= R6.H * R7.H ) (IU);
  55 R7 = A1.w;
  56 CHECKREG r0, 0xFFFF8ABD;
  57 CHECKREG r1, 0xAA761CF8;
  58 CHECKREG r2, 0xFFFF5679;
  59 CHECKREG r3, 0x6ECDE4C3;
  60 CHECKREG r4, 0xFFFFD569;
  61 CHECKREG r5, 0x7F6D61F3;
  62 CHECKREG r6, 0xFFFFA90D;
  63 CHECKREG r7, 0x24CC474B;
  64
  65 // The result accumulated in A1 , and stored to a reg half (MNOP)
  66 imm32 r0, 0xa354babd;
  67 imm32 r1, 0x9abcdec7;
  68 imm32 r2, 0x77a4e679;
  69 imm32 r3, 0x805a7007;
  70 imm32 r4, 0x9fb3a569;
  71 imm32 r5, 0xa2352a0b;
  72 imm32 r6, 0xb00c10ad;
  73 imm32 r7, 0x9876a10a;
  74  R0.H = A1 , A0 -= R1.L * R0.L (IU);
  75 R1 = A1.w;
  76  R2.H = A1 , A0 += R2.H * R3.L (IU);
  77 R3 = A1.w;
  78  R4.H = A1 , A0 = R4.H * R5.H (IU);
  79 R5 = A1.w;
  80  R6.H = A1 , A0 -= R6.L * R7.H (IU);
  81 R7 = A1.w;
  82 CHECKREG r0, 0xFFFFBABD;
  83 CHECKREG r1, 0x24CC474B;
  84 CHECKREG r2, 0xFFFFE679;
  85 CHECKREG r3, 0x24CC474B;
  86 CHECKREG r4, 0xFFFFA569;
  87 CHECKREG r5, 0x24CC474B;
  88 CHECKREG r6, 0xFFFF10AD;
  89 CHECKREG r7, 0x24CC474B;
  90
  91 // The result accumulated in A1 , and stored to a reg half
  92 imm32 r0, 0x33545abd;
  93 imm32 r1, 0x9dbcfec7;
  94 imm32 r2, 0x81245679;
  95 imm32 r3, 0x97060007;
  96 imm32 r4, 0xaf6c4569;
  97 imm32 r5, 0xd235900b;
  98 imm32 r6, 0xc00c400d;
  99 imm32 r7, 0x678ed30f;
 100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU);
 101 R1 = A1.w;
 102 R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU);
 103 R3 = A1.w;
 104 R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU);
 105 R5 = A1.w;
 106 R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU);
 107 R7 = A1.w;
 108 CHECKREG r0, 0x80005ABD;
 109 CHECKREG r1, 0xFF910EEB;
 110 CHECKREG r2, 0x80005679;
 111 CHECKREG r3, 0xCC8DA915;
 112 CHECKREG r4, 0x80004569;
 113 CHECKREG r5, 0xD2A949A4;
 114 CHECKREG r6, 0x8000400D;
 115 CHECKREG r7, 0xB8CAA44C;
 116
 117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 118 imm32 r0, 0xe2005ABD;
 119 imm32 r1, 0x0e300000;
 120 imm32 r2, 0x56e49679;
 121 imm32 r3, 0x30Ae5000;
 122 imm32 r4, 0xa000e669;
 123 imm32 r5, 0x01000e70;
 124 imm32 r6, 0xdf4560eD;
 125 imm32 r7, 0x1234567e;
 126 R0.H = ( A1 -= R1.L * R0.L ) (M,IU);
 127 R1 = A1.w;
 128 R2.H = ( A1 += R2.L * R3.H ) (M,IU);
 129 R3 = A1.w;
 130 R4.H = ( A1 -= R4.H * R5.L ) (M,IU);
 131 R5 = A1.w;
 132 R6.H = ( A1 -= R6.H * R7.H ) (M,IU);
 133 R7 = A1.w;
 134 CHECKREG r0, 0x80005ABD;
 135 CHECKREG r1, 0xB8CAA44C;
 136 CHECKREG r2, 0x80009679;
 137 CHECKREG r3, 0xA4B99A8A;
 138 CHECKREG r4, 0x8000E669;
 139 CHECKREG r5, 0xAA239A8A;
 140 CHECKREG r6, 0x800060ED;
 141 CHECKREG r7, 0xAC776686;
 142
 143
 144
 145 pass