sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
   2 // Spec Reference: dsp32mac dr a1 t (truncation)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A , and stored to a reg half
  14 imm32 r0, 0xa3545abd;
  15 imm32 r1, 0xbdbcfec7;
  16 imm32 r2, 0xc1248679;
  17 imm32 r3, 0xd0069007;
  18 imm32 r4, 0xefbc4569;
  19 imm32 r5, 0xcd35500b;
  20 imm32 r6, 0xe00c800d;
  21 imm32 r7, 0xf78e900f;
  22 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T);
  23 R1 = A1.w;
  24 R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T);
  25 R3 = A1.w;
  26 R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T);
  27 R5 = A1.w;
  28 R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T);
  29 R7 = A1.w;
  30 CHECKREG r0, 0xFF225ABD;
  31 CHECKREG r1, 0xFF221DD6;
  32 CHECKREG r2, 0x2D8C8679;
  33 CHECKREG r3, 0x2D8CEDAC;
  34 CHECKREG r4, 0xF5D44569;
  35 CHECKREG r5, 0xF5D41A28;
  36 CHECKREG r6, 0x021B800D;
  37 CHECKREG r7, 0x021BB550;
  38
  39 // The result accumulated in A , and stored to a reg half (MNOP)
  40 imm32 r0, 0x63548abd;
  41 imm32 r1, 0x7dbcfec7;
  42 imm32 r2, 0xa1245679;
  43 imm32 r3, 0xb0069007;
  44 imm32 r4, 0xcfbc4569;
  45 imm32 r5, 0xd235c00b;
  46 imm32 r6, 0xe00ca00d;
  47 imm32 r7, 0x678e700f;
  48 R0.H = ( A1 = R1.L * R0.L ) (T);
  49 R1 = A1.w;
  50 R2.H = ( A1 += R2.L * R3.H ) (T);
  51 R3 = A1.w;
  52 R4.H = ( A1 = R4.H * R5.L ) (T);
  53 R5 = A1.w;
  54 R6.H = ( A1 = R6.H * R7.H ) (T);
  55 R7 = A1.w;
  56 CHECKREG r0, 0x011E8ABD;
  57 CHECKREG r1, 0x011EBDD6;
  58 CHECKREG r2, 0xCB175679;
  59 CHECKREG r3, 0xCB172B82;
  60 CHECKREG r4, 0x181D4569;
  61 CHECKREG r5, 0x181DDA28;
  62 CHECKREG r6, 0xE626A00D;
  63 CHECKREG r7, 0xE6263550;
  64
  65 // The result accumulated in A , and stored to a reg half (MNOP)
  66 imm32 r0, 0x5354babd;
  67 imm32 r1, 0x6dbcdec7;
  68 imm32 r2, 0x7124e679;
  69 imm32 r3, 0x80067007;
  70 imm32 r4, 0x9fbc4569;
  71 imm32 r5, 0xa235900b;
  72 imm32 r6, 0xb00c300d;
  73 imm32 r7, 0xc78ea00f;
  74  R0.H = A1 , A0 = R1.L * R0.L (T);
  75 R1 = A1.w;
  76  R2.H = A1 , A0 = R2.H * R3.L (T);
  77 R3 = A1.w;
  78  R4.H = A1 , A0 = R4.H * R5.H (T);
  79 R5 = A1.w;
  80  R6.H = A1 , A0 += R6.L * R7.H (T);
  81 R7 = A1.w;
  82 CHECKREG r0, 0xE626BABD;
  83 CHECKREG r1, 0xE6263550;
  84 CHECKREG r2, 0xE626E679;
  85 CHECKREG r3, 0xE6263550;
  86 CHECKREG r4, 0xE6264569;
  87 CHECKREG r5, 0xE6263550;
  88 CHECKREG r6, 0xE626300D;
  89 CHECKREG r7, 0xE6263550;
  90
  91 // The result accumulated in A , and stored to a reg half
  92 imm32 r0, 0x33545abd;
  93 imm32 r1, 0x5dbcfec7;
  94 imm32 r2, 0x71245679;
  95 imm32 r3, 0x90060007;
  96 imm32 r4, 0xafbc4569;
  97 imm32 r5, 0xd235900b;
  98 imm32 r6, 0xc00ca00d;
  99 imm32 r7, 0x678ed00f;
 100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
 101 R1 = A1.w;
 102 R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T);
 103 R3 = A0.w;
 104 R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T);
 105 R5 = A1.w;
 106 R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T);
 107 R7 = A0.w;
 108 CHECKREG r0, 0xFF915ABD;
 109 CHECKREG r1, 0xFF910EEB;
 110 CHECKREG r2, 0x30375679;
 111 CHECKREG r3, 0x00062FF8;
 112 CHECKREG r4, 0x030D4569;
 113 CHECKREG r5, 0x030D72D5;
 114 CHECKREG r6, 0xE621A00D;
 115 CHECKREG r7, 0xCF173844;
 116
 117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 118 imm32 r0, 0x83545abd;
 119 imm32 r1, 0xa8bcfec7;
 120 imm32 r2, 0xc1845679;
 121 imm32 r3, 0x1c080007;
 122 imm32 r4, 0xe1cc8569;
 123 imm32 r5, 0x921c080b;
 124 imm32 r6, 0x7901908d;
 125 imm32 r7, 0x679e9008;
 126 R0.H = ( A1 += R1.L * R0.L ) (M,T);
 127 R1 = A1.w;
 128 R2.H = ( A1 = R2.L * R3.H ) (M,T);
 129 R3 = A1.w;
 130 R4.H = ( A1 += R4.H * R5.L ) (M,T);
 131 R5 = A1.w;
 132 R6.H = ( A1 = R6.H * R7.H ) (M,T);
 133 R7 = A1.w;
 134 CHECKREG r0, 0xE5B25ABD;
 135 CHECKREG r1, 0xE5B26993;
 136 CHECKREG r2, 0x09775679;
 137 CHECKREG r3, 0x0977EFC8;
 138 CHECKREG r4, 0x08858569;
 139 CHECKREG r5, 0x0885038C;
 140 CHECKREG r6, 0x30FA908D;
 141 CHECKREG r7, 0x30FA159E;
 142
 143 imm32 r0, 0x03545abd;
 144 imm32 r1, 0xb0bcfec7;
 145 imm32 r2, 0xc1048679;
 146 imm32 r3, 0xd0009007;
 147 imm32 r4, 0xefbc0569;
 148 imm32 r5, 0xcd35510b;
 149 imm32 r6, 0xe00c802d;
 150 imm32 r7, 0xf78e9003;
 151 R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T);
 152 R1 = A1.w;
 153 R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T);
 154 R3 = A1.w;
 155 R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T);
 156 R5 = A1.w;
 157 R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T);
 158 R7 = A1.w;
 159 CHECKREG r0, 0x31D75ABD;
 160 CHECKREG r1, 0x31D7F7C8;
 161 CHECKREG r2, 0x2D928679;
 162 CHECKREG r3, 0x2D92A000;
 163 CHECKREG r4, 0x37DF0569;
 164 CHECKREG r5, 0x37DF0DD8;
 165 CHECKREG r6, 0x39FA802D;
 166 CHECKREG r7, 0x39FAC328;
 167
 168 // The result accumulated in A , and stored to a reg half (MNOP)
 169 imm32 r0, 0x63548abd;
 170 imm32 r1, 0x7dbcfec7;
 171 imm32 r2, 0xa1245679;
 172 imm32 r3, 0xb0069007;
 173 imm32 r4, 0xcfbc4569;
 174 imm32 r5, 0xd235c00b;
 175 imm32 r6, 0xe00ca00d;
 176 imm32 r7, 0x678e700f;
 177 R0.H = ( A1 -= R1.L * R0.L ) (T);
 178 R1 = A1.w;
 179 R2.H = ( A1 -= R2.L * R3.H ) (T);
 180 R3 = A1.w;
 181 R4.H = ( A1 -= R4.H * R5.L ) (T);
 182 R5 = A1.w;
 183 R6.H = ( A1 -= R6.H * R7.H ) (T);
 184 R7 = A1.w;
 185 CHECKREG r0, 0x38DC8ABD;
 186 CHECKREG r1, 0x38DC0552;
 187 CHECKREG r2, 0x6EE35679;
 188 CHECKREG r3, 0x6EE397A6;
 189 CHECKREG r4, 0x56C54569;
 190 CHECKREG r5, 0x56C5BD7E;
 191 CHECKREG r6, 0x709FA00D;
 192 CHECKREG r7, 0x709F882E;
 193
 194 // The result accumulated in A , and stored to a reg half (MNOP)
 195 imm32 r0, 0x5354babd;
 196 imm32 r1, 0x6dbcdec7;
 197 imm32 r2, 0x7124e679;
 198 imm32 r3, 0x80067007;
 199 imm32 r4, 0x9fbc4569;
 200 imm32 r5, 0xa235900b;
 201 imm32 r6, 0xb00c300d;
 202 imm32 r7, 0xc78ea00f;
 203  R0.H = A1 , A0 -= R1.L * R0.L (T);
 204 R1 = A1.w;
 205  R2.H = A1 , A0 -= R2.H * R3.L (T);
 206 R3 = A1.w;
 207  R4.H = A1 , A0 -= R4.H * R5.H (T);
 208 R5 = A1.w;
 209  R6.H = A1 , A0 -= R6.L * R7.H (T);
 210 R7 = A1.w;
 211 CHECKREG r0, 0x709FBABD;
 212 CHECKREG r1, 0x709F882E;
 213 CHECKREG r2, 0x709FE679;
 214 CHECKREG r3, 0x709F882E;
 215 CHECKREG r4, 0x709F4569;
 216 CHECKREG r5, 0x709F882E;
 217 CHECKREG r6, 0x709F300D;
 218 CHECKREG r7, 0x709F882E;
 219
 220 // The result accumulated in A , and stored to a reg half
 221 imm32 r0, 0x33545abd;
 222 imm32 r1, 0x5dbcfec7;
 223 imm32 r2, 0x71245679;
 224 imm32 r3, 0x90060007;
 225 imm32 r4, 0xafbc4569;
 226 imm32 r5, 0xd235900b;
 227 imm32 r6, 0xc00ca00d;
 228 imm32 r7, 0x678ed00f;
 229 R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
 230 R1 = A1.w;
 231 R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T);
 232 R3 = A0.w;
 233 R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T);
 234 R5 = A1.w;
 235 R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T);
 236 R7 = A0.w;
 237 CHECKREG r0, 0x710E5ABD;
 238 CHECKREG r1, 0x710E7943;
 239 CHECKREG r2, 0x40685679;
 240 CHECKREG r3, 0x1ED0EB56;
 241 CHECKREG r4, 0x133E4569;
 242 CHECKREG r5, 0x133EAF81;
 243 CHECKREG r6, 0xF960A00D;
 244 CHECKREG r7, 0x4FB9B312;
 245
 246 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 247 imm32 r0, 0x83545abd;
 248 imm32 r1, 0xa8bcfec7;
 249 imm32 r2, 0xc1845679;
 250 imm32 r3, 0x1c080007;
 251 imm32 r4, 0xe1cc8569;
 252 imm32 r5, 0x921c080b;
 253 imm32 r6, 0x7901908d;
 254 imm32 r7, 0x679e9008;
 255 R0.H = ( A1 -= R1.L * R0.L ) (M,T);
 256 R1 = A1.w;
 257 R2.H = ( A1 -= R2.L * R3.H ) (M,T);
 258 R3 = A1.w;
 259 R4.H = ( A1 -= R4.H * R5.L ) (M,T);
 260 R5 = A1.w;
 261 R6.H = ( A1 -= R6.H * R7.H ) (M,T);
 262 R7 = A1.w;
 263 CHECKREG r0, 0xF9CE5ABD;
 264 CHECKREG r1, 0xF9CEFB3E;
 265 CHECKREG r2, 0xF0575679;
 266 CHECKREG r3, 0xF0570B76;
 267 CHECKREG r4, 0xF1498569;
 268 CHECKREG r5, 0xF149F7B2;
 269 CHECKREG r6, 0xC04F908D;
 270 CHECKREG r7, 0xC04FE214;
 271
 272
 273
 274 pass