sim/testsuite/sim/bfin/c_dsp32shift_bxor.s

   1 //Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp
   2 // Spec Reference: dsp32shift bxor
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 R0 = 0;
   9 R1 = 58;
  10 A0 = R1;
  11 ASTAT = R0;
  12
  13
  14 imm32 r0, 0x12345678;
  15 imm32 r1, 0x22334455;
  16 imm32 r2, 0x66778890;
  17 imm32 r3, 0xaabbccdd;
  18 imm32 r4, 0x34567890;
  19 imm32 r5, 0xa2d3d5f6;
  20 imm32 r6, 0x456bda06;
  21 imm32 r7, 0x56789abc;
  22 R0.L = CC = BXORSHIFT( A0 , R0 );
  23 R1.L = CC = BXORSHIFT( A0 , R1 );
  24 R2.L = CC = BXORSHIFT( A0 , R2 );
  25 R3.L = CC = BXORSHIFT( A0 , R3 );
  26 R4.L = CC = BXORSHIFT( A0 , R4 );
  27 R5.L = CC = BXORSHIFT( A0 , R5 );
  28 R6.L = CC = BXORSHIFT( A0 , R6 );
  29 R7.L = CC = BXORSHIFT( A0 , R7 );
  30 CHECKREG r0, 0x12340001;
  31 CHECKREG r1, 0x22330001;
  32 CHECKREG r2, 0x66770000;
  33 CHECKREG r3, 0xAABB0001;
  34 CHECKREG r4, 0x34560000;
  35 CHECKREG r5, 0xA2D30000;
  36 CHECKREG r6, 0x456B0000;
  37 CHECKREG r7, 0x56780001;
  38
  39 imm32 r0, 0xa1001001;
  40 imm32 r1, 0x1b001001;
  41 imm32 r2, 0x11c01002;
  42 imm32 r3, 0x110d1003;
  43 imm32 r4, 0x1100e004;
  44 imm32 r5, 0x11001f05;
  45 imm32 r6, 0x11001006;
  46 imm32 r7, 0x11001001;
  47 R5.L = CC = BXORSHIFT( A0 , R0 );
  48 R4.L = CC = BXORSHIFT( A0 , R1 );
  49 R2.L = CC = BXORSHIFT( A0 , R2 );
  50 R7.L = CC = BXORSHIFT( A0 , R3 );
  51 R0.L = CC = BXORSHIFT( A0 , R4 );
  52 R1.L = CC = BXORSHIFT( A0 , R5 );
  53 R3.L = CC = BXORSHIFT( A0 , R6 );
  54 R6.L = CC = BXORSHIFT( A0 , R7 );
  55 CHECKREG r0, 0xA1000000;
  56 CHECKREG r1, 0x1B000000;
  57 CHECKREG r2, 0x11C00001;
  58 CHECKREG r3, 0x110D0000;
  59 CHECKREG r4, 0x11000000;
  60 CHECKREG r5, 0x11000001;
  61 CHECKREG r6, 0x11000000;
  62 CHECKREG r7, 0x11000001;
  63
  64 imm32 r0, 0xa2001001;
  65 imm32 r1, 0x1b341001;
  66 imm32 r2, 0x71c01002;
  67 imm32 r3, 0x810d1003;
  68 imm32 r4, 0x1600e004;
  69 imm32 r5, 0x41001405;
  70 imm32 r6, 0x31003006;
  71 imm32 r7, 0x21004671;
  72 R2.L = CC = BXOR( A0 , R0 );
  73 R3.L = CC = BXOR( A0 , R1 );
  74 R5.L = CC = BXOR( A0 , R2 );
  75 R6.L = CC = BXOR( A0 , R3 );
  76 R0.L = CC = BXOR( A0 , R4 );
  77 R1.L = CC = BXOR( A0 , R5 );
  78 R7.L = CC = BXOR( A0 , R6 );
  79 R4.L = CC = BXOR( A0 , R7 );
  80 CHECKREG r0, 0xA2000000;
  81 CHECKREG r1, 0x1B340000;
  82 CHECKREG r2, 0x71C00000;
  83 CHECKREG r3, 0x810D0000;
  84 CHECKREG r4, 0x16000000;
  85 CHECKREG r5, 0x41000000;
  86 CHECKREG r6, 0x31000001;
  87 CHECKREG r7, 0x21000000;
  88
  89 imm32 r0, 0x4a502001;
  90 imm32 r1, 0x6b343001;
  91 imm32 r2, 0x71c04002;
  92 imm32 r3, 0x810d5003;
  93 imm32 r4, 0x5600e004;
  94 imm32 r5, 0x47001405;
  95 imm32 r6, 0x91003006;
  96 imm32 r7, 0xa1004671;
  97 A1 = R3;
  98 R0.L = CC = BXOR( A0 , A1, CC );
  99 A0 = BXORSHIFT( A0 , A1, CC );
 100 R1.L = CC = BXOR( A0 , A1, CC );
 101 A0 = BXORSHIFT( A0 , A1, CC );
 102 R2.L = CC = BXOR( A0 , A1, CC );
 103 A0 = BXORSHIFT( A0 , A1, CC );
 104 R3.L = CC = BXOR( A0 , A1, CC );
 105 A0 = BXORSHIFT( A0 , A1, CC );
 106 R4.L = CC = BXOR( A0 , A1, CC );
 107 A0 = BXORSHIFT( A0 , A1, CC );
 108 R5.L = CC = BXOR( A0 , A1, CC );
 109 A0 = BXORSHIFT( A0 , A1, CC );
 110 R6.L = CC = BXOR( A0 , A1, CC );
 111 A0 = BXORSHIFT( A0 , A1, CC );
 112 R7.L = CC = BXOR( A0 , A1, CC );
 113 A0 = BXORSHIFT( A0 , A1, CC );
 114 CHECKREG r0, 0x4A500001;
 115 CHECKREG r1, 0x6B340000;
 116 CHECKREG r2, 0x71C00000;
 117 CHECKREG r3, 0x810D0000;
 118 CHECKREG r4, 0x56000001;
 119 CHECKREG r5, 0x47000000;
 120 CHECKREG r6, 0x91000001;
 121 CHECKREG r7, 0xA1000001;
 122
 123
 124
 125
 126 pass