sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s

   1 //Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp
   2 // Spec Reference: dsp32shift lshift
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 // lshift : positive data, count (+)=left (half reg)
  12 // d_lo = lshift (d_lo BY d_lo)
  13 // RLx by RLx
  14 imm32 r0, 0x00000000;
  15 R0.L = -1;
  16 imm32 r1, 0x00008001;
  17 imm32 r2, 0x00008002;
  18 imm32 r3, 0x00008003;
  19 imm32 r4, 0x00008004;
  20 imm32 r5, 0x00008005;
  21 imm32 r6, 0x00008006;
  22 imm32 r7, 0x00008007;
  23 //rl0 = lshift (rl0 by rl0);
  24 R1.L = LSHIFT R1.L BY R0.L;
  25 R2.L = LSHIFT R2.L BY R0.L;
  26 R3.L = LSHIFT R3.L BY R0.L;
  27 R4.L = LSHIFT R4.L BY R0.L;
  28 R5.L = LSHIFT R5.L BY R0.L;
  29 R6.L = LSHIFT R6.L BY R0.L;
  30 R7.L = LSHIFT R7.L BY R0.L;
  31 //CHECKREG r0, 0x00000000;
  32 CHECKREG r1, 0x00004000;
  33 CHECKREG r2, 0x00004001;
  34 CHECKREG r3, 0x00004001;
  35 CHECKREG r4, 0x00004002;
  36 CHECKREG r5, 0x00004002;
  37 CHECKREG r6, 0x00004003;
  38 CHECKREG r7, 0x00004003;
  39
  40 imm32 r0, 0x00008001;
  41 R1.L = -1;
  42 imm32 r2, 0x00008002;
  43 imm32 r3, 0x00008003;
  44 imm32 r4, 0x00008004;
  45 imm32 r5, 0x00008005;
  46 imm32 r6, 0x00008006;
  47 imm32 r7, 0x00008007;
  48 R0.L = LSHIFT R0.L BY R1.L;
  49 //rl1 = lshift (rl1 by rl1);
  50 R2.L = LSHIFT R2.L BY R1.L;
  51 R3.L = LSHIFT R3.L BY R1.L;
  52 R4.L = LSHIFT R4.L BY R1.L;
  53 R5.L = LSHIFT R5.L BY R1.L;
  54 R6.L = LSHIFT R6.L BY R1.L;
  55 R7.L = LSHIFT R7.L BY R1.L;
  56 CHECKREG r0, 0x00004000;
  57 //CHECKREG r1, 0x00000001;
  58 CHECKREG r2, 0x00004001;
  59 CHECKREG r3, 0x00004001;
  60 CHECKREG r4, 0x00004002;
  61 CHECKREG r5, 0x00004002;
  62 CHECKREG r6, 0x00004003;
  63 CHECKREG r7, 0x00004003;
  64
  65
  66 imm32 r0, 0x00008001;
  67 imm32 r1, 0x00008001;
  68 R2.L = -15;
  69 imm32 r3, 0x00008003;
  70 imm32 r4, 0x00008004;
  71 imm32 r5, 0x00008005;
  72 imm32 r6, 0x00008006;
  73 imm32 r7, 0x00008007;
  74 R0.L = LSHIFT R0.L BY R2.L;
  75 R1.L = LSHIFT R1.L BY R2.L;
  76 //rl2 = lshift (rl2 by rl2);
  77 R3.L = LSHIFT R3.L BY R2.L;
  78 R4.L = LSHIFT R4.L BY R2.L;
  79 R5.L = LSHIFT R5.L BY R2.L;
  80 R6.L = LSHIFT R6.L BY R2.L;
  81 R7.L = LSHIFT R7.L BY R2.L;
  82 CHECKREG r0, 0x00000001;
  83 CHECKREG r1, 0x00000001;
  84 //CHECKREG r2, 0x0000000f;
  85 CHECKREG r3, 0x00000001;
  86 CHECKREG r4, 0x00000001;
  87 CHECKREG r5, 0x00000001;
  88 CHECKREG r6, 0x00000001;
  89 CHECKREG r7, 0x00000001;
  90
  91 imm32 r0, 0x00008001;
  92 imm32 r1, 0x00008001;
  93 imm32 r2, 0x00008002;
  94 R3.L = -16;
  95 imm32 r4, 0x00008004;
  96 imm32 r5, 0x00008005;
  97 imm32 r6, 0x00008006;
  98 imm32 r7, 0x00008007;
  99 R0.L = LSHIFT R0.L BY R3.L;
 100 R1.L = LSHIFT R1.L BY R3.L;
 101 R2.L = LSHIFT R2.L BY R3.L;
 102 //rl3 = lshift (rl3 by rl3);
 103 R4.L = LSHIFT R4.L BY R3.L;
 104 R5.L = LSHIFT R5.L BY R3.L;
 105 R6.L = LSHIFT R6.L BY R3.L;
 106 R7.L = LSHIFT R7.L BY R3.L;
 107 CHECKREG r0, 0x00000000;
 108 CHECKREG r1, 0x00000000;
 109 CHECKREG r2, 0x00000000;
 110 //CHECKREG r3, 0x00000010;
 111 CHECKREG r4, 0x00000000;
 112 CHECKREG r5, 0x00000000;
 113 CHECKREG r6, 0x00000000;
 114 CHECKREG r7, 0x00000000;
 115
 116 // d_lo = ashft (d_hi BY d_lo)
 117 // RHx by RLx
 118 imm32 r0, 0x00000000;
 119 imm32 r1, 0x80010000;
 120 imm32 r2, 0x80020000;
 121 imm32 r3, 0x80030000;
 122 imm32 r4, 0x80040000;
 123 imm32 r5, 0x80050000;
 124 imm32 r6, 0x80060000;
 125 imm32 r7, 0x80070000;
 126 R0.L = LSHIFT R0.H BY R0.L;
 127 R1.L = LSHIFT R1.H BY R0.L;
 128 R2.L = LSHIFT R2.H BY R0.L;
 129 R3.L = LSHIFT R3.H BY R0.L;
 130 R4.L = LSHIFT R4.H BY R0.L;
 131 R5.L = LSHIFT R5.H BY R0.L;
 132 R6.L = LSHIFT R6.H BY R0.L;
 133 R7.L = LSHIFT R7.H BY R0.L;
 134 CHECKREG r0, 0x00000000;
 135 CHECKREG r1, 0x80018001;
 136 CHECKREG r2, 0x80028002;
 137 CHECKREG r3, 0x80038003;
 138 CHECKREG r4, 0x80048004;
 139 CHECKREG r5, 0x80058005;
 140 CHECKREG r6, 0x80068006;
 141 CHECKREG r7, 0x80078007;
 142
 143 imm32 r0, 0x80010000;
 144 R1.L = -1;
 145 imm32 r2, 0x80020000;
 146 imm32 r3, 0x80030000;
 147 imm32 r4, 0x80040000;
 148 imm32 r5, 0x80050000;
 149 imm32 r6, 0x80060000;
 150 imm32 r7, 0x80070000;
 151 R0.L = LSHIFT R0.H BY R1.L;
 152 //rl1 = lshift (rh1 by rl1);
 153 R2.L = LSHIFT R2.H BY R1.L;
 154 R3.L = LSHIFT R3.H BY R1.L;
 155 R4.L = LSHIFT R4.H BY R1.L;
 156 R5.L = LSHIFT R5.H BY R1.L;
 157 R6.L = LSHIFT R6.H BY R1.L;
 158 R7.L = LSHIFT R7.H BY R1.L;
 159 CHECKREG r0, 0x80014000;
 160 //CHECKREG r1, 0x00010001;
 161 CHECKREG r2, 0x80024001;
 162 CHECKREG r3, 0x80034001;
 163 CHECKREG r4, 0x80044002;
 164 CHECKREG r5, 0x80054002;
 165 CHECKREG r6, 0x80064003;
 166 CHECKREG r7, 0x80074003;
 167
 168
 169 imm32 r0, 0xa0010000;
 170 imm32 r1, 0xa0010000;
 171 R2.L = -15;
 172 imm32 r3, 0xa0030000;
 173 imm32 r4, 0xa0040000;
 174 imm32 r5, 0xa0050000;
 175 imm32 r6, 0xa0060000;
 176 imm32 r7, 0xa0070000;
 177 R0.L = LSHIFT R0.H BY R2.L;
 178 R1.L = LSHIFT R1.H BY R2.L;
 179 //rl2 = lshift (rh2 by rl2);
 180 R3.L = LSHIFT R3.H BY R2.L;
 181 R4.L = LSHIFT R4.H BY R2.L;
 182 R5.L = LSHIFT R5.H BY R2.L;
 183 R6.L = LSHIFT R6.H BY R2.L;
 184 R7.L = LSHIFT R7.H BY R2.L;
 185 CHECKREG r0, 0xa0010001;
 186 CHECKREG r1, 0xa0010001;
 187 //CHECKREG r2, 0x2002000f;
 188 CHECKREG r3, 0xa0030001;
 189 CHECKREG r4, 0xa0040001;
 190 CHECKREG r5, 0xa0050001;
 191 CHECKREG r6, 0xa0060001;
 192 CHECKREG r7, 0xa0070001;
 193
 194 imm32 r0, 0xb0010001;
 195 imm32 r1, 0xb0010001;
 196 imm32 r2, 0xb0020002;
 197 R3.L = -16;
 198 imm32 r4, 0xb0040004;
 199 imm32 r5, 0xb0050005;
 200 imm32 r6, 0xb0060006;
 201 imm32 r7, 0xb0070007;
 202 R0.L = LSHIFT R0.H BY R3.L;
 203 R1.L = LSHIFT R1.H BY R3.L;
 204 R2.L = LSHIFT R2.H BY R3.L;
 205 //rl3 = lshift (rh3 by rl3);
 206 R4.L = LSHIFT R4.H BY R3.L;
 207 R5.L = LSHIFT R5.H BY R3.L;
 208 R6.L = LSHIFT R6.H BY R3.L;
 209 R7.L = LSHIFT R7.H BY R3.L;
 210 CHECKREG r0, 0xb0010000;
 211 CHECKREG r1, 0xb0010000;
 212 CHECKREG r2, 0xb0020000;
 213 //CHECKREG r3, 0x30030010;
 214 CHECKREG r4, 0xb0040000;
 215 CHECKREG r5, 0xb0050000;
 216 CHECKREG r6, 0xb0060000;
 217 CHECKREG r7, 0xb0070000;
 218
 219 // d_hi = ashft (d_lo BY d_lo)
 220 // RLx by RLx
 221 imm32 r0, 0x00000001;
 222 imm32 r1, 0x00000001;
 223 imm32 r2, 0x00000002;
 224 imm32 r3, 0x00000003;
 225 imm32 r4, 0x00000000;
 226 imm32 r5, 0x00000005;
 227 imm32 r6, 0x00000006;
 228 imm32 r7, 0x00000007;
 229 R0.H = LSHIFT R0.L BY R4.L;
 230 R1.H = LSHIFT R1.L BY R4.L;
 231 R2.H = LSHIFT R2.L BY R4.L;
 232 R3.H = LSHIFT R3.L BY R4.L;
 233 //rh4 = lshift (rl4 by rl4);
 234 R5.H = LSHIFT R5.L BY R4.L;
 235 R6.H = LSHIFT R6.L BY R4.L;
 236 R7.H = LSHIFT R7.L BY R4.L;
 237 CHECKREG r0, 0x00010001;
 238 CHECKREG r1, 0x00010001;
 239 CHECKREG r2, 0x00020002;
 240 CHECKREG r3, 0x00030003;
 241 //CHECKREG r4, 0x00040004;
 242 CHECKREG r5, 0x00050005;
 243 CHECKREG r6, 0x00060006;
 244 CHECKREG r7, 0x00070007;
 245
 246 imm32 r0, 0x00008001;
 247 imm32 r1, 0x00008001;
 248 imm32 r2, 0x00008002;
 249 imm32 r3, 0x00008003;
 250 imm32 r4, 0x00008004;
 251 R5.L = -1;
 252 imm32 r6, 0x00008006;
 253 imm32 r7, 0x00008007;
 254 R0.H = LSHIFT R0.L BY R5.L;
 255 R1.H = LSHIFT R1.L BY R5.L;
 256 R2.H = LSHIFT R2.L BY R5.L;
 257 R3.H = LSHIFT R3.L BY R5.L;
 258 R4.H = LSHIFT R4.L BY R5.L;
 259 //rh5 = lshift (rl5 by rl5);
 260 R6.H = LSHIFT R6.L BY R5.L;
 261 R7.H = LSHIFT R7.L BY R5.L;
 262 CHECKREG r0, 0x40008001;
 263 CHECKREG r1, 0x40008001;
 264 CHECKREG r2, 0x40018002;
 265 CHECKREG r3, 0x40018003;
 266 CHECKREG r4, 0x40028004;
 267 //CHECKREG r5, 0x00020005;
 268 CHECKREG r6, 0x40038006;
 269 CHECKREG r7, 0x40038007;
 270
 271
 272 imm32 r0, 0x00009001;
 273 imm32 r1, 0x00009001;
 274 imm32 r2, 0x00009002;
 275 imm32 r3, 0x00009003;
 276 imm32 r4, 0x00009004;
 277 imm32 r5, 0x00009005;
 278 R6.L = -15;
 279 imm32 r7, 0x00009007;
 280 R0.H = LSHIFT R0.L BY R6.L;
 281 R1.H = LSHIFT R1.L BY R6.L;
 282 R2.H = LSHIFT R2.L BY R6.L;
 283 R3.H = LSHIFT R3.L BY R6.L;
 284 R4.H = LSHIFT R4.L BY R6.L;
 285 R5.H = LSHIFT R5.L BY R6.L;
 286 //rh6 = lshift (rl6 by rl6);
 287 R7.H = LSHIFT R7.L BY R6.L;
 288 CHECKREG r0, 0x00019001;
 289 CHECKREG r1, 0x00019001;
 290 CHECKREG r2, 0x00019002;
 291 CHECKREG r3, 0x00019003;
 292 CHECKREG r4, 0x00019004;
 293 CHECKREG r5, 0x00019005;
 294 //CHECKREG r6, 0x00006006;
 295 CHECKREG r7, 0x00019007;
 296
 297 imm32 r0, 0x0000a001;
 298 imm32 r1, 0x0000a001;
 299 imm32 r2, 0x0000a002;
 300 imm32 r3, 0x0000a003;
 301 imm32 r4, 0x0000a004;
 302 imm32 r5, 0x0000a005;
 303 imm32 r6, 0x0000a006;
 304 R7.L = -16;
 305 R0.H = LSHIFT R0.L BY R7.L;
 306 R1.H = LSHIFT R1.L BY R7.L;
 307 R2.H = LSHIFT R2.L BY R7.L;
 308 R3.H = LSHIFT R3.L BY R7.L;
 309 R4.H = LSHIFT R4.L BY R7.L;
 310 R5.H = LSHIFT R5.L BY R7.L;
 311 R6.H = LSHIFT R6.L BY R7.L;
 312 R7.H = LSHIFT R7.L BY R7.L;
 313 CHECKREG r0, 0x0000a001;
 314 CHECKREG r1, 0x0000a001;
 315 CHECKREG r2, 0x0000a002;
 316 CHECKREG r3, 0x0000a003;
 317 CHECKREG r4, 0x0000a004;
 318 CHECKREG r5, 0x0000a005;
 319 CHECKREG r6, 0x0000a006;
 320 //CHECKREG r7, 0x00007007;
 321
 322 // d_lo = ashft (d_hi BY d_lo)
 323 // RHx by RLx
 324 imm32 r0, 0x80010000;
 325 imm32 r1, 0x80010000;
 326 imm32 r2, 0x80020000;
 327 imm32 r3, 0x80030000;
 328 R4.L = -1;
 329 imm32 r5, 0x80050000;
 330 imm32 r6, 0x80060000;
 331 imm32 r7, 0x80070000;
 332 R0.H = LSHIFT R0.H BY R4.L;
 333 R1.H = LSHIFT R1.H BY R4.L;
 334 R2.H = LSHIFT R2.H BY R4.L;
 335 R3.H = LSHIFT R3.H BY R4.L;
 336 //rh4 = lshift (rh4 by rl4);
 337 R5.H = LSHIFT R5.H BY R4.L;
 338 R6.H = LSHIFT R6.H BY R4.L;
 339 R7.H = LSHIFT R7.H BY R4.L;
 340 CHECKREG r0, 0x40000000;
 341 CHECKREG r1, 0x40000000;
 342 CHECKREG r2, 0x40010000;
 343 CHECKREG r3, 0x40010000;
 344 //CHECKREG r4, 0x00020000;
 345 CHECKREG r5, 0x40020000;
 346 CHECKREG r6, 0x40030000;
 347 CHECKREG r7, 0x40030000;
 348
 349 imm32 r0, 0x80010000;
 350 imm32 r1, 0x80010000;
 351 imm32 r2, 0x80020000;
 352 imm32 r3, 0x80030000;
 353 imm32 r4, 0x80040000;
 354 R5.L = -1;
 355 imm32 r6, 0x80060000;
 356 imm32 r7, 0x80070000;
 357 R0.H = LSHIFT R0.H BY R5.L;
 358 R1.H = LSHIFT R1.H BY R5.L;
 359 R2.H = LSHIFT R2.H BY R5.L;
 360 R3.H = LSHIFT R3.H BY R5.L;
 361 R4.H = LSHIFT R4.H BY R5.L;
 362 //rh5 = lshift (rh5 by rl5);
 363 R6.H = LSHIFT R6.H BY R5.L;
 364 R7.H = LSHIFT R7.H BY R5.L;
 365 CHECKREG r0, 0x40000000;
 366 CHECKREG r1, 0x40000000;
 367 CHECKREG r2, 0x40010000;
 368 CHECKREG r3, 0x40010000;
 369 CHECKREG r4, 0x40020000;
 370 //CHECKREG r5, 0x28020000;
 371 CHECKREG r6, 0x40030000;
 372 CHECKREG r7, 0x40030000;
 373
 374
 375 imm32 r0, 0xd0010000;
 376 imm32 r1, 0xd0010000;
 377 imm32 r2, 0xd0020000;
 378 imm32 r3, 0xd0030000;
 379 imm32 r4, 0xd0040000;
 380 imm32 r5, 0xd0050000;
 381 R6.L = -15;
 382 imm32 r7, 0xd0070000;
 383 R0.L = LSHIFT R0.H BY R6.L;
 384 R1.L = LSHIFT R1.H BY R6.L;
 385 R2.L = LSHIFT R2.H BY R6.L;
 386 R3.L = LSHIFT R3.H BY R6.L;
 387 R4.L = LSHIFT R4.H BY R6.L;
 388 R5.L = LSHIFT R5.H BY R6.L;
 389 //rl6 = lshift (rh6 by rl6);
 390 R7.L = LSHIFT R7.H BY R6.L;
 391 CHECKREG r0, 0xd0010001;
 392 CHECKREG r1, 0xd0010001;
 393 CHECKREG r2, 0xd0020001;
 394 CHECKREG r3, 0xd0030001;
 395 CHECKREG r4, 0xd0040001;
 396 CHECKREG r5, 0xd0050001;
 397 //CHECKREG r6, 0x60060000;
 398 CHECKREG r7, 0xd0070001;
 399
 400 imm32 r0, 0xe0010000;
 401 imm32 r1, 0xe0010000;
 402 imm32 r2, 0xe0020000;
 403 imm32 r3, 0xe0030000;
 404 imm32 r4, 0xe0040000;
 405 imm32 r5, 0xe0050000;
 406 imm32 r6, 0xe0060000;
 407 R7.L = -16;
 408 R0.H = LSHIFT R0.H BY R7.L;
 409 R1.H = LSHIFT R1.H BY R7.L;
 410 R2.H = LSHIFT R2.H BY R7.L;
 411 R3.H = LSHIFT R3.H BY R7.L;
 412 R4.H = LSHIFT R4.H BY R7.L;
 413 R5.H = LSHIFT R5.H BY R7.L;
 414 R6.H = LSHIFT R6.H BY R7.L;
 415 //rh7 = lshift (rh7 by rl7);
 416 CHECKREG r0, 0x00000000;
 417 CHECKREG r1, 0x00000000;
 418 CHECKREG r2, 0x00000000;
 419 CHECKREG r3, 0x00000000;
 420 CHECKREG r4, 0x00000000;
 421 CHECKREG r5, 0x00000000;
 422 CHECKREG r6, 0x00000000;
 423 //CHECKREG r7, -16;
 424
 425 pass