sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s

   1 //Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp
   2 // Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // lshift : neg data, count (+)=left (half reg)
  11 // d_lo = lshift (d_lo BY d_lo)
  12 // RLx by RLx
  13 imm32 r0, 0x00000000;
  14 imm32 r1, 0x0000c001;
  15 imm32 r2, 0x0000c002;
  16 imm32 r3, 0x0000c003;
  17 imm32 r4, 0x0000c004;
  18 imm32 r5, 0x0000c005;
  19 imm32 r6, 0x0000c006;
  20 imm32 r7, 0x0000c007;
  21 R0.L = R0.L << 1;
  22 R1.L = R1.L << 0;
  23 R2.L = R2.L << 0;
  24 R3.L = R3.L << 0;
  25 R4.L = R4.L << 0;
  26 R5.L = R5.L << 0;
  27 R6.L = R6.L << 0;
  28 R7.L = R7.L << 0;
  29 CHECKREG r0, 0x00000000;
  30 CHECKREG r1, 0x0000C001;
  31 CHECKREG r2, 0x0000C002;
  32 CHECKREG r3, 0x0000C003;
  33 CHECKREG r4, 0x0000C004;
  34 CHECKREG r5, 0x0000C005;
  35 CHECKREG r6, 0x0000C006;
  36 CHECKREG r7, 0x0000C007;
  37
  38 imm32 r0, 0x00008001;
  39 imm32 r1, 0x00000001;
  40 imm32 r2, 0x0000d002;
  41 imm32 r3, 0x0000e003;
  42 imm32 r4, 0x0000f004;
  43 imm32 r5, 0x0000c005;
  44 imm32 r6, 0x0000d006;
  45 imm32 r7, 0x0000e007;
  46 R1.L = R0.L << 1;
  47 R2.L = R1.L << 2;
  48 R3.L = R2.L << 3;
  49 R4.L = R3.L << 4;
  50 R5.L = R4.L << 5;
  51 R6.L = R5.L << 6;
  52 R7.L = R6.L << 7;
  53 R0.L = R7.L << 8;
  54 imm32 r1, 0x2000d001;
  55 imm32 r2, 0x2000000f;
  56 imm32 r3, 0x2000e003;
  57 imm32 r4, 0x2000f004;
  58 imm32 r5, 0x2200f005;
  59 imm32 r6, 0x2000f006;
  60 imm32 r7, 0x2000f007;
  61 imm32 r0, 0x2000c001;
  62
  63 R2.L = R0.L << 10;
  64 R3.L = R1.L << 12;
  65 R4.L = R2.L << 13;
  66 R5.L = R3.L << 14;
  67 R6.L = R4.L << 15;
  68 R7.L = R5.L << 15;
  69 R0.L = R6.L << 2;
  70 R1.L = R7.L << 3;
  71 CHECKREG r0, 0x20000000;
  72 CHECKREG r1, 0x20000000;
  73 CHECKREG r2, 0x20000400;
  74 CHECKREG r3, 0x20001000;
  75 CHECKREG r4, 0x20000000;
  76 CHECKREG r5, 0x22000000;
  77 CHECKREG r6, 0x20000000;
  78 CHECKREG r7, 0x20000000;
  79
  80 imm32 r0, 0x30009001;
  81 imm32 r1, 0x3000a001;
  82 imm32 r2, 0x3000b002;
  83 imm32 r3, 0x30000010;
  84 imm32 r4, 0x3000c004;
  85 imm32 r5, 0x3000d005;
  86 imm32 r6, 0x3000e006;
  87 imm32 r7, 0x3000f007;
  88 R3.L = R0.L << 12;
  89 R4.L = R1.L << 13;
  90 R5.L = R2.L << 14;
  91 R6.L = R3.L << 15;
  92 R7.L = R4.L << 11;
  93 R0.L = R5.L << 12;
  94 R1.L = R6.L << 13;
  95 R2.L = R7.L << 15;
  96 CHECKREG r0, 0x30000000;
  97 CHECKREG r1, 0x30000000;
  98 CHECKREG r2, 0x30000000;
  99 CHECKREG r3, 0x30001000;
 100 CHECKREG r4, 0x30002000;
 101 CHECKREG r5, 0x30008000;
 102 CHECKREG r6, 0x30000000;
 103 CHECKREG r7, 0x30000000;
 104 // RHx by RLx
 105 imm32 r0, 0x00000040;
 106 imm32 r1, 0x00010040;
 107 imm32 r2, 0x00020040;
 108 imm32 r3, 0x00030040;
 109 imm32 r4, 0x00040040;
 110 imm32 r5, 0x00050040;
 111 imm32 r6, 0x00060040;
 112 imm32 r7, 0x00070040;
 113 R0.L = R0.H << 0;
 114 R1.L = R1.H << 1;
 115 R2.L = R2.H << 2;
 116 R3.L = R3.H << 3;
 117 R4.L = R4.H << 4;
 118 R5.L = R5.H << 5;
 119 R6.L = R6.H << 6;
 120 R7.L = R7.H << 7;
 121 CHECKREG r0, 0x00000000;
 122 CHECKREG r1, 0x00010002;
 123 CHECKREG r2, 0x00020008;
 124 CHECKREG r3, 0x00030018;
 125 CHECKREG r4, 0x00040040;
 126 CHECKREG r5, 0x000500A0;
 127 CHECKREG r6, 0x00060180;
 128 CHECKREG r7, 0x00070380;
 129
 130 imm32 r0, 0x90010000;
 131 imm32 r1, 0x00010001;
 132 imm32 r2, 0x90020000;
 133 imm32 r3, 0x90030000;
 134 imm32 r4, 0x90040000;
 135 imm32 r5, 0x90050000;
 136 imm32 r6, 0x90060000;
 137 imm32 r7, 0x90070000;
 138 R1.L = R0.H << 1;
 139 R2.L = R1.H << 2;
 140 R3.L = R2.H << 3;
 141 R4.L = R3.H << 4;
 142 R5.L = R4.H << 5;
 143 R6.L = R5.H << 6;
 144 R7.L = R6.H << 7;
 145 R0.L = R7.H << 8;
 146 CHECKREG r1, 0x00012002;
 147 CHECKREG r2, 0x90020004;
 148 CHECKREG r3, 0x90038010;
 149 CHECKREG r4, 0x90040030;
 150 CHECKREG r5, 0x90050080;
 151 CHECKREG r6, 0x90060140;
 152 CHECKREG r7, 0x90070300;
 153 CHECKREG r0, 0x90010700;
 154
 155
 156 imm32 r0, 0xa0010000;
 157 imm32 r1, 0xa0010000;
 158 imm32 r2, 0xa002000f;
 159 imm32 r3, 0xa0030000;
 160 imm32 r4, 0xa0040000;
 161 imm32 r5, 0xa0050000;
 162 imm32 r6, 0xa0060000;
 163 imm32 r7, 0xa0070000;
 164 R2.L = R0.H << 15;
 165 R3.L = R1.H << 15;
 166 R4.L = R2.H << 15;
 167 R5.L = R3.H << 15;
 168 R6.L = R4.H << 15;
 169 R7.L = R5.H << 15;
 170 R0.L = R6.H << 15;
 171 R1.L = R7.H << 15;
 172 CHECKREG r0, 0xA0010000;
 173 CHECKREG r1, 0xA0018000;
 174 CHECKREG r2, 0xA0028000;
 175 CHECKREG r3, 0xA0038000;
 176 CHECKREG r4, 0xA0040000;
 177 CHECKREG r5, 0xA0058000;
 178 CHECKREG r6, 0xA0060000;
 179 CHECKREG r7, 0xA0078000;
 180
 181 imm32 r0, 0xc0010001;
 182 imm32 r1, 0xc0010001;
 183 imm32 r2, 0xc0020002;
 184 imm32 r3, 0xc0030010;
 185 imm32 r4, 0xc0040004;
 186 imm32 r5, 0xc0050005;
 187 imm32 r6, 0xc0060006;
 188 imm32 r7, 0xc0070007;
 189 R3.L = R0.H << 14;
 190 R4.L = R1.H << 14;
 191 R5.L = R2.H << 14;
 192 R6.L = R3.H << 14;
 193 R7.L = R4.H << 14;
 194 R0.L = R5.H << 14;
 195 R1.L = R6.H << 14;
 196 R2.L = R7.H << 14;
 197 CHECKREG r0, 0xC0014000;
 198 CHECKREG r1, 0xC0018000;
 199 CHECKREG r2, 0xC002C000;
 200 CHECKREG r3, 0xC0034000;
 201 CHECKREG r4, 0xC0044000;
 202 CHECKREG r5, 0xC0058000;
 203 CHECKREG r6, 0xC006C000;
 204 CHECKREG r7, 0xC0070000;
 205
 206 // RLx by RLx
 207 imm32 r0, 0x00000000;
 208 imm32 r1, 0x00000001;
 209 imm32 r2, 0x00000002;
 210 imm32 r3, 0x00000003;
 211 imm32 r4, 0x00000004;
 212 imm32 r5, 0x00000005;
 213 imm32 r6, 0x00000006;
 214 imm32 r7, 0x00000007;
 215 R0.H = R0.L << 12;
 216 R1.H = R1.L << 12;
 217 R2.H = R2.L << 13;
 218 R3.H = R3.L << 14;
 219 R4.H = R4.L << 15;
 220 R5.H = R5.L << 14;
 221 R6.H = R6.L << 7;
 222 R7.H = R7.L << 8;
 223 CHECKREG r0, 0x00000000;
 224 CHECKREG r1, 0x10000001;
 225 CHECKREG r2, 0x40000002;
 226 CHECKREG r3, 0xC0000003;
 227 CHECKREG r4, 0x00000004;
 228 CHECKREG r5, 0x40000005;
 229 CHECKREG r6, 0x03000006;
 230 CHECKREG r7, 0x07000007;
 231
 232 imm32 r0, 0x0000d001;
 233 imm32 r1, 0x00000001;
 234 imm32 r2, 0x0000d002;
 235 imm32 r3, 0x0000d003;
 236 imm32 r4, 0x0000d004;
 237 imm32 r5, 0x0000d005;
 238 imm32 r6, 0x0000d006;
 239 imm32 r7, 0x0000d007;
 240 R1.H = R0.L << 3;
 241 R2.H = R1.L << 4;
 242 R3.H = R2.L << 5;
 243 R4.H = R3.L << 6;
 244 R5.H = R4.L << 7;
 245 R6.H = R5.L << 8;
 246 R7.H = R6.L << 9;
 247 R0.H = R7.L << 8;
 248 CHECKREG r1, 0x80080001;
 249 CHECKREG r2, 0x0010D002;
 250 CHECKREG r3, 0x0040D003;
 251 CHECKREG r4, 0x00C0D004;
 252 CHECKREG r5, 0x0200D005;
 253 CHECKREG r6, 0x0500D006;
 254 CHECKREG r7, 0x0C00D007;
 255 CHECKREG r0, 0x0700D001;
 256
 257
 258 imm32 r0, 0x0000e001;
 259 imm32 r1, 0x0000e001;
 260 imm32 r2, 0x0000000f;
 261 imm32 r3, 0x0000e003;
 262 imm32 r4, 0x0000e004;
 263 imm32 r5, 0x0000e005;
 264 imm32 r6, 0x0000e006;
 265 imm32 r7, 0x0000e007;
 266 R2.H = R0.L << 15;
 267 R3.H = R1.L << 15;
 268 R4.H = R2.L << 15;
 269 R5.H = R3.L << 15;
 270 R6.H = R4.L << 15;
 271 R7.H = R5.L << 15;
 272 R0.H = R6.L << 15;
 273 R1.H = R7.L << 15;
 274 CHECKREG r0, 0x0000E001;
 275 CHECKREG r1, 0x8000E001;
 276 CHECKREG r2, 0x8000000F;
 277 CHECKREG r3, 0x8000E003;
 278 CHECKREG r4, 0x8000E004;
 279 CHECKREG r5, 0x8000E005;
 280 CHECKREG r6, 0x0000E006;
 281 CHECKREG r7, 0x8000E007;
 282
 283 imm32 r0, 0x0000f001;
 284 imm32 r1, 0x0000f001;
 285 imm32 r2, 0x0000f002;
 286 imm32 r3, 0x00000010;
 287 imm32 r4, 0x0000f004;
 288 imm32 r5, 0x0000f005;
 289 imm32 r6, 0x0000f006;
 290 imm32 r7, 0x0000f007;
 291 R3.H = R0.L << 13;
 292 R4.H = R1.L << 13;
 293 R5.H = R2.L << 13;
 294 R6.H = R3.L << 13;
 295 R7.H = R4.L << 13;
 296 R0.H = R5.L << 13;
 297 R1.H = R6.L << 13;
 298 R2.H = R7.L << 13;
 299 // RHx by RLx
 300 imm32 r0, 0x00000000;
 301 imm32 r1, 0x00010000;
 302 imm32 r2, 0x00020000;
 303 imm32 r3, 0x00030000;
 304 imm32 r4, 0x00040000;
 305 imm32 r5, 0x00050000;
 306 imm32 r6, 0x00060000;
 307 imm32 r7, 0x00070000;
 308 R0.H = R0.H << 0;
 309 R1.H = R1.H << 0;
 310 R2.H = R2.H << 0;
 311 R3.H = R3.H << 0;
 312 R4.H = R4.H << 0;
 313 R5.H = R5.H << 0;
 314 R6.H = R6.H << 0;
 315 R7.H = R7.H << 0;
 316 CHECKREG r0, 0x00000000;
 317 CHECKREG r1, 0x00010000;
 318 CHECKREG r2, 0x00020000;
 319 CHECKREG r3, 0x00030000;
 320 CHECKREG r4, 0x00040000;
 321 CHECKREG r5, 0x00050000;
 322 CHECKREG r6, 0x00060000;
 323 CHECKREG r7, 0x00070000;
 324
 325 imm32 r0, 0xa0010000;
 326 imm32 r1, 0x00010001;
 327 imm32 r2, 0xa0020000;
 328 imm32 r3, 0xa0030000;
 329 imm32 r4, 0xa0040000;
 330 imm32 r5, 0xa0050000;
 331 imm32 r6, 0xa0060000;
 332 imm32 r7, 0xa0070000;
 333 R1.H = R0.H << 1;
 334 R2.H = R1.H << 1;
 335 R3.H = R2.H << 1;
 336 R4.H = R3.H << 1;
 337 R5.H = R4.H << 1;
 338 R6.H = R5.H << 1;
 339 R7.H = R6.H << 1;
 340 R0.H = R7.H << 1;
 341 CHECKREG r1, 0x40020001;
 342 CHECKREG r2, 0x80040000;
 343 CHECKREG r3, 0x00080000;
 344 CHECKREG r4, 0x00100000;
 345 CHECKREG r5, 0x00200000;
 346 CHECKREG r6, 0x00400000;
 347 CHECKREG r7, 0x00800000;
 348 CHECKREG r0, 0x01000000;
 349
 350
 351 imm32 r0, 0xb0010000;
 352 imm32 r1, 0xb0010000;
 353 imm32 r2, 0xb002000f;
 354 imm32 r3, 0xb0030000;
 355 imm32 r4, 0xb0040000;
 356 imm32 r5, 0xb0050000;
 357 imm32 r6, 0xb0060000;
 358 imm32 r7, 0xb0070000;
 359 R2.H = R0.H << 15;
 360 R3.H = R1.H << 15;
 361 R4.H = R2.H << 15;
 362 R5.H = R3.H << 15;
 363 R6.H = R4.H << 15;
 364 R7.H = R5.H << 15;
 365 R0.H = R6.H << 15;
 366 R1.H = R7.H << 15;
 367 CHECKREG r0, 0x00000000;
 368 CHECKREG r1, 0x00000000;
 369 CHECKREG r2, 0x8000000F;
 370 CHECKREG r3, 0x80000000;
 371 CHECKREG r4, 0x00000000;
 372 CHECKREG r5, 0x00000000;
 373 CHECKREG r6, 0x00000000;
 374 CHECKREG r7, 0x00000000;
 375
 376 imm32 r0, 0xd0010000;
 377 imm32 r1, 0xd0010000;
 378 imm32 r2, 0xd0020000;
 379 imm32 r3, 0xd0030010;
 380 imm32 r4, 0xd0040000;
 381 imm32 r5, 0xd0050000;
 382 imm32 r6, 0xd0060000;
 383 imm32 r7, 0xd0070000;
 384 R6.H = R0.H << 12;
 385 R7.H = R1.H << 12;
 386 R0.H = R2.H << 12;
 387 R1.H = R3.H << 12;
 388 R2.H = R4.H << 12;
 389 R3.H = R5.H << 12;
 390 R4.H = R6.H << 12;
 391 R5.H = R7.H << 12;
 392 CHECKREG r0, 0x20000000;
 393 CHECKREG r1, 0x30000000;
 394 CHECKREG r2, 0x40000000;
 395 CHECKREG r3, 0x50000010;
 396 CHECKREG r4, 0x00000000;
 397 CHECKREG r5, 0x00000000;
 398 CHECKREG r6, 0x10000000;
 399 CHECKREG r7, 0x10000000;
 400
 401 pass