sim/testsuite/sim/bfin/c_interr_timer_tcount.S

   1 //Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp
   2 // Spec Reference: interrupt on HW TIMER tcount
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 //
  11 // Include Files
  12 //
  13
  14 include(std.inc)
  15 include(selfcheck.inc)
  16
  17 // Defines
  18
  19 #ifndef TCNTL
  20 #define TCNTL            0xFFE03000
  21 #endif
  22 #ifndef TPERIOD
  23 #define TPERIOD          0xFFE03004
  24 #endif
  25 #ifndef TSCALE
  26 #define TSCALE           0xFFE03008
  27 #endif
  28 #ifndef TCOUNT
  29 #define TCOUNT           0xFFE0300c
  30 #endif
  31 #ifndef EVT
  32 #define EVT              0xFFE02000
  33 #endif
  34 #ifndef EVT15
  35 #define EVT15            0xFFE0203c
  36 #endif
  37 #ifndef EVT_OVERRIDE
  38 #define EVT_OVERRIDE     0xFFE02100
  39 #endif
  40 #ifndef ITABLE
  41 #define ITABLE           0x000FF000
  42 #endif
  43 #ifndef PROGRAM_STACK
  44 #define PROGRAM_STACK    0x000FF100
  45 #endif
  46 #ifndef STACKSIZE
  47 #define STACKSIZE        0x00000300
  48 #endif
  49
  50 // Boot code
  51
  52  BOOT :
  53 INIT_R_REGS(0);                             // Initialize Dregs
  54 INIT_P_REGS(0);                             // Initialize Pregs
  55
  56      // CHECK_INIT(p5,   0x00BFFFFC);
  57      // CHECK_INIT(p5,   0xE0000000);
  58 include(symtable.inc)
  59 CHECK_INIT_DEF(p5);
  60
  61
  62 LD32(sp, 0x000FF200);
  63 LD32(p0, EVT);              // Setup Event Vectors and Handlers
  64
  65 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  66         [ P0 ++ ] = R0;
  67
  68 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  69         [ P0 ++ ] = R0;
  70
  71 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  72         [ P0 ++ ] = R0;
  73
  74 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  75         [ P0 ++ ] = R0;
  76
  77         [ P0 ++ ] = R0;                // IVT4 not used
  78
  79 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  80         [ P0 ++ ] = R0;
  81
  82 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  83         [ P0 ++ ] = R0;
  84
  85 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  86         [ P0 ++ ] = R0;
  87
  88 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  89         [ P0 ++ ] = R0;
  90
  91 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  92         [ P0 ++ ] = R0;
  93
  94 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  95         [ P0 ++ ] = R0;
  96
  97 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  98         [ P0 ++ ] = R0;
  99
 100 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
 101         [ P0 ++ ] = R0;
 102
 103 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
 104         [ P0 ++ ] = R0;
 105
 106 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
 107         [ P0 ++ ] = R0;
 108
 109 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
 110         [ P0 ++ ] = R0;
 111
 112 LD32(p0, EVT_OVERRIDE);
 113         R0 = 0;
 114         [ P0 ++ ] = R0;
 115         R0 = -1;     // Change this to mask interrupts (*)
 116         [ P0 ] = R0;   // IMASK
 117
 118 LD32_LABEL(p1, START);
 119
 120 LD32(p0, EVT15);
 121         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 122 CSYNC;
 123
 124 RAISE 15;    // after we RTI, INT 15 should be taken
 125
 126 LD32_LABEL(r7, START);
 127 RETI = r7;
 128 NOP;        // Workaround for Bug 217
 129 RTI;
 130 NOP;
 131 NOP;
 132
 133 //.code 0x200
 134  START :
 135         R7 = 0x0;
 136         R6 = 0x1;
 137         [ -- SP ] = RETI;        // Enable Nested Interrupts
 138
 139 WR_MMR(TCNTL,   0x00000001, p0, r0);   // Turn ON TMPWR (active state)
 140 WR_MMR(TPERIOD, 0x00000010, p0, r0);
 141 WR_MMR(TCOUNT,  0x00000002, p0, r0);
 142 WR_MMR(TSCALE,  0x00000001, p0, r0);
 143 WR_MMR(TCNTL,   0x00000003, p0, r0);    // enable Timer (TMPWR, TMREN)
 144 CSYNC;
 145
 146
 147 RD_MMR(TCNTL, p0, r5);
 148 CHECKREG(r5,    0x0000000B);
 149
 150 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 151 CSYNC;
 152 CHECKREG(r7,    0x00000001);
 153         R7 = 0;
 154 NOP;
 155 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
 156 WR_MMR(TPERIOD, 0x00000010, p0, r0);
 157 WR_MMR(TCOUNT,  0x00000002, p0, r0);
 158 WR_MMR(TSCALE,  0x00000003, p0, r0);
 159 WR_MMR(TCNTL,   0x00000003, p0, r0);        // Turn ON Timer
 160 CSYNC;
 161 NOP;
 162 NOP;
 163         // Read the contents of the Timer
 164
 165
 166 RD_MMR(TCNTL , p0, r3);
 167 CHECKREG(r3,    0x0000000B);
 168
 169 CHECKREG(r7,    0x00000001);
 170
 171
 172 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 173 CSYNC;
 174 NOP; NOP; NOP;
 175
 176
 177
 178
 179
 180 dbg_pass;        // Call Endtest Macro
 181
 182
 183
 184 //*********************************************************************
 185 //
 186 // Handlers for Events
 187 //
 188
 189 EHANDLE:            // Emulation Handler 0
 190 RTE;
 191
 192 RHANDLE:            // Reset Handler 1
 193 RTI;
 194
 195 NHANDLE:            // NMI Handler 2
 196 RTN;
 197
 198 XHANDLE:            // Exception Handler 3
 199 RTX;
 200
 201 HWHANDLE:           // HW Error Handler 5
 202 RTI;
 203
 204 THANDLE:            // Timer Handler 6
 205         R7 = R7 + R6;
 206 RTI;
 207
 208 I7HANDLE:           // IVG 7 Handler
 209 RTI;
 210
 211 I8HANDLE:           // IVG 8 Handler
 212 RTI;
 213
 214 I9HANDLE:           // IVG 9 Handler
 215 RTI;
 216
 217 I10HANDLE:          // IVG 10 Handler
 218 RTI;
 219
 220 I11HANDLE:          // IVG 11 Handler
 221 RTI;
 222
 223 I12HANDLE:          // IVG 12 Handler
 224 RTI;
 225
 226 I13HANDLE:          // IVG 13 Handler
 227 RTI;
 228
 229 I14HANDLE:          // IVG 14 Handler
 230 RTI;
 231
 232 I15HANDLE:          // IVG 15 Handler
 233         R5 = RETI;
 234         P0 = R5;
 235 JUMP ( P0 );
 236 RTI;
 237
 238 .section MEM_DATA_ADDR_1,"aw"
 239
 240 .space (STACKSIZE);
 241 STACK:
 242 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug