sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s

   1 //Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
   2 // Spec Reference: ldimmhalf dreg lo
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 INIT_R_REGS -1;
  11
  12 // test Dreg
  13 R0.L = 0x0001;
  14 R1.L = 0x0003;
  15 R2.L = 0x0005;
  16 R3.L = 0x0007;
  17 R4.L = 0x0009;
  18 R5.L = 0x000b;
  19 R6.L = 0x000d;
  20 R7.L = 0x000f;
  21 CHECKREG r0, 0xFFFF0001;
  22 CHECKREG r1, 0xFFFF0003;
  23 CHECKREG r2, 0xFFFF0005;
  24 CHECKREG r3, 0xFFFF0007;
  25 CHECKREG r4, 0xFFFF0009;
  26 CHECKREG r5, 0xFFFF000b;
  27 CHECKREG r6, 0xFFFF000D;
  28 CHECKREG r7, 0xFFFF000F;
  29
  30 R0.L = 0x0020;
  31 R1.L = 0x0040;
  32 R2.L = 0x0060;
  33 R3.L = 0x0080;
  34 R4.L = 0x00a0;
  35 R5.L = 0x00b0;
  36 R6.L = 0x00c0;
  37 R7.L = 0x00d0;
  38 CHECKREG r0, 0xFFFF0020;
  39 CHECKREG r1, 0xFFFF0040;
  40 CHECKREG r2, 0xFFFF0060;
  41 CHECKREG r3, 0xFFFF0080;
  42 CHECKREG r4, 0xFFFF00a0;
  43 CHECKREG r5, 0xFFFF00b0;
  44 CHECKREG r6, 0xFFFF00c0;
  45 CHECKREG r7, 0xFFFF00d0;
  46
  47 R0.L = 0x0100;
  48 R1.L = 0x0200;
  49 R2.L = 0x0300;
  50 R3.L = 0x0400;
  51 R4.L = 0x0500;
  52 R5.L = 0x0600;
  53 R6.L = 0x0700;
  54 R7.L = 0x0800;
  55 CHECKREG r0, 0xFFFF0100;
  56 CHECKREG r1, 0xFFFF0200;
  57 CHECKREG r2, 0xFFFF0300;
  58 CHECKREG r3, 0xFFFF0400;
  59 CHECKREG r4, 0xFFFF0500;
  60 CHECKREG r5, 0xFFFF0600;
  61 CHECKREG r6, 0xFFFF0700;
  62 CHECKREG r7, 0xFFFF0800;
  63
  64 R0 = 0;
  65 R1 = 0;
  66 R2 = 0;
  67 R3 = 0;
  68 R4 = 0;
  69 R5 = 0;
  70 R6 = 0;
  71 R7 = 0;
  72 R0.L = 0x7fff;
  73 R1.L = 0x7ffe;
  74 R2.L = -32768;
  75 R3.L = -32767;
  76 R4.L = 32767;
  77 R5.L = 32766;
  78 R6.L = 32765;
  79 R7.L = 32764;
  80 CHECKREG r0, 0x00007fff;
  81 CHECKREG r1, 0x00007ffe;
  82 CHECKREG r2, 0x00008000;
  83 CHECKREG r3, 0x00008001;
  84 CHECKREG r4, 0x00007FFF;
  85 CHECKREG r5, 0x00007FFE;
  86 CHECKREG r6, 0x00007FFD;
  87 CHECKREG r7, 0x00007FFC;
  88
  89 pass