sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s

   1 //Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8 // Spec Reference: ldimmhalf lz ibml
   9
  10
  11
  12
  13 I0 = 0x2001 (Z);
  14 I1 = 0x2003 (Z);
  15 I2 = 0x2005 (Z);
  16 I3 = 0x2007 (Z);
  17 L0 = 0x2009 (Z);
  18 L1 = 0x200b (Z);
  19 L2 = 0x200d (Z);
  20 L3 = 0x200f (Z);
  21
  22
  23 R0 = I0;
  24 R1 = I1;
  25 R2 = I2;
  26 R3 = I3;
  27 R4 = L0;
  28 R5 = L1;
  29 R6 = L2;
  30 R7 = L3;
  31 CHECKREG r0, 0x00002001;
  32 CHECKREG r1, 0x00002003;
  33 CHECKREG r2, 0x00002005;
  34 CHECKREG r3, 0x00002007;
  35 CHECKREG r4, 0x00002009;
  36 CHECKREG r5, 0x0000200b;
  37 CHECKREG r6, 0x0000200d;
  38 CHECKREG r7, 0x0000200f;
  39
  40 I0 = 0x0111 (Z);
  41 I1 = 0x1111 (Z);
  42 I2 = 0x2222 (Z);
  43 I3 = 0x3333 (Z);
  44 L0 = 0x4444 (Z);
  45 L1 = 0x5555 (Z);
  46 L2 = 0x6666 (Z);
  47 L3 = 0x7777 (Z);
  48 R0 = I0;
  49 R1 = I1;
  50 R2 = I2;
  51 R3 = I3;
  52 R4 = L0;
  53 R5 = L1;
  54 R6 = L2;
  55 R7 = L3;
  56 CHECKREG r0, 0x00000111;
  57 CHECKREG r1, 0x00001111;
  58 CHECKREG r2, 0x00002222;
  59 CHECKREG r3, 0x00003333;
  60 CHECKREG r4, 0x00004444;
  61 CHECKREG r5, 0x00005555;
  62 CHECKREG r6, 0x00006666;
  63 CHECKREG r7, 0x00007777;
  64
  65 I0 = 0x8888 (Z);
  66 I1 = 0x9aaa (Z);
  67 I2 = 0xabbb (Z);
  68 I3 = 0xbccc (Z);
  69 L0 = 0xcddd (Z);
  70 L1 = 0xdeee (Z);
  71 L2 = 0xefff (Z);
  72 L3 = 0xf111 (Z);
  73 R0 = I0;
  74 R1 = I1;
  75 R2 = I2;
  76 R3 = I3;
  77 R4 = L0;
  78 R5 = L1;
  79 R6 = L2;
  80 R7 = L3;
  81 CHECKREG r0, 0x00008888;
  82 CHECKREG r1, 0x00009aaa;
  83 CHECKREG r2, 0x0000abbb;
  84 CHECKREG r3, 0x0000bccc;
  85 CHECKREG r4, 0x0000cddd;
  86 CHECKREG r5, 0x0000deee;
  87 CHECKREG r6, 0x0000efff;
  88 CHECKREG r7, 0x0000f111;
  89
  90 B0 = 0x3001 (Z);
  91 B1 = 0x3003 (Z);
  92 B2 = 0x3005 (Z);
  93 B3 = 0x3007 (Z);
  94 M0 = 0x3009 (Z);
  95 M1 = 0x300b (Z);
  96 M2 = 0x300d (Z);
  97 M3 = 0x300f (Z);
  98
  99 R0 = B0;
 100 R1 = B1;
 101 R2 = B2;
 102 R3 = B3;
 103 R4 = M0;
 104 R5 = M1;
 105 R6 = M2;
 106 R7 = M3;
 107 CHECKREG r0, 0x00003001;
 108 CHECKREG r1, 0x00003003;
 109 CHECKREG r2, 0x00003005;
 110 CHECKREG r3, 0x00003007;
 111 CHECKREG r4, 0x00003009;
 112 CHECKREG r5, 0x0000300B;
 113 CHECKREG r6, 0x0000300d;
 114 CHECKREG r7, 0x0000300f;
 115
 116
 117 B0 = 0x0110 (Z);
 118 B1 = 0x1110 (Z);
 119 B2 = 0x2220 (Z);
 120 B3 = 0x3330 (Z);
 121 M0 = 0x4440 (Z);
 122 M1 = 0x5550 (Z);
 123 M2 = 0x6660 (Z);
 124 M3 = 0x7770 (Z);
 125 R0 = B0;
 126 R1 = B1;
 127 R2 = B2;
 128 R3 = B3;
 129 R4 = M0;
 130 R5 = M1;
 131 R6 = M2;
 132 R7 = M3;
 133 CHECKREG r0, 0x00000110;
 134 CHECKREG r1, 0x00001110;
 135 CHECKREG r2, 0x00002220;
 136 CHECKREG r3, 0x00003330;
 137 CHECKREG r4, 0x00004440;
 138 CHECKREG r5, 0x00005550;
 139 CHECKREG r6, 0x00006660;
 140 CHECKREG r7, 0x00007770;
 141
 142 B0 = 0xf880 (Z);
 143 B1 = 0xfaa0 (Z);
 144 B2 = 0xfbb0 (Z);
 145 B3 = 0xfcc0 (Z);
 146 M0 = 0xfdd0 (Z);
 147 M1 = 0xfee0 (Z);
 148 M2 = 0xfff0 (Z);
 149 M3 = 0xf110 (Z);
 150 R0 = B0;
 151 R1 = B1;
 152 R2 = B2;
 153 R3 = B3;
 154 R4 = M0;
 155 R5 = M1;
 156 R6 = M2;
 157 R7 = M3;
 158 CHECKREG r0, 0x0000f880;
 159 CHECKREG r1, 0x0000faa0;
 160 CHECKREG r2, 0x0000fbb0;
 161 CHECKREG r3, 0x0000fcc0;
 162 CHECKREG r4, 0x0000fdd0;
 163 CHECKREG r5, 0x0000fee0;
 164 CHECKREG r6, 0x0000fff0;
 165 CHECKREG r7, 0x0000f110;
 166
 167
 168 pass