sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s

   1 //Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp
   2 // Spec Reference: ldimmhalf lz & hi dreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS -1;
  10
  11
  12 // test Dreg
  13 R0 = 0x0001 (Z);
  14 R0.H = 0x0000;
  15 R1 = 0x0003 (Z);
  16 R1.H = 0x0002;
  17 R2 = 0x0005 (Z);
  18 R2.H = 0x0004;
  19 R3 = 0x0007 (Z);
  20 R3.H = 0x0006;
  21 R4 = 0x0009 (Z);
  22 R4.H = 0x0008;
  23 R5 = 0x000b (Z);
  24 R5.H = 0x000a;
  25 R6 = 0x000d (Z);
  26 R6.H = 0x000c;
  27 R7 = 0x000f (Z);
  28 R7.H = 0x000e;
  29 CHECKREG r0, 0x00000001;
  30 CHECKREG r1, 0x00020003;
  31 CHECKREG r2, 0x00040005;
  32 CHECKREG r3, 0x00060007;
  33 CHECKREG r4, 0x00080009;
  34 CHECKREG r5, 0x000a000b;
  35 CHECKREG r6, 0x000c000d;
  36 CHECKREG r7, 0x000e000f;
  37
  38 R0 = 0x0010 (Z);
  39 R0.H = 0x0000;
  40 R1 = 0x0030 (Z);
  41 R1.H = 0x0020;
  42 R2 = 0x0050 (Z);
  43 R2.H = 0x0040;
  44 R3 = 0x0070 (Z);
  45 R3.H = 0x0060;
  46 R4 = 0x0090 (Z);
  47 R4.H = 0x0080;
  48 R5 = 0x00b0 (Z);
  49 R5.H = 0x00a0;
  50 R6 = 0x00d0 (Z);
  51 R6.H = 0x00c0;
  52 R7 = 0x00f0 (Z);
  53 R7.H = 0x00e0;
  54 CHECKREG r0, 0x00000010;
  55 CHECKREG r1, 0x00200030;
  56 CHECKREG r2, 0x00400050;
  57 CHECKREG r3, 0x00600070;
  58 CHECKREG r4, 0x00800090;
  59 CHECKREG r5, 0x00a000b0;
  60 CHECKREG r6, 0x00c000d0;
  61 CHECKREG r7, 0x00e000f0;
  62
  63 R0 = 0x0100 (Z);
  64 R0.H = 0x0000;
  65 R1 = 0x0300 (Z);
  66 R1.H = 0x0200;
  67 R2 = 0x0500 (Z);
  68 R2.H = 0x0400;
  69 R3 = 0x0700 (Z);
  70 R3.H = 0x0600;
  71 R4 = 0x0900 (Z);
  72 R4.H = 0x0800;
  73 R5 = 0x0b00 (Z);
  74 R5.H = 0x0a00;
  75 R6 = 0x0d00 (Z);
  76 R6.H = 0x0c00;
  77 R7 = 0x0f00 (Z);
  78 R7.H = 0x0e00;
  79 CHECKREG r0, 0x00000100;
  80 CHECKREG r1, 0x02000300;
  81 CHECKREG r2, 0x04000500;
  82 CHECKREG r3, 0x06000700;
  83 CHECKREG r4, 0x08000900;
  84 CHECKREG r5, 0x0a000b00;
  85 CHECKREG r6, 0x0c000d00;
  86 CHECKREG r7, 0x0e000f00;
  87
  88 R0 = 0x1000 (Z);
  89 R0.H = 0x0000;
  90 R1 = 0x3000 (Z);
  91 R1.H = 0x2000;
  92 R2 = 0x5000 (Z);
  93 R2.H = 0x4000;
  94 R3 = 0x7000 (Z);
  95 R3.H = 0x6000;
  96 R4 = 0x9000 (Z);
  97 R4.H = 0x8000;
  98 R5 = 0xb000 (Z);
  99 R5.H = 0xa000;
 100 R6 = 0xd000 (Z);
 101 R6.H = 0xc000;
 102 R7 = 0xf000 (Z);
 103 R7.H = 0xe000;
 104 CHECKREG r0, 0x00001000;
 105 CHECKREG r1, 0x20003000;
 106 CHECKREG r2, 0x40005000;
 107 CHECKREG r3, 0x60007000;
 108 CHECKREG r4, 0x80009000;
 109 CHECKREG r5, 0xa000b000;
 110 CHECKREG r6, 0xc000d000;
 111 CHECKREG r7, 0xe000f000;
 112
 113 pass