1 //Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp
2 // Spec Reference: c_ldst ld d [p] h
5 .include "testutils.inc"
8 loadsym p1, DATA_ADDR_1;
9 loadsym p2, DATA_ADDR_2;
11 loadsym p3, DATA_ADDR_3;
13 loadsym p4, DATA_ADDR_4;
14 loadsym p5, DATA_ADDR_5;
15 loadsym fp, DATA_ADDR_6;
17 // load 16 bits from memory and zero extend into 32-bit reg
29 CHECKREG r0, 0x00000203;
30 CHECKREG r1, 0x00002223;
31 CHECKREG r2, 0x00004243;
32 CHECKREG r3, 0x00006263;
33 CHECKREG r4, 0x00008283;
34 CHECKREG r5, 0x00008283;
35 CHECKREG r6, 0x00000203;
46 CHECKREG r0, 0x00000203;
47 CHECKREG r1, 0x00002223;
48 CHECKREG r2, 0x00004243;
49 CHECKREG r3, 0x00006263;
50 CHECKREG r4, 0x00008283;
51 CHECKREG r5, 0x00000203;
52 CHECKREG r7, 0x00000203;
63 CHECKREG r0, 0x00002223;
64 CHECKREG r1, 0x00002223;
65 CHECKREG r2, 0x00004243;
66 CHECKREG r3, 0x00006263;
67 CHECKREG r4, 0x00008283;
68 CHECKREG r5, 0x00000203;
69 CHECKREG r7, 0x00000203;
81 CHECKREG r0, 0x00002223;
82 CHECKREG r1, 0x00004243;
83 CHECKREG r2, 0x00004243;
84 CHECKREG r3, 0x00006263;
85 CHECKREG r4, 0x00008283;
86 CHECKREG r5, 0x00000203;
87 CHECKREG r7, 0x00000203;
91 // Pre-load memory with known data
92 // More data is defined than will actually be used