1 //Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp
2 // Spec Reference: c_ldst ld d [p--] xb
6 .include "testutils.inc"
20 I1 = P3; P3 = I0; I3 = SP; SP = I2;
21 loadsym p5, DATA_ADDR_1, 0x20;
22 loadsym p1, DATA_ADDR_2, 0x20;
23 loadsym p2, DATA_ADDR_3, 0x20;
24 loadsym i1, DATA_ADDR_4, 0x20;
25 loadsym p4, DATA_ADDR_5, 0x20;
26 loadsym fp, DATA_ADDR_6, 0x20;
27 loadsym i3, DATA_ADDR_7, 0x20;
37 CHECKREG r0, 0xFFFFFFEE;
38 CHECKREG r1, 0x00000013;
39 CHECKREG r2, 0x00000023;
40 CHECKREG r3, 0xFFFFFFA3;
41 CHECKREG r4, 0x00000000;
42 CHECKREG r5, 0x00000044;
43 CHECKREG r6, 0xFFFFFF94;
44 CHECKREG r7, 0xFFFFFFCD;
53 CHECKREG r0, 0xFFFFFFC5;
54 CHECKREG r1, 0x0000007C;
55 CHECKREG r2, 0xFFFFFF9C;
56 CHECKREG r3, 0x0000001C;
57 CHECKREG r4, 0xFFFFFF9C;
58 CHECKREG r5, 0x00000044;
59 CHECKREG r6, 0x0000001C;
60 CHECKREG r7, 0x0000003C;
69 CHECKREG r0, 0x0000003D;
70 CHECKREG r1, 0xFFFFFFC6;
71 CHECKREG r2, 0x0000007D;
72 CHECKREG r3, 0xFFFFFF9D;
73 CHECKREG r4, 0x0000001D;
74 CHECKREG r5, 0xFFFFFF9D;
75 CHECKREG r6, 0x0000001C;
76 CHECKREG r7, 0x0000001D;
81 // Pre-load memory with known data
82 // More data is defined than will actually be used