1 //Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp
2 // Spec Reference: c_ldstidxl load dreg (ld with indexed addressing)
5 .include "testutils.inc"
17 loadsym p1, DATA_ADDR_1, 0x00;
18 loadsym p2, DATA_ADDR_2, 0xA0;
19 loadsym p4, DATA_ADDR_2, 0x70;
20 loadsym p5, DATA_ADDR_1, 0x70;
21 loadsym fp, DATA_ADDR_2, 0x70;
31 CHECKREG r0, 0x08090A0B;
32 CHECKREG r1, 0x22232425;
33 CHECKREG r2, 0x82838485;
34 CHECKREG r3, 0x0C0D0E0F;
35 CHECKREG r4, 0x55667788;
36 CHECKREG r5, 0x14151617;
37 CHECKREG r6, 0x66676869;
38 CHECKREG r7, 0x08090A0B;
48 CHECKREG r0, 0xD3D4D5D6;
49 CHECKREG r1, 0xDBDCDDDE;
50 CHECKREG r2, 0xA455565A;
51 CHECKREG r3, 0xA667686A;
52 CHECKREG r4, 0x96E899EA;
53 CHECKREG r5, 0x4C4D4E4F;
54 CHECKREG r6, 0x94E899EA;
55 CHECKREG r7, 0x4C4D4E4F;
65 CHECKREG r0, 0x50515253;
66 CHECKREG r1, 0x94E899EA;
67 CHECKREG r2, 0x48494A4B;
68 CHECKREG r3, 0x96E899EA;
69 CHECKREG r4, 0x40414243;
70 CHECKREG r5, 0xA667686A;
71 CHECKREG r6, 0x99E899EA;
72 CHECKREG r7, 0x96E899EA;
82 CHECKREG r0, 0x34353637;
83 CHECKREG r1, 0x62636465;
84 CHECKREG r2, 0x42434445;
85 CHECKREG r3, 0x54555657;
86 CHECKREG r4, 0x50515253;
87 CHECKREG r5, 0x46474849;
88 CHECKREG r6, 0x58596061;
89 CHECKREG r7, 0x04050607;
99 CHECKREG r0, 0x92E899EA;
100 CHECKREG r1, 0x91E899EA;
101 CHECKREG r2, 0x4C4D4E4F;
102 CHECKREG r3, 0xDBDCDDDE;
103 CHECKREG r4, 0x40414243;
104 CHECKREG r5, 0x96E899EA;
105 CHECKREG r6, 0x48494A4B;
106 CHECKREG r7, 0x50515253;
110 // Pre-load memory with known data
111 // More data is defined than will actually be used