1 //Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp
2 // Spec Reference: c_ldstidxl store preg
5 .include "testutils.inc"
31 I1 = P3; P3 = I0; I3 = SP; SP = I2;
32 loadsym p1, DATA_ADDR_1, 0x0000;
33 loadsym p2, DATA_ADDR_2, 0x00c8;
40 [ P2 + -0x1020 ] = P4;
41 [ P2 + -0x1024 ] = P5;
42 [ P2 + -0x1028 ] = SP;
43 [ P2 + -0x1034 ] = FP;
48 R2 = [ P2 + -0x1020 ];
49 R7 = [ P2 + -0x1024 ];
50 R0 = [ P2 + -0x1028 ];
51 R1 = [ P2 + -0x1034 ];
52 CHECKREG r0, 0x00001ACE;
53 CHECKREG r1, 0x00006DEF;
54 CHECKREG r2, 0x00004567;
55 CHECKREG r3, 0x00000123;
56 CHECKREG r4, 0x00004567;
57 CHECKREG r5, 0x00000123;
58 CHECKREG r6, 0x000079AB;
59 CHECKREG r7, 0x000079AB;
75 I1 = P3; P3 = I0; I3 = SP; SP = I2;
76 loadsym i1, DATA_ADDR_1, 0x0000;
77 loadsym p4, DATA_ADDR_2, 0x00c8;
84 [ P4 + -0x1054 ] = P2;
85 [ P4 + -0x1058 ] = P5;
86 [ P4 + -0x1060 ] = SP;
87 [ P4 + -0x1064 ] = FP;
92 R2 = [ P4 + -0x1054 ];
93 R5 = [ P4 + -0x1058 ];
94 R6 = [ P4 + -0x1060 ];
95 R7 = [ P4 + -0x1064 ];
96 CHECKREG r0, 0x00001234;
97 CHECKREG r1, 0x00003456;
98 CHECKREG r2, 0x00001234;
99 CHECKREG r3, 0x00001234;
100 CHECKREG r4, 0x00003456;
101 CHECKREG r5, 0x00005E23;
102 CHECKREG r6, 0x00006378;
103 CHECKREG r7, 0x00002AC5;
106 imm32 r0, 0x10cf50c0;
107 imm32 r1, 0x20ce60c1;
108 imm32 r2, 0x30c370c2;
109 imm32 r3, 0x40cc80c3;
110 imm32 r4, 0x50cb90c4;
111 imm32 r5, 0x60caa0c5;
112 imm32 r6, 0x70c9b0c6;
113 imm32 r7, 0xd0c8c0c7;
120 I1 = P3; P3 = I0; I3 = SP; SP = I2;
121 loadsym p5, DATA_ADDR_1, 0x0000;
122 loadsym i3, DATA_ADDR_2, 0x00c8;
125 [ P5 + 0x1004 ] = P2;
126 [ P5 + 0x1008 ] = P1;
127 [ P5 + 0x1014 ] = P2;
128 [ P5 + 0x1018 ] = P3;
129 [ SP + -0x1020 ] = P4;
130 [ SP + -0x1024 ] = P2;
131 [ SP + -0x1028 ] = P3;
132 [ SP + -0x1034 ] = FP;
133 R6 = [ P5 + 0x1004 ];
134 R5 = [ P5 + 0x1008 ];
135 R4 = [ P5 + 0x1014 ];
136 R3 = [ P5 + 0x1018 ];
137 R2 = [ SP + -0x1020 ];
138 R0 = [ SP + -0x1024 ];
139 R7 = [ SP + -0x1028 ];
140 R1 = [ SP + -0x1034 ];
141 CHECKREG r0, 0x00007345;
142 CHECKREG r1, 0x00005BCD;
143 CHECKREG r2, 0x00005789;
144 CHECKREG r3, 0x00003230;
145 CHECKREG r4, 0x00007345;
146 CHECKREG r5, 0x00002125;
147 CHECKREG r6, 0x00007345;
148 CHECKREG r7, 0x00003230;
151 imm32 r0, 0x60df50d0;
152 imm32 r1, 0x70de60d1;
153 imm32 r2, 0x80dd70d2;
154 imm32 r3, 0x90dc80d3;
155 imm32 r4, 0xa0db90d4;
156 imm32 r5, 0xb0daa0d5;
157 imm32 r6, 0xc0d9b0d6;
158 imm32 r7, 0xd0d8c0d7;
165 I1 = P3; P3 = I0; I3 = SP; SP = I2;
166 loadsym fp, DATA_ADDR_1, 0x0010;
168 [ FP + 0x1034 ] = P1;
169 [ FP + 0x2040 ] = P1;
170 [ FP + 0x1144 ] = P2;
171 [ FP + 0x2048 ] = P3;
172 [ FP + 0x1050 ] = P4;
173 [ FP + 0x2058 ] = P5;
174 [ FP + 0x1160 ] = P2;
175 [ FP + 0x2064 ] = SP;
176 R3 = [ FP + 0x1034 ];
177 R4 = [ FP + 0x2040 ];
178 R0 = [ FP + 0x1144 ];
179 R1 = [ FP + 0x2048 ];
180 R2 = [ FP + 0x1050 ];
181 R5 = [ FP + 0x2058 ];
182 R6 = [ FP + 0x1160 ];
183 R7 = [ FP + 0x2064 ];
184 CHECKREG r0, 0x00001122;
185 CHECKREG r1, 0x00003455;
186 CHECKREG r2, 0x00006677;
187 CHECKREG r3, 0x00005BCD;
188 CHECKREG r4, 0x00005BCD;
189 CHECKREG r5, 0x000058AB;
190 CHECKREG r6, 0x00001122;
191 CHECKREG r7, 0x00001ace;
195 // Pre-load memory with known data
196 // More data is defined than will actually be used
199 // Make sure there is space between the text and data sections
708 // Make sure there is space for us to scribble