1 //Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp
2 // Spec Reference: c_ldstii store dreg
5 .include "testutils.inc"
17 loadsym p1, DATA_ADDR_1;
18 loadsym p2, DATA_ADDR_2;
20 loadsym p3, DATA_ADDR_3;
22 loadsym p4, DATA_ADDR_4;
23 loadsym p5, DATA_ADDR_1;
24 loadsym fp, DATA_ADDR_2;
26 loadsym sp, DATA_ADDR_3;
37 R6 = W [ P1 + 2 ] (Z);
38 R5 = W [ P1 + 4 ] (Z);
39 R4 = W [ P1 + 6 ] (Z);
40 R3 = W [ P1 + 8 ] (Z);
41 R2 = W [ P2 + 10 ] (Z);
42 R7 = W [ P2 + 12 ] (Z);
43 R0 = W [ P2 + 14 ] (Z);
44 R1 = W [ P2 + 16 ] (Z);
45 CHECKREG r0, 0x0000B0A6;
46 CHECKREG r1, 0x0000C0A7;
47 CHECKREG r2, 0x000090A4;
48 CHECKREG r3, 0x000080A3;
49 CHECKREG r4, 0x000070A2;
50 CHECKREG r5, 0x000060A1;
51 CHECKREG r6, 0x000050A0;
52 CHECKREG r7, 0x0000A0A5;
71 R3 = W [ P3 + 18 ] (Z);
72 R4 = W [ P3 + 20 ] (Z);
73 R0 = W [ P3 + 22 ] (Z);
74 R1 = W [ P3 + 24 ] (Z);
75 R2 = W [ P4 + 26 ] (Z);
76 R5 = W [ P4 + 28 ] (Z);
77 R6 = W [ P4 + 30 ] (Z);
78 R7 = W [ P4 + 32 ] (Z);
79 CHECKREG r0, 0x000070B2;
80 CHECKREG r1, 0x000080B3;
81 CHECKREG r2, 0x000090B4;
82 CHECKREG r3, 0x000050B0;
83 CHECKREG r4, 0x000060B1;
84 CHECKREG r5, 0x0000A0B5;
85 CHECKREG r6, 0x0000B0B6;
86 CHECKREG r7, 0x0000C0B7;
108 R6 = W [ P5 + 34 ] (Z);
109 R5 = W [ P5 + 36 ] (Z);
110 R4 = W [ P5 + 38 ] (Z);
111 R3 = W [ P5 + 40 ] (Z);
113 R2 = W [ SP + 42 ] (Z);
114 R0 = W [ SP + 44 ] (Z);
115 R7 = W [ SP + 46 ] (Z);
116 R1 = W [ SP + 48 ] (Z);
118 CHECKREG r0, 0x0000A0C5;
119 CHECKREG r1, 0x0000C0C7;
120 CHECKREG r2, 0x000090C4;
122 CHECKREG r3, 0x000080C3;
123 CHECKREG r4, 0x000070C2;
124 CHECKREG r5, 0x000060C1;
125 CHECKREG r6, 0x000050C0;
128 imm32 r0, 0x60df50d0;
129 imm32 r1, 0x70de60d1;
130 imm32 r2, 0x80dd70d2;
131 imm32 r3, 0x90dc80d3;
132 imm32 r4, 0xa0db90d4;
133 imm32 r5, 0xb0daa0d5;
134 imm32 r6, 0xc0d9b0d6;
135 imm32 r7, 0xd0d8c0d7;
144 R3 = W [ FP + 50 ] (Z);
145 R4 = W [ FP + 52 ] (Z);
146 R0 = W [ FP + 54 ] (Z);
147 R1 = W [ FP + 56 ] (Z);
148 R2 = W [ FP + 58 ] (Z);
149 R5 = W [ FP + 60 ] (Z);
150 R6 = W [ FP + 62 ] (Z);
151 R7 = W [ FP + 64 ] (Z);
152 CHECKREG r0, 0x000070D2;
153 CHECKREG r1, 0x000080D3;
154 CHECKREG r2, 0x000090D4;
155 CHECKREG r3, 0x000050D0;
156 CHECKREG r4, 0x000060D1;
157 CHECKREG r5, 0x0000A0D5;
158 CHECKREG r6, 0x0000B0D6;
159 CHECKREG r7, 0x0000C0D7;
163 // Pre-load memory with known data
164 // More data is defined than will actually be used