sim/testsuite/sim/bfin/c_loopsetup_overlap.s

   1 //Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp
   2 // Spec Reference: loopsetup overlap
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS 0;
  10
  11 ASTAT = r0;
  12
  13 //p0 = 2;
  14 P1 = 3;
  15 P2 = 4;
  16 P3 = 5;
  17 P4 = 6;
  18 P5 = 7;
  19 SP = 8;
  20 FP = 9;
  21
  22 R0 = 0x05;
  23 R1 = 0x10;
  24 R2 = 0x20;
  25 R3 = 0x30;
  26 R4 = 0x40 (X);
  27 R5 = 0x50 (X);
  28 R6 = 0x60 (X);
  29 R7 = 0x70 (X);
  30 LSETUP ( start1 , end1 ) LC0 = P1;
  31 start1: R0 += 1;
  32  R1 += -2;
  33 LSETUP ( start2 , end2 ) LC1 = P2;
  34 start2: R4 += 4;
  35 end2: R5 += -5;
  36  R3 += 1;
  37 end1: R2 += 3;
  38  R3 += 4;
  39
  40 LSETUP ( start3 , end3 ) LC1 = P3;
  41 start3: R6 += 6;
  42 LSETUP ( start4 , end4 ) LC0 = P4 >> 1;
  43 start4: R0 += 1;
  44  R1 += -2;
  45 end3: R2 += 3;
  46  R3 += 4;
  47 end4: R7 += -7;
  48  R3 += 1;
  49 CHECKREG r0, 0x0000000F;
  50 CHECKREG r1, 0xFFFFFFFC;
  51 CHECKREG r2, 0x0000003E;
  52 CHECKREG r3, 0x00000044;
  53 CHECKREG r4, 0x00000070;
  54 CHECKREG r5, 0x00000014;
  55 CHECKREG r6, 0x0000007E;
  56 CHECKREG r7, 0x0000005B;
  57
  58 R0 = 0x05;
  59 R1 = 0x10;
  60 R2 = 0x20;
  61 R3 = 0x30;
  62 R4 = 0x40 (X);
  63 R5 = 0x50 (X);
  64 R6 = 0x60 (X);
  65 R7 = 0x70 (X);
  66 LSETUP ( start5 , end5 ) LC0 = P5;
  67 start5: R4 += 1;
  68 LSETUP ( start6 , end6 ) LC1 = SP >> 1;
  69 start6: R6 += 4;
  70 end5: R7 += -5;
  71  R3 += 6;
  72 end6: R5 += -2;
  73  R3 += 3;
  74 CHECKREG r0, 0x00000005;
  75 CHECKREG r1, 0x00000010;
  76 CHECKREG r2, 0x00000020;
  77 CHECKREG r3, 0x0000004B;
  78 CHECKREG r4, 0x00000047;
  79 CHECKREG r5, 0x00000048;
  80 CHECKREG r6, 0x00000088;
  81 CHECKREG r7, 0x0000003E;
  82 LSETUP ( start7 , end7 ) LC0 = FP;
  83 start7: R4 += 4;
  84 end7: R5 += -5;
  85  R3 += 6;
  86 CHECKREG r0, 0x00000005;
  87 CHECKREG r1, 0x00000010;
  88 CHECKREG r2, 0x00000020;
  89 CHECKREG r3, 0x00000051;
  90 CHECKREG r4, 0x0000006B;
  91 CHECKREG r5, 0x0000001B;
  92 CHECKREG r6, 0x00000088;
  93 CHECKREG r7, 0x0000003E;
  94
  95 P1 = 8;
  96 P2 = 10;
  97 P3 = 12;
  98 P4 = 14;
  99 P5 = 16;
 100 SP = 18;
 101 FP = 20;
 102
 103 R0 = 0x05;
 104 R1 = 0x10;
 105 R2 = 0x20;
 106 R3 = 0x30;
 107 R4 = 0x40 (X);
 108 R5 = 0x50 (X);
 109 R6 = 0x60 (X);
 110 R7 = 0x70 (X);
 111 LSETUP ( start11 , end11 ) LC1 = P1;
 112 start11: R0 += 1;
 113  R1 += -1;
 114 LSETUP ( start15 , end15 ) LC0 = P5;
 115 start15: R4 += 5;
 116 end11: R5 += -14;
 117  R3 += 1;
 118 end15: R2 += 17;
 119  R3 += 12;
 120 LSETUP ( start13 , end13 ) LC1 = P3;
 121 start13: R6 += 1;
 122 LSETUP ( start12 , end12 ) LC0 = P2;
 123 start12: R4 += 22;
 124 end13: R5 += -11;
 125  R3 += 13;
 126 end12: R7 += -1;
 127  R3 += 14;
 128 CHECKREG r0, 0x0000000D;
 129 CHECKREG r1, 0x00000008;
 130 CHECKREG r2, 0x00000130;
 131 CHECKREG r3, 0x000000DC;
 132 CHECKREG r4, 0x00000281;
 133 CHECKREG r5, 0xFFFFFE27;
 134 CHECKREG r6, 0x0000006C;
 135 CHECKREG r7, 0x00000066;
 136
 137 R0 = 0x05;
 138 R1 = 0x10;
 139 R2 = 0x20;
 140 R3 = 0x30;
 141 R4 = 0x40 (X);
 142 R5 = 0x50 (X);
 143 R6 = 0x60 (X);
 144 R7 = 0x70 (X);
 145 LSETUP ( start14 , end14 ) LC0 = P4;
 146 start14: R0 += 21;
 147  R1 += -11;
 148 LSETUP ( start16 , end16 ) LC1 = SP;
 149 start16: R6 += 10;
 150 end16: R7 += -12;
 151  R3 += 1;
 152 LSETUP ( start17 , end17 ) LC1 = FP >> 1;
 153 start17: R4 += 31;
 154 end14: R5 += -1;
 155  R3 += 11;
 156 end17: R2 += 41;
 157  R3 += 1;
 158 CHECKREG r0, 0x0000012B;
 159 CHECKREG r1, 0xFFFFFF76;
 160 CHECKREG r2, 0x000001BA;
 161 CHECKREG r3, 0x000000AD;
 162 CHECKREG r4, 0x00000309;
 163 CHECKREG r5, 0x00000039;
 164 CHECKREG r6, 0x00000A38;
 165 CHECKREG r7, 0xFFFFF4A0;
 166
 167 pass