1 //Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp
2 // Spec Reference: dsp32mac and 2 loads
5 .include "testutils.inc"
21 // test the default (signed fraction : left )
30 A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
31 A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ];
32 A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ];
35 CHECKREG r0, 0x000A0000;
36 CHECKREG r1, 0x00F00100;
37 CHECKREG r2, 0x000B0001;
38 CHECKREG r3, 0x00E00101;
39 CHECKREG r4, 0x000A0000;
40 CHECKREG r5, 0x00D00102;
41 CHECKREG r6, 0x92793486;
42 CHECKREG r7, 0xDD2F9BAA;
52 A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ];
53 A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ];
54 A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ];
57 CHECKREG r0, 0x12245618;
58 CHECKREG r1, 0x23256719;
59 CHECKREG r2, 0x00F00100;
60 CHECKREG r3, 0x00C00103;
61 CHECKREG r4, 0x000B0001;
62 CHECKREG r5, 0x67291214;
63 CHECKREG r6, 0x863ABC70;
64 CHECKREG r7, 0xB4EF6A10;
74 A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ];
75 A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ];
76 A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ];
79 CHECKREG r0, 0x00A00105;
80 CHECKREG r1, 0x25256749;
81 CHECKREG r2, 0x000C0002;
82 CHECKREG r3, 0x00D00102;
83 CHECKREG r4, 0x000D0003;
84 CHECKREG r5, 0x000E0004;
85 CHECKREG r6, 0xCBDCD104;
86 CHECKREG r7, 0x0001DAE8;
95 R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ];
96 R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ];
97 R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ];
98 CHECKREG r0, 0xFA99FFDD;
99 CHECKREG r1, 0x0B8A0E79;
100 CHECKREG r2, 0x00610336;
101 CHECKREG r3, 0x000C0002;
102 CHECKREG r4, 0x000B0001;
103 CHECKREG r5, 0x009F0105;
104 CHECKREG r6, 0x000D0003;
105 CHECKREG r7, 0x00230567;